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Lecture 4
EGRE 254
1/26/09
Digital Logic
• Binary system -- 0 & 1, LOW & HIGH,
negated and asserted.
• Basic building blocks -- AND, OR, NOT
Logic levels
• Undefined region
is inherent
– digital, not analog
– Current amplification,
weak => strong
• Switching threshold varies with voltage, temp,
process, phase of the moon
– need “noise margin”
• The more you push the technology, the more
“analog” it becomes.
• Logic voltage levels decreasing with process
– 5 -> 3.3 -> 2.5 -> 1.8 V
MOS Transistors
Voltage-controlled resistance
PMOS
NMOS
CMOS Inverter
Switch model
Alternate transistor symbols
CMOS Gate Characteristics
• No DC current flow into MOS gate terminal
– However gate has capacitance ==> current required for
switching (CV2f power)
• No current in output structure,
except during switching since
– Both transistors partially on
– Power consumption related
to frequency
– Slow input-signal rise times
==> more power
• Symmetric output structure
==> equally strong drive in
LOW and HIGH states
CMOS NAND Gates
• Use 2n transistors for n-input gate
CMOS NAND -- switch model
TTL Electrical Characteristics
TTL LOW-State Behavior
TTL HIGH-State Behavior
TTL differences from CMOS
• Asymmetric input and output characteristics.
• Inputs source significant current in the LOW state,
leakage current in the HIGH state.
• Output can handle much more current in the LOW
state (saturated transistor).
• Output can source only limited current in the HIGH
state (resistor plus partially-on transistor).
• TTL has difficulty driving “pure” CMOS inputs
because VOH = 2.4 V (except “T” CMOS).
EGRE 254
14
Effect of overloading a gate
• In the low state, the output voltage may rise above
the point where it is no longer recognized as a
logic “0”.
• In the high state, the output voltage may drop to
the point that it is no longer recognized as a logic
“1”.
• The input to output propagation delay may
increase beyond specifications.
• The temperature of the IC may increase, thereby
reducing reliability and eventually causing failure.
Unused inputs
• Sometimes not all gate inputs are used.
Unused TTL input usually assume a value of “1”.
Read Chapter 3
• Pay particular attention to the practical
information in 3.4 - 3.13