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Memory • It’s all about storing bits--binary digits • Vacuum tubes, CRTs, drums, disks, core, ICs • Issues of size, cost, speed • Semiconductor memories (chips) Memory • How to store • How to organize--so as to be able to “store” a bit (or byte or word) and then find it again • How to associate an address with a “set” of bits Processor k-bit address bus MAR n-bit data bus MDR Memory Up to 2 k addressable locations Word length = n bits Control lines ( R/ W , MFC, etc.) Figure 5.1. Connection of the memory to the processor. Memory • Memory access (read) address MAR MAR bus memory READ bus memory bus data processor bus MFC MDR bus Memory • Memory access time: – Time from Read issued to MFC received • Memory cycle time: – Time between two successive reads Memory • Obviously, the speed of the processor depends on the speed of the memory • Random Access Memory (RAM) simply means that access time is fixed (and the same) for all memory locations (addresses) b7 b¢7 b1 b¢1 b0 b¢0 W0 • • • FF A0 A2 Address decoder • • • A1 W1 FF • • • • • • • • • • • • • • • • • • Memory cells A3 • • • W15 Sense / Write circuit Data input/output lines: b7 Sense / Write circuit Sense / Write circuit b1 R/W CS b0 Figure 5.2. Organization of bit cells in a memory chip. small (very) example (128 bit chip) 16 words of 8 bits each (16 x 8) b7 b¢7 b1 b¢1 b0 b¢0 W0 • • • FF A0 A2 Address decoder • • • A1 W1 FF • • • • • • • • • • • • • • • • • • Memory cells A3 • • • W15 Sense / Write circuit Data input/output lines: b7 Sense / Write circuit b1 Sense / Write circuit R/W CS b0 Figure 5.2. Organization of bit cells in a memory chip. W 0 A0 A1 A2 A3 Address decoder W 1 • • • W 15 word lines four input, sixteen output decoder 4 address lines, 16 word addresses bit lines b 7 b . . • • • • • • . . W1 (one bit) • • • W 15 Sense / Write circuit data output lines memory cell • • • word lines • • • W0 7 b7 R / W of course CS bit 7 of the selected word chip select for multi-chip memory bit lines bit lines b 7 b • • • • • • • • • . . . • • • . W1 • • • • • • W 15 Sense / Write circuit data output lines • • • . . b7 0 • • • . . • • • word lines b • • • W0 b 0 7 Sense / Write circuit b0 b7 b¢7 b1 b¢1 b0 b¢0 W0 • • • FF A0 A2 Address decoder • • • A1 W1 FF • • • • • • • • • • • • • • • • • • Memory cells A3 • • • W15 Sense / Write circuit Data input/output lines: b7 Sense / Write circuit Sense / Write circuit b1 R/W CS b0 Figure 5.2. Organization of bit cells in a memory chip. small (very) example (128 bit chip) 16 words of 8 bits each (16 x 8) b7 b¢7 b1 b¢1 b0 b¢0 W0 • • • FF A0 A2 • • • A1 W1 FF Address decoder • • • • • • • • • • • • • • • • • • Memory cells A3 • • • W15 Sense / Write circuit Data input/output lines: b7 Sense / Write circuit b1 Sense / Write circuit R/W CS b0 128 bit chip, 16 words of 8 bits each (16 x 8) 4 address lines 8 data lines R / W line chip select line power ground 16 external connections Chip with 1024 Memory Cells • Could be 128 x 8 – Same as the 16 x 8, but with more word lines W 0 A0 A1 • • • A7 Address decoder W 1 • • • W 127 word lines 8 data lines 4 more address lines, total of 20 external connections Chip with 1024 Memory Cells • Or, it could be 1024 x 1 W 0 A0 A1 • • • A9 Address decoder W 1 word lines • • • W 1023 (1 bit each) 1 data line 2 more address lines, but only 1 data line, total of 15 external connections 5-bit row address W 0 W 1 5-bit decoder W 31 32 x 32 memory cell array 10-bit address 32-to-1 output multiplexer and input demultiplexer 5-bit column address Data input/output (1 bit) Figure 5.3. Organization of a 1K 1 memory chip. Sense/Write circuitry R/ W CS Multiplexer 2 lines to choose one of the 4 inputs as its output 2 lines to choose one of the 4 inputs as its output 5-bit row address W 0 W 1 5-bit decoder W 31 32 x 32 memory cell array 10-bit address 32-to-1 output multiplexer and input demultiplexer 5-bit column address Data input/output (1 bit) Figure 5.3. Organization of a 1K 1 memory chip. Sense/Write circuitry R/ W CS Static Memory • Static: retains its state (content) as long as power is applied – and, of course, loses it if powered off (volatile) • SRAM: static ram – fast – expensive b b T 1 T2 X Y latch Word line Bit lines Figure 5.4. A static RAM cell. Transistors in the circuit are effectively switches T Voltage = 0 (ground), open switch T Voltage = Vs, closed switch If the cell represents a 1, for example b 0 1 T 1 b T2 X Y If the Word line goes high (read), then b = 1, (high) b = 0, (low) latch If the Word line is low, nothing on the bit lines sense line sets output high Word line Bit lines to sense/write circuit Figure 5.4. A static RAM cell. If the cell represents a 1, for example b 0 1 To write (say 0), put b low, b high, set Word line high, latch changes T 1 b T2 X Y latch Then, if the Word line goes high (read) b = 0, b = 1 Word line Bit lines to sense/write circuit Figure 5.4. A static RAM cell. CMOS SRAM • Complementary Metal Oxide Semiconductor • Uses both “P type” and “N type” transistors Vsupply Vsupply Vsupply R R R Vout gate Vout gate Vout drain drain S (a) Vin T source (b) NMOS--closed when Vin raised An inverter circuit. Vin T source (c) PMOS--open when Vin raised b b Vsupply T3 T4 T2 T1 X Y T 5 T 6 Word line Bit lines Figure 5.5. An example of a CMOS memory cell. CMOS SRAM • Volatile • Low power consumption--no current flows except when being accessed • Fast--access times of a few nanoseconds • Expensive (6 transistors per cell) Dynamic Ram (DRAM) • Simpler cells, higher density • 1 million to 16 million bits or more per chip • Less expensive • But, DRAM cells do not retain their state • Must be refreshed periodically Bit line Word line capacitor is charged to write a 1 (voltage applied to Word line and to the Bit line) T C charge on the capacitor will discharge over time Figure 5.6. A single-transistor dynamic memory cell Bit line Word line If a Read detects a voltage on the capacitor above the “threshold, ” it “sees” a 1, and drives the bit line to full voltage and recharges the capacitor T If a Read detects a voltage on the capacitor below the “threshold, ” it “sees” a 0, and drives the bit line to ground and fully discharges the capacitor C Refreshes whenever read Refresh circuit will periodically read all cells Figure 5.6. A single-transistor dynamic memory cell 4096 lines RAS Row address latch 12 bits to select one of the 4096 rows Row decoder 4096 x (512 x 8) cell array 4096 lines A 20-9 / A8 - 0 Sense / Write circuits Column address latch 9 bits to select one of the 512 bytes in a row CAS CS R/ W Column decoder D 7 D 0 the selected byte Figure 5.7. Internal organization of a 2M x 8 dynamic memory chip. 16 megabits, 2 million bytes Row Address Strobe RAS 1 12 bit row address applied, latched on RAS Row address latch 21 bit address on 12 lines (reduces external connections) Row decoder 4096 x (512 x 8) cell array Sense / Write circuits 2 9 bit column address applied, latched on CAS Column address latch CAS Column Address Strobe Column decoder D 7 D 0 the selected byte CS R/ W DRAM • Possible to leave row selected (all 512 bytes on sense lines) • Then rapidly retrieve successive bytes by changing column addresses • Result is a “fast page mode” for “blocks” or “pages” of bytes where appropriate (such as cache loading, disk transfer) • Or, synchronous DRAM, SDRAM SDRAM • Can operate in different modes • “Burst” modes of different lengths • Can transfer “blocks” of data on single Read or Write Refresh counter Row Row/Column address Clock RAS CAS R/ W CS Clock pulses cause “counting” to select successive columns address latch Column address counter Mode register and timing control Row decoder Column decoder Cell array Read/Write circuits & latches Data input register Data output register Data Figure 5.8. Synchronous DRAM. Entire row can be addressed and put into latches Successive columns put into output register on successive clock pulses Clock R/ W RAS CAS Address Row Col Data row address latched 2 cycles to activate selected row D0 column address latched D1 D2 D3 1 cycle to put data on data lines Figure 5.9. Burst read of length 4 in an SDRAM. column address automatically incremented by memory control each cycle Larger Memories Using Multiple Chips 512K x 8 memory chip 19 bit address on chip 8-bit data input/output chip select (2 bits) 4 chips 2 million 32-bit words 21 bit address 19-bit internal chip address A0 21-bit addresses A18 A19 A20 16 chips 2-bit decode r 512K x 8 memory chip D31-24 D23-16 D 15-8 D7-0 Figure 5.10. Organization of a 2M 32 memory module using 512K 8 static memory chips (16 chips). 19-bit internal chip address A0 4 chips for each 32 bit word A18 A D31-24 D23-16 D 15-8 D7-0 512K x 8 memory chip Figure 5.10. Organization of a 2M 32 memory module using 512K 8 static memory chips (16 chips). 19-bit internal chip address A0 21-bit addresses A18 A19 A20 16 chips 2-bit decode r 512K x 8 memory chip D31-24 D23-16 D 15-8 D7-0 Figure 5.10. Organization of a 2M 32 memory module using 512K 8 static memory chips (16 chips). Memory controller does the multiplexing of row and column and issues strobe signals Processor sends all bits of address Row/Column address Address RAS R/ W Processor Request Memory controller CAS R/ W CS Clock Clock Data Figure 5.11. Use of a memory controller. Memory Row/Column address Address RAS R/ W Processor Request Memory controller CAS R/ W Memory CS Clock Clock Data Memory controller provides the refresh control if not done on the chip Refreshing typically once every 64 ms. At a cost of .2ms Less than .4% overhead Figure 5.11. Use of a memory controller. ROM: Read Only Memory Bit line Word line T P Not connected to store a 1 Connected to store a 0 Figure 5.12. A ROM cell. PROM: Programmable Read Only Memory Bit line Word line T P A PROM cell. Manufactured connected (storing 0), but the connection is a “fuse” and can be burned out with a high current to change it to a 1 EPROM: Erasable Read Only Memory Bit line Word line T P Connection to ground always made An EPROM cell. Transistor can have a charge put into it that causes it to remain permanently open (programmed to be a 1) Can be erased with ultraviolet light EEPROM: Electrically Erasable PROM Cells erasable selectively vs. EPROM, erase all Flash Memory Similar to EEPROM--each cell a single transistor with a “trapped” charge Read individual cells, write in blocks Greater density, low power consumption, small, cheap Can substitute for disks (up to a gigabyte?) higher cost, but portable Processor Increasing size Registers Increasing speed Primary cache L1 Secondary cache L2 Main memory Magnetic disk secondary memory Figure 5.13. Memory hierarchy. Increasing cost per bit Processor Increasing size Registers always on the processor chip Primary cache L1 Secondary cache L2 Main memory cache usually SRAM--faster but more expensive may also be on the processor chip main usually DRAM-cheap enough to be large Magnetic disk secondary memory Figure 5.13. Memory hierarchy. Cache Memories • Main memory (still) slow in comparison to processor speed • Main memory constrained by packaging, electronic characteristics and costs • Cache memory on the processor chip typically ten times faster than main memory Locality of Reference • Programs tend to spend their time “focused” on particular groups of instructions – Loops – Frequently called procedures • “Localized” areas of programs executed repeatedly during some time period • Much (most?) of program not accessed during some time period Locality of Reference • Temporal – Recently executed instruction likely to repeat soon – When first accessed, move to cache where it will be when referenced again • Spatial – Instructions near an executed instruction likely to be executed soon – When fetching an instruction from memory, move its neighbors into cache as well blocks of memory transferred to (and from) cache Processor Cache Main memory processor accesses instructions and data in the cache if there (a “hit”), in main memory if not (a “miss”) Figure 5.14. Use of a cache memory. Writing to Cache • Write through – Cache copy and main memory copy updated simultaneously – May repeatedly update the same word in main memory unnecessarily • Write back – Update cache only – Mark cache block “dirty” or “modified” – Copy it back to main memory when another block needs the cache space Cache Management • Mapping – Determination of where in the cache the blocks (cache lines) of main memory are to be placed • Replacement – Determination of when to replace a block in cache with another block of main memory • Coherency – Assurance that no problems arise from cache version differing from main memory version Direct Mapping Example 64K main memory 16 bit address (word addressed only) View as 4096 blocks of 16 words each Cache of 128 blocks of 16 words 0-31 which block “assigned” to this position is in the cache 0--127 which block in cache 0-15 which word in block The 16-bit address Direct Mapping Example Main memory blocks 0, 128, 256, etc to block 0 of cache Main memory blocks 1, 129, 257, etc to block 0 of cache Tags are searched “associatively” to find the referenced block Any block of main memory can be put in any block in the cache Cache tag tag tag Main memory Block 0 Block 1 Block 0 Block 1 Block i Block 127 Tag Word 12 4 Block 4095 Main memory address Figure 5.16. Associative-mapped cache. Processing units L1 instruction cache L1 data cache Bus interface unit System bus Cache bus L2 cache Main memory Input/Output Figure 5.24. Caches and external connections in Pentium III processor. k bits Module ABR DBR m bits Address in module ABR Module 0 DBR MM address ABR DBR Module n- 1 Module i (a) Consecutive words in a module m bits k bits Address in module ABR DBR Module 0 ABR Module DBR Module i MM address ABR DBR Module 2k - 1 (b) Consecutive words in consecutive modules Figure 5.25. Addressing multiple-module memory systems. Processor Virtual address Data MMU Physical address Cache Data Physical address Main memory DMA transfer Disk storage Figure 5.26. Virtual memory organization.