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Transcript
Adv. Radio Sci., 5, 285–290, 2007
www.adv-radio-sci.net/5/285/2007/
© Author(s) 2007. This work is licensed
under a Creative Commons License.
Advances in
Radio Science
Analog circuits using FinFETs: benefits in speed-accuracy-power
trade-off and simulation of parasitic effects
M. Fulde1 , J. P. Engelstädter2,3 , G. Knoblinger2 , and D. Schmitt-Landsiedel1
1 Institute
of Technical Electronics, Technical University Munich, Germany
Technologies AG, Villach, Austria
3 Department of Electrical Engineering, RWTH Aachen University, Aachen, Germany
2 Infineon
Abstract. Multi-gate FET, e.g. FinFET devices are the
most promising contenders to replace bulk FETs in sub45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials
(e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog
device properties significantly. First measurements indicate
enhanced intrinsic gain (gm /gDS ) and promising matching
behavior of FinFETs. The resulting benefits regarding the
speed-accuracy-power trade-off in analog circuit design will
be shown in this work. Additionally novel device specific
effects will be discussed. The hysteresis effect caused by
charge trapping in high-k dielectrics or self-heating due to
the high thermal resistor of the BOX isolation are possible
challenges for analog design in these emerging technologies.
To gain an early assessment of the impact of such parasitic
effects SPICE based models are derived and applied in analog building blocks.
1
Introduction
Scaling limitations of standard planar bulk CMOS technologies such as short channel effects or leakage currents enforce the introduction of new device concepts like siliconon-insulator (SOI) and/or multi-gate transistors.
Especially 3-dimensional FinFET devices as shown in
Fig. 1 offer a large variety of interesting features. Here
the transistor consists of vertical (fully-depleted) Si fins
on a buried oxide (BOX), surrounded by the gate stack.
The channel width per fin of this tri-gate device results in
W =2Hfin +Wfin . FinFET devices combine the advantages of
fully depleted (FD) SOI devices with the features of a multiCorrespondence to: M. Fulde
(fulde@tum.de)
gate device. So they show low short channel effects (SCE),
however the requirements on the Si layer thickness (i.e. the
fin height) on top of the BOX are relaxed compared to planar
(single-gate) FD devices. On the other hand the fin width has
to be chosen as small as possible (Wfin ≤2/3Lmin ) to keep the
short channel effects under control, (Colinge, 2004). Using
small fin pitches (i.e. ≤2Hfin +Wfin ) enables comparable or
even higher area efficiency in terms of the current per device
width ratio. Table 2 shows an example for a prototype FinFET technology, targeting a 45 nm LP process, (Schulz et al.,
2005).
Of course also novel process features can be implemented
in a FinFET technology. Metal gates eliminate poly depletion effects and enable undoped Si fins. HALO implants are
no longer necessary due to the low SCE. High-k dielectrics
can be used to reduce gate tunneling currents while bringing
up other new issues such as increased flicker noise or reduced
mobility. The introduction of these new materials and device
concepts implicates changes in analog transistor characteristics as output resistance or matching behavior. Sect. 2 covers
the basic analog transistor properties of FinFETs compared
to standard bulk devices. Also their specific impact on circuit
design is discussed. New materials and device architectures
cause also new effects, such as transient variations in transistor current due to self heating or charge trapping. In Sect. 3
these effects are shown, concerning their impact on transistor behavior, modeling aspects and their influence on analog
circuits.
2
Analog device properties and impact on circuit design
The feasibility of digital and analog multi-gate circuits has
already been proven, (Knoblinger et al., 2005; Pacha et al.,
2006). But these circuits do not take advantage of special
multi-gate device features, as discussed in this section. The
FinFET devices presented here are based on the technology
Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.
286
M. Fulde et al.: Analog circuits using FinFETs
−3
W FIN
1
(a)
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11111111111111111
0.8
2
10
ds
0.6
m
g /g
gm [S/um]
SI−BODY
BOX
10
n − fin FET
n − bulk FET
GATE
HFIN
3
x 10
0.4
1
10
0.2
(b)
0
(a)
n − fin FET
n − bulk FET
0
−1
10
gate length [um]
10
0
10
(b)
−1
10
gate length [um]
Fig. 1. Schematic X-section (a) and TEM image (b) of FinFET.
Fig. 2. gm and gm /gds of bulk- and FinFET.
Table 1. Example for FinFET technology.
gm /gDS here. Figure 2.1 shows that the gain of the FinFET
is improved, despite the lower gm . For typical analog device dimensions the gain is about 2–10 times higher. Taking
gm and gDS into account we conclude that FinFETs are best
suited for low power analog circuits with frequencies below
10 GHz.
Technology features
Wfin [nm]
Hfin [nm]
Lmin [nm]
Gate electrode
Dielectric
Fin doping [cm−3 ]
Electrical features
Lgate [nm]
VDD [V]
ION [µA/µm]
IOFF [nA/µm]
S [mV/dec]
DIBL [mV]
30
60
45
TiSiN
HfSiON
1015
NMOS
60
1.0
560
1.4
69
46
PMOS
60
1.0
330
0.027
72
44
shown in Table 2, the bulk devices are based on a comparable
45 nm process.
2.1
Small signal parameters
The transconductance gm and the output conductance gDS
are the basic DC transistor properties that determine the performance of analog circuits. Figure 2.1 compares gm of FinFET and bulk nFET at VGS =VT +200 mV and VDS =VDD .
The gm of the FinFET is reduced for short channel lengths
up to 30%. This is attributed to the lowered mobility on the
rough fin sidewall and the high resistance of the connection
from the source-drain landing pads to the active channel region under the gate. Lowered gm values implicate lowered
transit frequency values and decreased RF performance. A
possible solution for this issue is a selective epitaxial growth
(SEG) process to fill the gaps between gate and source-drain
pads and to reduce the high source-drain resistance.
The output conductance of FinFETs is expected to be very
low due to the missing HALO implants. HALO implants
introduce an additional barrier at the drain side of the channel region that can be modulated by the drain-source voltage. This effect degrades significantly the output resistance
of bulk devices in modern CMOS technologies. For a fair
comparison we use the intrinsic transistor gain defined as
Adv. Radio Sci., 5, 285–290, 2007
2.2
Benefits in speed-power trade-off
To investigate the benefits of the improved intrinsic gain on
circuit level a standard two stage Miller compensated OTA is
simulated. The following specifications are used: DC voltage
gain AV 0 ≥50 dB, gain bandwidth product GBW ≥10 MHz
for a 5pF capacitive load and a phase margin of 60◦ . To compare FinFET and bulk implementation a figure-of-merit is
defined as gain bandwidth to power ratio: FOM=GBW/P .
The starting point of the comparison is a bulk design using only 3Lmin devices that fulfills the given specifications.
This design is compared to a FinFET implementation using devices with the same channel length of 3Lmin . Due to
the high intrinsic transistor gain, the FinFET version shows
an improved voltage gain (about 30 dB higher) and reaches
the same gain bandwidth product, see the Bode diagram in
Fig. 3.
As the specifications do not require such a high gain, the
FinFET implementation can use shorter channel lengths to
reach higher gm values. The improved gm can then be used to
enhance the gain bandwidth product or to decrease the power
consumption. Figure 3 shows two FinFET implementations
using devices with 1.4Lmin channel length. Both OTAs have
a voltage gain of around 50dB, while one is optimized for
high gain bandwidth and the other for low power. Table 2
shows the quantitative results of the comparison. Using the
improved output conductance the FOM of the FinFET implementation can be improved by about 30%, although the gm
is reduced.
2.3
0
10
Matching behavior
Random variations such as fluctuations of channel/gate dopants, oxide charge or surface roughness lead to current mismatch of nominal identical devices. In today’s CMOS technologies the mismatch of the threshold voltage VT is the
dominant effect. The variation of VT can be approximated
www.adv-radio-sci.net/5/285/2007/
M. Fulde et al.: Analog circuits using FinFETs
287
7
Table 2. Characteristic values of different implementations.
3 Lmin
bulk
3 Lmin
FinFET
1.4 Lmin
FinFET
1.4 Lmin
FinFET
GBW [MHz]
AV 0 [dB]
P [W]
F OM
Improvement
10.8
48.4
53.2
0.203
–
10.6
81.3
55.6
0.191
–6%
14.7
47.1
56.8
0.259
+28%
10.4
47.6
41.9
0.248
+22%
6
5
AVT /mVµm
Version
4
3
2
n − bulk FETs / poly gate
n − FinFET / metal gate
p − FinFET / metal gate
1
90
3xl
min
80
70
0
0
fast fin FET
low power fin FET
60
AV [dB]
bulk FET
3xlmin fin FET
2
3
4
tox /nm
5
6
7
Fig. 4. Matching constant in different technology nodes (Gustin
et al., 2006; Parvais et al., 2006; Decoutere, 2006).
50
40
30
20
10
0
2
4
10
6
10
10
f [Hz]
Fig. 3. Bode diagram of different implementations.
AV
as σVT = √ T , (Pelgrom et al., 1989). AVT is a technology
WL
constant proportional to
√ the oxide thickness and the channel doping: AVT ∝ tox 4 ND . Thus metal gate FinFETs with
undoped body are expected to show good matching behavior.
This assumption can be proven by measurements as shown in
Fig. 4. Compared to bulk devices with poly gate, the matching constant of FinFETs with metal gate amounts roughly to
the half. It is important to note that the matching behavior
degrades for very narrow fins in the current state of technology. Here other effects are dominant, e.g. the variations of
the source-drain resistance, gate misalignment or line edge
and sidewall roughness. Technology optimization is still necessary. E.g. SEG could improve the matching behavior by
decreasing the source-drain resistance.
2.4
1
Benefits in speed-accuracy-power trade-off
Of course matching is one of the most important device properties for analog circuit design. It can be shown that in many
cases the speed-accuracy-power trade-off is limited in general by the matching behavior (Kinget and Steyaert, 1996):
Speed · Accuracy
1
∝
Power
Cox A2VT
www.adv-radio-sci.net/5/285/2007/
(1)
Obviously an improved matching constant AVT can be used
to reduce the area consumption or enhance the resolution
without the drawback of increased power consumption. As
concrete example for this relationship we use a current
source in a current steering DA converter. The DAC specifications for resolution and yield determine the tolerable cur)
rent variation σ (I
of the current sources (van den Bosch
I
et al., 2001). These matching requirements can be converted
into area requirements:
!
4A2VT
1
2
W Lcurrent source = (2)
2 Aβ +
(VGS − VT )2
)
2 σ (I
I
Assuming that the mobility mismatch given by A2β is negligible compared to the VT mismatch, a reduction of AVT by
a factor of two enables a reduction of the current source area
by a factor of four.
3
Simulation of parasitic effects
Besides the beneficial analog properties presented above,
FinFETs show some new effects that have to be considered
in the design of analog circuits. As example we discuss self
heating and charge trapping. Both effects lead to transient
variations of the transistor current and influence the behavior
of analog circuits.
3.1
Self heating – modeling and scaling behavior
The local temperature increase of active devices due to their
dissipated power is called self heating (SH). Important transistor parameters, e.g. VT or the mobility µ depend on the
temperature and thus on the dissipated power. For high values of VDS and VGS the reduction of the mobility is the dominant effect, so the transistor current is decreased by SH. Self
Adv. Radio Sci., 5, 285–290, 2007
288
M. Fulde et al.: Analog circuits using FinFETs
Temperature
D
5
2.5
BSIM4
technology 1
technology 2 (scaled)
Temperature
Pdiss
M
G
Rth
2
C th
Rth [K/W]
Power
Ambient Temperature
S
Fig. 5. Self heating equivalent circuit.
Impact of self heating on analog circuit performance
Using the equivalent circuit model, the impact of SH on FinFET circuits is investigated. Rth is obtained from simulations as described above, Cth from measurement and device simulations (Molzer et al., 2006) revealing a time constant of about 100ns and a maximum current reduction of
about 10%. First a single-ended two stage OTA as presented
above is analyzed in terms of it’s transient response. A sinusoidal differential input signal is applied with a frequency of
fsig 1/τth . Figure 3.2 shows the impact of self heating on
the output signal. The signal amplitude is decreased by about
2% through SH whereas the waveform is not affected. This
is confirmed by the spectral analysis of this signal in Fig. 3.2.
The second and third harmonic of the signal are even a touch
lower in case of self heating, which can be explained by the
Adv. Radio Sci., 5, 285–290, 2007
1.5
1
0.5
0
0
200
400
600
gate length [nm]
800
1000
Fig. 6. Impact of technology scaling on Rth .
0
1
w/o self heating
self heating included
w/o self heating
self heating included
−20
Pyy (Vout) [dB]
0.8
Vout [V]
heating is more severe in SOI technologies due to the low
thermal conductivity of the surrounding oxide that acts as
thermal insulator. To quantify SH usually the thermal resistance Rth is used. The time dependence of SH can be
described with the thermal capacitance Cth as shown in the
equivalent circuit model for a transistor with self heating in
Fig. 5. The equivalent circuit is based on electro-thermal
coupling: the dissipated power is sensed and applied to the
thermal RC network which determines the actual device temperature which then again influences the transistor parameters. To avoid complex measurements or device simulations
for the extraction of the thermal resistance, in (Bertolissi,
2004) an alternative approach is shown. Here a thermal network of complex 3d FinFET structures is constructed based
on small building blocks where a analytic calculation of Rth
is possible. This model is used here to investigate the impact
of technology scaling on the thermal resistance. A scenario
with relaxed design rules is compared to a scaled technology
as shown in Fig. 6. Fin dimensions and pitch, metal/contact
dimensions and pitch as well as the BOX thickness are reduced. The thermal resistance of a test device with 2 fins is
increased up to a factor of two in case on the scaled technology, although the density of contacts with high thermal
conductivity increases. So SH will become even more severe
in future SOI technologies.
3.2
x 10
0.6
0.4
−40
−60
−80
−100
−120
(a)
0.2
0
0.5
1
t [s]
1.5
2
−5
x 10
(b)
1
1.5
2
2.5
3
f [Hz]
3.5
4
4.5
5
x 10
Fig. 7. OTA output voltage with and without SH in time (a) and
spectral domain (b).
decreased amplitude of the output signal. Consequently the
impact of SH on the gain and the linearity of the amplifier
is negligible here, although the current of a single transistor can be decreased by nearly 10%. This is attributed to
the bias points typically chosen for amplifiers with moderate
bandwidths. To reach a high gm /ID ratio VGS is typically set
to values in the range of 50 mV–300 mV above VT leading to
quite low current densities.
Next the impact of SH on comparator circuits is shown.
A simple comparator structure with differential input stage,
MOS diode loads and common source output is used as example. The adjacent latch is not considered here. In the simulation the differential input voltage is pulsed from a large
(positive) value to a small (positive) residual voltage Vres , see
Fig. 3.3. Without self heating, the comparator output voltage
follows the input as intended. If self heating is included, the
differential output voltage is negative for a certain period of
time. This can be explained with the history of the comparator. Before the step of the input voltage, the devices providing the positive part of the differential output signal suffer
much more from self heating than the devices providing the
negative part. This situation remains for a short time after
the step to small input values near common mode, yielding
to strong thermal mismatch and a wrong comparator decision
if the latch is activated at this point of time, see Fig. 3.3. The
www.adv-radio-sci.net/5/285/2007/
M. Fulde et al.: Analog circuits using FinFETs
0.62
289
0.62
Voutp
Voutp
Voutn
0.61
Vout [V]
V
0.59
0.58
6
Measurement: pulsed
Simulation: pulsed
4
0.59
2
2.5
3
3.5
t [s]
4
4.5
5
−7
x 10
x 10
0.6
0.58
(b)
2
2.5
3
3.5
t [s]
4
4.5
5
−7
x 10
ID [A]
out
[V]
Vinn
0.6
(a)
−4
Voutn
0.61
Vinp
Fig. 8. Comparator input and output voltage without SH (a) and
with SH (b) included.
2
0
D
−2
0
BSIM4
M
G
V GS*x
RS
CS
VShift
VGS [V]
1
1.5
Fig. 10. Measurement and simulation of charge trapping effect.
VShift
S
Fig. 9. Charge trapping equivalent circuit.
maximum residual voltage which causes wrong decisions is
depending on the input signal, the comparator gain and the
sampling time. In this scenario a Vres of 0.16 mV leads to a
wrong decision for about 50ns. Assuming a reference voltage
of 1V, self heating limits the performance of this comparator to a resolution of 12bit or sampling frequencies below
20 MHz. Thus SH is a potential issue for high speed, high
resolution AD converters.
3.3
0.5
the transistor current. Therefore the impact of charge trapping on circuit behavior is comparable. The linearity and
gain of operational amplifiers is nearly not affected because
the input devices see only a small signal oscillation of the
gate-source voltage around the bias point. So the amount
of charge trapping is almost constant over time. However
charge trapping can cause erroneous comparator decisions as
discussed above. The maximum residual voltage Vres that is
necessary to modify the comparator decision is in the range
of the maximum steady-state VT shift. That means Vres can
be much higher than in case of self-heating, e.g. in the mV
regime. Fulde et al. (2006) shows how a dynamic VT shift
of a few mV can degrade the resolution of a 12bit SAR converter.
Charge trapping – modeling and impact on analog circuits
4
Another -not FinFET specific- effect is charge trapping in
high-k materials. Under strong positive (in case of nFET)
gate bias charges tunnel through the dielectric barrier and occupy free states in the dielectric material. Thereby the threshold voltage of the device is increased. Detrapping of charges
is possible leading to a hysteresis effect as shown in Fig. 10.
Material properties such as the dielectric itself (e.g. HfO2 )
or the interface layer, temperature and bias conditions determine the amount of trapped charges (Ribes et al., 2005).
Measured VT shifts reach values in the range of 100 mV,
while values around 10 mV are supposed to be tolerable for
digital circuits. Time constants are reported from µs up to
ms. For circuit simulations, an equivalent circuit model can
be used (Fulde et al., 2006; Tewksbury and Lee, 1994) as
shown in Fig. 9. The gate-source voltage is sensed and used
to calculate the steady-state VT shift via a voltage controlled
voltage source. This voltage is applied to a RC network
that creates an exponential time dependence and then subtracted from the gate-source voltage. Similar to the self
heating effect, charge trapping causes transient variations of
www.adv-radio-sci.net/5/285/2007/
Conclusions
FinFETs offer a lot of interesting device features and show
beneficial analog device properties. Primarily the low output
conductance and the good matching behavior can be used to
improve the figure-of-merit of typical analog applications as
operational amplifiers or AD/DA converters. Nevertheless
technology optimization, e.g. SEG, is still needed to eliminate parasitic effects like the high source-drain resistance or
the matching issues for very narrow fins. Additionally new
effects have to be considered in the design of analog circuits.
Self heating and charge trapping influence transistor behavior
significantly and introduce transient variations. Simple approaches based on equivalent circuit models enable an early
assessment of the impact of such effects on circuit performance, revealing possible limitations for high speed, high
resolution converters.
Acknowledgements. The authors would like to thank A. Kerber,
F. Bauer, M. Kropfitsch, P. Bogner, C. Kropf and K. von Arnim
for their valuable support.
Adv. Radio Sci., 5, 285–290, 2007
290
References
Bertolissi, L.: Modeling and Simulation of Self-Heating Effects in
Deep Sub-Micron Silicon on Insulator (SOI) Technologies for
Analog Circuits, Ph.D. thesis, Universita Degli Studi di Udine,
2004.
Colinge, J.-P.: Novel Gate Concepts for MOS devices, in: IEEE
Proceedings of the 34th European Solid-State Device Research
conference, ESSDERC, 45–49, 2004.
Decoutere, S.: Perspectives of Downscaled CMOS for RFIC and
mm-wave Applications, in: IEEE MTT-S International Microwave Symposium, 2006.
Fulde, M., Schmitt-Landsiedel, D., and Knoblinger, G.: Transient
Variations in Emerging SOI Technologies: Modeling and Impact
on Analog/Mixed-Signal Circuits, in: Proceedings of the IEEE
International Symposium on Circuits and Systems, ISCAS, 2007.
Gustin, C., Mercha, A., Loo, J., Subramanian, V., Parvais, B., Dehan, M., and Decoutere, S.: Stochastic Matching Properties of
FinFETs, IEEE Electron Device Letters, 27, 846–848, 2006.
Kinget, P. and Steyaert, M.: Impact of transistor mismatch on the
speed-accuracy-power trade-off of analog CMOS circuits, in:
Proceedings of the IEEE Custom Integrated Circuits Conference,
CICC 1996, 333–336, 1996.
Knoblinger, G., Kuttner, F., Marshall, A., Russ, C., Haibach, P.,
Patruno, P., Schulz, T., Xiong, W., Gostkowski, M., Schruefer,
K., and Cleavelin, C.: Design and evaluation of basic analog circuits in an emerging MuGFET technology, in: Proceedings of
the IEEE International SOI Conference, 39–40, 2005.
Molzer et al., W.: Self Heating Simulation of Multi-Gate FETs, in:
IEEE Proceedings of 36th European Solid-State Device Research
conference, ESSDERC, 311–314, 2006.
Adv. Radio Sci., 5, 285–290, 2007
M. Fulde et al.: Analog circuits using FinFETs
Pacha, C., von Arnim, K., Schulz, T., Xiong, W., Gostkowski, M.,
Knoblinger, G., Marshall, A., Nirschl, T., Berthold, J., Russ, C.,
Gossner, H., Duvvury, C., Patruno, P., Cleavelin, R., and Schruefer, K.: Circuit design issues in multi-gate FET CMOS technologies, in: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1656–1665, 2006.
Parvais, B., Gustin, C., de Heyn, V., Loo, J., Dehan, M., Subramanian, V., Mercha, A., Collaert, N., Rooyackers, R., Jurczak, M.,
Wambacq, P., and Decoutere, S.: Suitability of FinFET technology for low-power mixed-signal applications, in: IEEE International Conference on Integrated Circuit Design and Technology,
ICICDT ’06, 1–4, 2006.
Pelgrom, M., Duinmaijer, A., and Welbers, A.: Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits,
24, 1433–1439, 1989.
Ribes, G., Mitard, J., Denais, M., Bruyere, S., Monsieur, F.,
Parthasarathy, C., Vincent, E., and Ghibaudo, G.: Review on
high-k dielectrics reliability issues, Device and Materials Reliability, IEEE Transactions on, 5, 5–19, 2005.
Schulz, T., Xiong, W., Cleavelin, C., Schruefer, K., Gostkowski,
M., Matthews, K., Gebara, G., Zaman, R., Patruno, P., Chaudhry,
A., Woo, A., and Colinge, J.: Fin thickness asymmetry effects
in multiple-gate SOI FETs (MuGFETs), in: Proceedings of the
IEEE International SOI Conference, 154–156, 2005.
Tewksbury, T.L., I. and Lee, H.-S.: Characterization, modeling, and
minimization of transient thresholdvoltage shifts in MOSFETs,
IEEE Journal of Solid-State Circuits, 29, 239–252, 1994.
van den Bosch, A., Borremans, M., Steyaert, M., and Sansen, W.:
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter, IEEE Journal of Solid-State Circuits, 36, 315–324, 2001.
www.adv-radio-sci.net/5/285/2007/