Download Conceptual Design Review

Conceptual Design Review:
Design of an Integrated Solar Cell Array to Power a Solar Ear Hearing Aid
Battery Recharger
Chrissa Blattner – Materials Engineering
Scott Carey – Electrical Engineering
Jared Myren –Materials Engineering
Faye Siao – Materials Engineering
December 6, 2010
Advisor: Dr. Richard Savage
Application
The intended goal of use for this project is to create a solar cell array to power a battery
recharger, specifically for hearing aid devices. Our goal is to design, fabricate and test a small solar cell
array capable of generating power for a portable hearing aid recharger. The stakeholders of our project
are the future users of the product. At least two thirds of the 250 million people who experience hearing
loss do not have access to advances in hearing aid technology and live in developing countries (Kumar
2001). We want to target the residents of third world countries where power sources and/or batteries are
not readily available.
In order to better understand the specific requirements of our stakeholders, we conducted an
interview with a local audiologist, Jacqueline M. Carr of Hearing Aids Audiology, Inc. Through this
interview we determined that the current market for hearing aid rechargeable batteries is not very
prominent. GN Resound, one of the world’s largest providers of hearing aids and audiological
instrumentation, had previously released a rechargeable device for hearing aids. It was discontinued in
February 2009 with complaints from consumers for the product’s lack of durability. Carr also mentioned
that the alternative and main power source of hearing aids today, button batteries, are also not the most
convenient way to power a hearing aid. The biggest complaint from customers is the fact that these
disposable batteries do not last very long. Each battery, depending on size, can last from a minimum of 35 days to a maximum of 1-2 weeks before a replacement battery is needed. A pack of 6 medium sized
batteries, each lasting about a week, costs about $7.25. Costs to replace these batteries add up quickly,
especially if consumers experience bilateral hearing loss, like most of Carr’s patients.
If our main stakeholders are residents of developing countries, then there are certain obstacles
that our team must overcome in order to help solve this problem. By creating a solar cell array that can
fully charge a battery within 8 hours of direct sunlight we will eliminate the use of disposable batteries and
can transition to using only rechargeable batteries in hearing aids.
Background
A solar cell is built from a p-n junction in a semiconductor material such as silicon, meaning a
material with extra protons (positive charge) is in contact with a material with extra electrons (negative
charge). Energy from a photon of light striking the solar cells knocks the extra valence electrons loose,
allowing it to flow through a circuit to the p-region while a hole simultaneously flows to the n-region. If
individual solar cells are connected together in series, a solar array is created (Figure 1).
Figure 1: Solar cells convert incident sunlight into electric energy.
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The lifespan of most solar cells is at least twenty years. This period is assuming the cell continues
to create electricity without any significant drop in efficiency. On average, solar cells tend to degrade to
about 85% efficiency of their original amount after 25-30 years. Even with this consideration, our device
can decrease costs of owning a hearing aid device by no longer having to constantly purchase batteries.
The circuit of the solar cells must produce enough voltage and current to be able to recharge the hearing
aid batteries. Many different charging methods exist, but the most common methods include normal
(trickle) charging, fast charging, and delta V charging. Trickle chargers provide a very small current to
avoid the risk of overcharging the battery. This method is usually used for nickel-cadmium and nickelmetal hydride cells or batteries (Figure 2).
Figure 2: Charging curves for 1.4V NiMH hearing aid batteries
Constant voltage can be used to charge Lithium-Ion batteries (Figure 3). In all cases, it is
important not to overcharge the batteries. If there is no special circuitry to prevent overcharging, it is
recommended to charge at a rate no faster than about 10% or the rated battery capacity per hour.
Figure 3: Voltage requirements to charge a lithium-ion battery
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In order to maximize the efficiency of our solar cell array we want to deposit an anti-reflective
coating on our solar cells. This is a thin transparent layer on the solar cell that helps increase light
absorption through destructive interference between the light reflected off the surface of the coating and
the substrate. This causes no light to reflect back so all the light input is absorbed by the solar cell.
The previous project done by Jeremy Lenhof and Sadao Takabayashi had some issues with
uneven oxidation in the furnace. We plan to fix this problem by experimenting with dummy wafers on
either side of our test wafer. Hopefully this will create a more even heating gradient across the wafer.
We will fix other problems as they arise throughout the project.
A non-profit organization, The Godisa Trust, currently offers technology and services in third
world countries for the relief of hearing disabilities (McPherson, Brouilette 2004). They have recognized
that hearing aids marketed in developed countries are not suitable for third world countries through
various reasons: high costs of hearing aids/ batteries, lack of availability, lack of local repair or
maintenance, non-durable through shipments and etc. Their aim is to mitigate these problems by
developing products that are more appropriate in these countries’ conditions. An initial idea was to create
a solar aid Behind-the-Ear (BTE) hearing aid using a conventional rechargeable cell (Figure 4), similar to
what this project is aiming for. Their product had gone through field-testing and was found to hold charge
for about 4 days under 6 hours of direct sunlight. Their current products are inexpensive to manufacture,
easy to charge, and use low cost NiMH batteries that are resistant to outside elements and can be sold at
affordable prices in developing countries. What Godisa has developed is similar to what our group is
aiming to develop.
Figure 4: Godisa solar powered battery recharger. (McPherson, Brouilette 2004)
User’s Needs
There are certain performance goals and functional requirements that are required for our design
to meet our users’ needs. To meet the needs of the Solar Ear user, we want the rechargeable package to
be compact, durable, ergonomic, and have an intuitive interface. The Solar Ear package needs to be
compact due to the fact that we want it to be a portable device. The portability of the device would
assume that it is lightweight, easy to carry and ergonomic. The intuitive interface will ease the use of
Solar Ear for our consumers. These needs are especially important if we narrow down the broad span of
our users to children in third world countries.
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Functional Requirements
Based on the user’s need for durability, the package must not yield or break under normal stress.
The material that makes up the housing must be environmentally friendly, cost effective, non permeable
to liquids and strong enough to withstand dropping from at least six feet. The material covering the array
must also be optically clear. When the Solar Ear device is exposed to sunlight or a light source we want it
to be able to produce enough voltage to charge a size 13 NiMH battery and produce enough current to
charge the batteries within a reasonable time span. These functional requirements help ensure the safety
and functionality of the user and our device.
Design Specifications
Table I lists the possible design specifications of the Solar Ear packaged device. These
specifications are currently still being determined and have not been finalized.
Table I: List of Possible Design Specifications for the Packaging of the Solar Ear Device
Packaged Dimensions
Required Voltage
Required Current
Possible Materials for
Casing
127 mm long
152.4 mm wide
25.4 mm deep
3-5 V
20-30 mA
Polycarbonate (PC)
Acrylonitrile Butadiene Styrene (ABS)
Polypropylene (PP)
Polyethylene (PE)
Poly Methyl Methacrylate (PMMA, Acrylic)
System Block Diagram
The solar cell array consists of six main components: the cells, the insulation that separates the
cells, the contacts that connect the cells in series all contained on a single silicon wafer, the external
circuitry, and the device housing (Figure 5).
Figure 5: The six components of the system are responsible for creating and carrying an electric
current to an external charging circuit. The insulation and interconnects ensure that the voltage
created in each cell is kept in the circuit and connected in series
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Cells:
The solar cells are created by a junction between p-type silicon and n-type silicon. Cells are
connected together in series to produce the desired voltage. Each cell is theoretically capable of
producing around 0.5V based on the band gap of silicon. Preliminary testing, however, yielded a
maximum actual voltage of 0.4V. The current generated by each cell is dependent on the area,
approximately 30-40 mA/cm2.
Each cell requires an insulating layer between it and the adjacent cell. This insulation requires
its own area on the silicon wafer. If the cells are only connected in series, each individual cell can be
larger, creating the desired current without wasting additional area on the silicon wafer. Parallel
circuits increase total current, but since the requirements for current are low, they should not be
necessary.
Insulation:
Insulation is required between each cell to make sure the cell does not short circuit. Two different
insulations are going to be used, SU-8 and an oxide layer. An oxide layer will cover the top and
bottom of the cells to protect them from the outside world and support the aluminum contact traces.
SU-8 will be used between the cells. Originally we were going to use SU-8 to cover the top surface
as well, but since SU-8 is not transparent, it would reduce the light absorption, reducing the voltage
created by the solar cell. The SU-8 will provide a flat surface for the sputtered aluminum traces to
form interconnects across. It will be crucial to control the exact spin-on depth of the SU-8 to create a
flat surface between the cells.
Contacts and interconnects:
The contacts of the solar cell connect the cell to the outside world. The contacts are like
terminals on a battery. Interconnects connect each individual cell into an array of cells. The p-region
of one cell is connected to the n-region of another cell. It is very important that the p-region and the nregion of any one cell are not connected together. This would cause a short circuit and render the cell
useless. The contacts will be formed by etching holes in an oxide layer and sputtering down
aluminum. The interconnects will be formed by patterning the aluminum layer. The cells will be
connected with aluminum that will be laid across the insulation layer as described above. The
contacts to the external circuits will be accomplished by either conductive tape strips or by soldered
conductive wires.
SOI (Silicon-on-Insulator) Wafer:
The silicon wafer acts as both the foundation on which the solar cell is created and the material
from which the cell is created. The silicon wafers we will be using are n-type SOI wafers. These
silicon wafers consist of three layers: a silicon base, an oxide layer, and n-type silicon on the top
(Figure 6).
Figure 6: N-type SOI wafers are doped with phosphorous to create a thin, doped layer on top.
External Circuitry:
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We anticipate the current generated by our solar cell to be very small (less than 10% of the
battery capacity) so we will plan on using the trickle charging method to charge the hearing aid
batteries. Since the current is small, there is no danger of overcharging the batteries. We may still
use a diode to prevent leakage current out of the battery when the solar cell is not active. If it turns
out we generate more current than anticipated, we will look at other circuitry options, such as an
integrated circuit (IC) provided by National Semiconductor or Linear Technologies (LT3654).
Device Housing:
The housing needs to protect the circuitry and the wafer while allowing light to reach the cells. It
also must be cheap and easily moldable. The housing will form the shape of the product, which will
be compact and easily held. A possible material of choice is polycarbonate, since it is formable,
strong, optically clear, and relatively cheap. The housing must also allow for input and removal of the
batteries. The housing is what allows the device to function outdoors reliably and without being
damaged.
Conceptual Design Solutions
Our team decided that the most critical component of our device was the connection between the
cells in the array. These interconnects were the primary cause for failure in past years’ projects due to
shorting and disconnects. The problem arises because the cells must be isolated from one another on
the wafer, so bridging the gaps between the cells with sputtered aluminum becomes a challenge. The
previous team’s design is shown below, with shorts and disconnects pointed out (Figure 7).
Figure 7: The previous possible problems areas for disconnects and shorts were at the corners of
the islands containing the junctions.
Last year’s team attempted to bridge the gap between the cells by placing the aluminum along
the bottom of the chamber, shown on the left. This means the aluminum had to start at the top of the cell,
coat the side of the channel down to the bottom, and back up to the top of the next cell. Based on the
optical microscope images shown on the right, the team believed that there were disconnects in the
aluminum traces at the corners. The second possible problem was a short at the junctions where the
insulating layer failed to prevent the aluminum from contacting the positive and negative regions of one
cell.
To address the disconnect issue identified by last year’s team, our design solution involves
depositing the aluminum contacts on top of an insulating SU-8 layer which will be sequestering the cells
from one another. This will eliminate the need for the aluminum to maintain a continuous connection
across a corner. Our design solution solves the shorting problem by doping the p-type regions out to the
edges of each cell. An iteration of this design solution is shown below.
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Figure 8: The SU-8 layer isolates the cells and supports the interconnects. The p-regions are
positioned to eliminate the possibility of a short.
Micro-fabrication of Solar Cells
We have two proposed methods of processing to fabricate the solar cell arrays. Both of the
methods form the aluminum interconnects on top of an insulating SU-8 channel. In the first method, the
channel is created before the p-n junction is doped and diffused. In the second method, the p-n junction is
created first and the channels are formed after. This method requires an additional cycle in the furnace.
See Appendices A and B for full process descriptions. The choice in a final method from these two will
depend on the diffusion rates of the boron to create the p-type regions.
Risk Areas:
The first method has two primary risk areas. First, it will be necessary to thermally grow an oxide
after the boron dopant has been driven in. This could cause excess diffusion and affect the efficiency of
the p-n junctions. Second, the SU-8 in the channels must be flush with the wafer surface. This will require
a high degree of control in the etch rate of SU-8.
The second method has four areas of concern. The first two are the same concerns as method 1.
Third, doping into the channels to create the junctions could create some leakage current (shorts)
between the cells under the SU-8. Fourth, the surface doped in the channel will be covered in SU-8,
which is not optically clear. This reduces the viable junction area, which could reduce the electrical
performance of the cells.
We will begin our fabrication of cell arrays by creating a two-cell module with one interconnect to
evaluate the effectiveness of the proposed processing methods. Using a simple two-cell design will allow
us to pinpoint where problems are occurring and optimize our chosen process to ensure the greatest
probability of success for our final design. Once we have successfully fabricated a two-cell array we can
use this same process and interconnect technique to create modules containing more cells. To ensure
that our solar cell array will produce the voltage necessary to recharge a hearing aid battery, our multi-cell
design will be composed of at most 12 cells in series (Figure 9). By using more cells than necessary to
produce the needed voltage, we can avoid the risk of producing too little voltage if our junctions do not
produce the ideal theoretical voltage of 0.5 V per junction.
2 cells in series
12 cells in series
N-Type
Insulator
Contacts
P-Type
Figure 9: Two designs - one of 2 cells in series and another of a 12 cell array in a 4 X 3 matrix
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Testing Methodology
The goal of the testing methodology is to determine whether or not the end product meets the
performance goals. The performance goals for the solar cell are to produce a total voltage of 3-5 volts
and a total current of 20-30 milliamps. The testing methodology therefore, will define a test that will
determine if each individual wafer meets the performance goals and allow comparisons between separate
wafers and their solar modules.
To test the total current and total voltage, I-V curves will be graphed and created. In this
procedure, a solar cell is placed under a light source to simulate the sun. The light that will be used in this
case is a quartz halogen lamp. The light source has three settings: low, medium, and high. These settings
supply three different amounts of energy to the cell. A light meter will be used to measure the lumens for
each setting. The light source will be placed directly above the solar cell. The solar cell itself will be
placed directly onto the surface of the table. By placing the solar cell flat, the angle of the light onto the
solar cell will be consistent. In addition, the table will act as a heat sink, causing the solar cell to maintain
a consistent temperature throughout testing. The solar cell will be connected to the instrumentation using
4-wire connection to reduce lead resistance errors. Aluminum conducting tape may be used to create a
better connection between the contacts and the wire. The instrumentation will be a Keithley 2400
SourceMeter in series with the solar cell and a variable load to create a circuit (Figure 10).
Figure 10: Method used to test solar cells.
The circuit will be used to measure the current and voltage created by radiance from the light
source. To begin, the light source will be turned on its lowest setting and the lowest variable load will be
used. The instantaneous voltage and current will be measured and recorded. Then the load will be
increased. The new instantaneous voltage and current will be measured and recorded. The voltage and
current will be measured for every load. The voltage and current at each point will be collected in order to
create an IV curve. This curve provides the short circuit current, ISC, the open circuit voltage, VOC, and the
max power, Pmax (Figure 11).
Figure 11: The maximum power achievable in the circuit can be calculated by multiplying the
voltage by the current.
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The conversion efficiency, N, can be determined using the maximum power calculated from the IV curve with the power input,
η = Pm/PIN
Eqn. 1
If the solar cell does not meet the functional requirements for total voltage and total current, additional
tests can be conducted to determine the source of the problem. Instead of attaching the probes to the
contacts at each end of the solar cell array, each individual cell can be manually tested. This would locate
which cells were causing problems. Also, the individual cells could be compared with one another to
determine if the amount of voltage produced by each cell is uniform. If the problem were localized the cell
could be further examined through optical microscopy to determine if flaws with the wafer or the
interconnects were causing a decrease in voltage at that location. If the problem was universal throughout
the wafer, the processing method could be examined to look for sources of error.
Project Plan
The project plan can be divided into three main steps: design, fabricate, and test. These three
steps are dependent on each other; each step being started after the previous step is completed. The
critical path includes the majority of the steps, due to the dependence of each step on the one before it.
The basic plan is to design a circuit, create a mask to process the designed circuit, fabricate the solar
cells with that mask, and then test the solar cells using the stated testing methodology to confirm if the
process worked (Figure 12).
Figure 12: Proposed work breakdown structure.
This basic format will be repeated twice, first to create a two-cell wafer and secondly to create the
multi-cell wafer. The Gantt chart allocates 140 days for the completion of the project (Appendix A).
Working for 3 hours for each of these days, 420 total hours will be needed to complete the project.
The main risk in the project will be successfully connecting the p-n junctions in series. Therefore,
most of the risk lies in the processing of the wafers. To mitigate risk the risk of excess diffusion, our team
will customize the diffusion times and temperatures for the original driving step to diffuse boron. A second
major risk is the effective removal of SU-8 to ensure that the insulation is level with the top of the
junctions. The SU-8 needs to be level so that the aluminum contacts will not be forced to form over
corners. A test of etch rates of SU-8 can be conducted in order to determine the appropriate etching time
of SU-8 required to produce a flat surface for the interconnects during the fabrication process.
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References
Battery Chargers and Charging Methods. (n.d.). Electropaedia, Energy Sources and Energy Storage,
Battery and Energy Encyclopaedia and History of Technology. Retrieved December 4, 2010,
from http://www.mpoweruk.com/chargers
Battery Charging. Retrieved Dec. 4, 2010, from http://www.national.com/appinfo/power/files/f7.pdf
Charging methods. (1997). Retrieved from
http://www.wppltd.demon.co.uk/WPP/Batteries/Charging_Methods/charging_methods.html
Kumar, S. (2001). WHO tackles hearing disabilities in developing world. Lancet, 358:9277, 219.
Lt3652 - power tracking 2a battery charger for solar power. (n.d.). Retrieved from
http://www.linear.com/pc/productDetail.jsp?navId=H0,C1,C1003,C1037,C1078,C1089,P89360
Markvart, T., & Castañer, L. (2005). Solar cells materials, manufacture and operation. Oxford: Elsevier
Advanced Technology.
McPherson, B. & Brouilette, R. (2004). A Fair Hearing for All: Providing Appropriate Amplification in
Developing Countries. Communications Disorders Quarterly. 25:4. 219-223.
"Speaking with an Audiologist: Jacqueline M. Carr." Personal interview. 3 Nov. 2010.
SPREE - Future Students - What are Photovoltaic Devices - How do they work?. (n.d.). School of
Photovoltaic and Renewable Energy Engineering, UNSW. Retrieved December 4, 2010,
fromhttp://www.pv.unsw.edu.au/future-students/pv-devices/how-they-work.asp
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Appendix A: Method 1 for the Fabrication of Solar Cells:
Purchase SOI wafers with n-type
doped silicon.
Step 1
N-Type-
Oxide Layer
Silicon Base
Thermally grow an oxide layer on
top of the n-type silicon.
Step 2
Thermally Grown Oxide
N-Type-
Oxide Layer
Silicon Base
Mask the oxide layer and etch to
create an exposed area for the ptype doped regions.
Step 3
Boron Dopant
N-TypeOxide Layer
Silicon Base
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Spin on and diffuse boron to create
the p-type regions.
Step 4
P-Type+
P-Type+
N-TypeOxide Layer
Silicon Base
Etch off the oxide layer (if needed).
Step 5
P-Type+
P-Type+
N-TypeOxide Layer
Silicon Base
Grow another oxide layer.
Step 6
P-Type+
P-Type+
N-TypeOxide Layer
Silicon Base
12
Mask and etch the oxide layer
between the cells.
Step 7
P-Type+
P-Type+
N-TypeOxide Layer
Silicon Base
Deep etch the silicon to create the
channel for the insulating barrier
between the cells.
Step 8
P-Type+
P-Type+
N-Type-
N-TypeOxide Layer
Silicon Base
Spin on SU-8 to act as the insulator
between the cells.
Step 9
P-Type+
SU-8
N-Type-
P-Type+
N-TypeOxide Layer
Silicon Base
13
Remove the SU-8 that is on top of
the oxide layer. This process is one
of our major risks. We have to
remove just enough to eliminate the
residual SU-8 on top of the oxide
layer but not so much that it cuts
into the insulating channel.
Step 10
P-Type+
SU-8
N-Type-
P-Type+
N-TypeOxide Layer
Silicon Base
Mask and etch the oxide layer to
create the contact points.
Step 11
Oxide Layer
P-Type+
SU-8
N-Type-
P-Type+
N-TypeOxide Layer
Silicon Base
Sputter on aluminum to create the
interconnects.
Step 12
Oxide Layer
P-Type+
SU-8
N-Type-
P-Type+
N-TypeOxide Layer
Silicon Base
14
Pattern the aluminum traces to
create the finished product.
Step 13
Oxide Layer
P-Type+
SU-8
N-Type-
P-Type+
N-TypeOxide Layer
Silicon Base
15
Appendix B: Method 2 for the Fabrication of Solar Cells:
Purchase SOI wafers with n-type
doped silicon.
Step 1
N-Type-
Oxide Layer
Silicon Base
Grow an oxide layer on top of the ntype silicon.
Step 2
Thermally Grown Oxide
N-Type-
Oxide Layer
Silicon Base
Mask and etch the oxide layer in
anticipation of creating an insulation
barrier between the cells.
Step 3
N-Type-
N-Type-
Oxide Layer
Silicon Base
16
Etch the silicon to create the hole for
the insulating barrier between the
cells.
Step 4
N-Type-
N-TypeOxide Layer
Silicon Base
Etch off the oxide layer.
Step 5
N-Type-
N-TypeOxide Layer
Silicon Base
Grow another oxide layer.
Step 6
N-Type-
N-TypeOxide Layer
Silicon Base
17
Mask and create an oxide layer to
leave only the p-type doped regions
exposed.
Step 7
N-Type-
N-TypeOxide Layer
Silicon Base
Spin on boron.
Step 8
P-Type+
P-Type+
N-Type-
N-TypeOxide Layer
Silicon Base
Diffuse boron to create the p-type
regions.
Step 9
P-Type+
P-Type+
N-Type-
N-TypeOxide Layer
Silicon Base
18
Etch off the remaining oxide layer (if
needed).
Step 10
P-Type+
P-Type+
N-Type-
N-TypeOxide Layer
Silicon Base
Grow another oxide layer.
Step 11
P-Type+
N-Type-
N-Type- N-Type
Oxide Layer
Silicon Base
Spin on SU-8 to act as the insulator
between the cells.
Step 12
SU-8
N-Type-
P-Type+
N-Type-
Oxide Layer
Silicon Base
19
Remove the SU-8 that is on top of
the oxide layer. This process is one
of our major risks. We have to
remove just enough to eliminate
everything on top of the oxide layer
but not so much that it cuts into the
insulating barrier.
Step 13
SU-8
N-Type-
P-Type+
N-Type-
Oxide Layer
Silicon Base
Mask and etch the oxide layer to
create holes for the aluminum
contacts.
Step 14
Oxide Layer
SU-8
N-Type-
P-Type+
N-Type-
Oxide Layer
Silicon Base
Sputter on aluminum to create the
interconnects.
Step 15
Oxide Layer
SU-8
N-Type-
P-Type+
N-Type-
Oxide Layer
Silicon Base
20
Pattern the aluminum traces to
create the finished product.
Step 16
Oxide Layer
SU-8
N-Type-
P-Type+
N-Type-
Oxide Layer
Silicon Base
21
Appendix C: Gantt Chart Detailing Project Plan for Solar Ear Project:
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