Download Low-Voltage Cascode Current Mirror Based on Bulk

2009 International Conference on Advances in Recent Technologies in Communication and Computing
Low-Voltage Cascode Current Mirror based
on Bulk-Driven MOSFET and FGMOS
techniques
Bhawna Aggarwal
Maneesha Gupta
Electronics and Communication Engg. Department,
Maharaja Agrasen Institute of Technology, Rohini
Sec.22, New Delhi-110086.
Email : [email protected],
ph: +91-9911565959
Electronics and Communication Engg. Department,
Netaji Subhash Institute of Technology, sector-3,
Dwarka New Delhi-110078
Email : [email protected],
ph: +91-9873333861
based on Bulk-Driven MOSFET approach (operating in linear
region) and based on FGMOS approach.
The paper is organized as follows: In section II, the
operation of Bulk Driven MOSFET is described. Section III,
deals with the working of FGMOS. In Section IV, Cascode
Current Mirror (CCM) is explained. In section V, low voltage
CCMs based on bulk-driven MOSFET and FGMOS are
proposed. Finally, the simulation results and comparison of
these techniques is given in section VI.
Abstract—In this paper, low voltage cascode current mirror
based on bulk-driven MOSFET (operating in linear region) and
floating-gate MOSFET are presented. The proposed circuits are
simulated using SPICE for 0.25 µm CMOS technology and their
results are compared with that of conventional cascode current
mirror.
Keywords—low voltage, cascode current mirror, bulk-driven
MOSFET, FGMOS
I. INTRODUCTION
Nowadays, need for reducing power supply to IC circuits
has assumed great importance with the shrinking dimension in
VLSI technology along with new fabrication trends. This
presents a great challenge to CMOS Analog /Mixed signal
circuit design. Also, the lowering of threshold voltage (VT) is
not directly proportional with reduction in the feature size of
modern CMOS circuit design [1].
In conventional analog circuit design, the fundamental
limitation for reduction of supply voltage is given by (1).
Equation (1) infers that the power supply must be at least
equal to the sum of magnitudes of p-type and n-type threshold
voltages [1].
|VDD-VSS| ≥VtN+|Vtp|
Fig. 1. Cross-section of a PMOS transistor and
terminal voltages for bulk driven operation
(1)
Where, VDD and VSS are positive and negative supply
voltages and VtN and Vtp are threshold voltages of NMOS and
PMOS respectively.
Many new techniques have been developed to overcome
this limitation and achieve low voltage CMOS analog circuits,
viz; MOSFETs operating in Sub- Threshold region, BulkDriven MOSFETs, Self-Cascode Structure, Floating-Gate
MOSFET (FGMOS) Approach and Level Shifter techniques
[2].
A Bulk-Driven Cascode Current Mirror working in
saturation region is presented in [4]. Here in this paper, lowvoltage modified Cascode Current Mirror has been proposed
VDD
Vin
Vb
VSS
Fig. 2. Bulk-driven MOSFET structure
978-0-7695-3845-7/09 $26.00
$25.00 © 2009 IEEE
DOI 10.1109/ARTCom.2009.83
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II. BULK-DRIVEN TRANSISTOR
In bulk-driven MOSFET, wells are required to isolate the
bulk terminals and if both NMOS and PMOS are required,
then a twin-well technology has to be used [3]. A Crosssection of P-Channel MOSFET in N-well CMOS technology
is shown in Fig 1. The current in a conventional gate-driven
MOSFET is obtained when the applied gate bias overcomes
the threshold voltage [2].However, in a bulk-driven MOSFET,
VGS (gate to source voltage) is kept constant [1], by applying a
biasing voltage at the gate terminal, as shown in Fig 2, and the
input is applied at the bulk terminal. Functionally seen, a bulkdriven MOSFET behaves like a JFET [2]. Thus, a bulk-driven
MOSFET operates as a depletion type device where the bulk
terminal functions as the gate terminal of the virtual JFET and
modifies the width of the channel according to the applied
voltage. Being a depletion type device, it can work under
negative, zero or even slightly positive biasing conditions.
Generally the substrate potential in a MOSFET is equal to
the source potential, i.e., VSB (source to substrate voltage) = 0.
But in some cases, the source potential of an NMOS can be
larger than the substrate potential. This results in a positive
source-to-substrate voltage, i.e., VSB > 0. In such a case,
threshold voltage VT includes the substrate bias terms and can
be defined as [6]:
VT = VT 0 + γ
(
2φ F + V SB − 2φ F
)
(a)
(b)
Fig. 4. FGMOS (a) Symbol (b) Equivalent circuit
model
Where, β is the transconductance parameter given as:
β=
β
2
(VGS − VT 0 − γ
\
g mbs =
(2)
2φF − VBS + γ
2φ F )2 ,
(4)
L
Where µn is the electron mobility, Cox is the gate-oxide
capacitance per unit area, W is the effective channel width and
the L is the effective channel length.
The channel conductance of the bulk-to-source junctions
gmbs is defined as:
γ 2β I D
γg m
∂I D
=
=
∂V BS 2 2φ − V
2 2φ F − V BS
F
BS
(5)
Where, gm is the channel transconductance of the gate-tosource junctions.
Where, VT0 is the threshold voltage when VSB=0, γ is the
bulk threshold parameter and ФF is the strong inversion surface
potential.
Substituting this value of VT in the conventional drain
current equation of the n-channel MOSFET in saturation
region, we get [5]:
I D ( sat ) =
μ n C oxW
III. FLOATING GATE MOSFET (FGMOS)
The structure of a typical n-channel, N-input FGMOS is
shown in Fig. 3. Its structure is similar to that of a
conventional MOSFET except that there is an additional
floating gate in FGMOS, which is electrically isolated within
the oxide layer. The additional floating gate offers almost
infinite input impedance. Threshold voltage of FGMOS can be
suitably altered and hence it can be used to realize low-voltage
circuits. The voltage on its floating gate (VFG) can be written as
[7]:
(3)
VDS > VGS - VT
N
∑ C iVGS + C fd V DS + C fsV SS + C fbV BS + Q FG
V FG =
i =1
Where,
CT
(6)
N
∑ C i = C1 + C 2 + C 3 + ....... + C N are the input
i =1
capacitances between control gates and floating gate, Cfd, Cfs
and Cfb denotes the capacitances from floating-gate to drain,
source and bulk respectively, VDS is the drain-to-source
voltage, CT is the total capacitance of the floating-gate and QFG
is the residual charge. The total capacitance is given as:
Fig. 3. Stucture of an n-input FGMOS MOSFET
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VSS
M5
VSS
M5
M6
Vb2
IIN
IOUT
M1
M6
Vb1
M2
IOUT
M1
M2
Vb1
VY
VX
M3
Vb1
M4
M3
M4
Vb1
VDD
Fig. 5. Gate-Driven Cascode Current Mirror
VDD
Fig.6. Bulk-Driven Cascode Current Mirror
N
CT = ∑ C i + C fd + C fs + C fb
(7)
⎧⎛ ⎛ N
⎪⎜ ⎜ ∑ C i
⎪⎜ ⎜
O
I DS = β ⎨⎜ ⎜ i =1
⎪⎜ ⎜ CT
⎪⎜ ⎜
⎩⎝ ⎝
i =1
The residual charge may be trapped at the floating gate
during the fabrication process and can be neglected using
method suggested in [8]. Therefore (6) reduces to:
N
∑ C iVGS + C fd V DS + C fsV SS + C fbV BS
V FG =
i =1
⎧⎛ ⎛ N
⎪⎜ ⎜ ∑ C i
⎪⎜ ⎜
O
I DS
= β ⎨⎜ ⎜ i =1
⎪⎜ ⎜ CT
⎪⎜ ⎜
⎩⎝ ⎝
⎞
⎟
⎛ C fd
⎟
⎟VGS + ⎜⎜ C
⎝ T
⎟
⎟
⎠
⎞
⎛C
⎟V DS + ⎜ fs
⎟
⎜C
⎠
⎝ T
⎞
⎛C
⎟V SS + ⎜ fb
⎟
⎜C
⎠
⎝ T
⎞
⎟V BS −VT
⎟
⎠
⎞
⎟
⎛ C fd
⎟
⎟VGS + ⎜⎜ C
⎝ T
⎟
⎟
⎠
(11)
2
⎫
⎞
⎟
⎪
⎟
1
⎛ ⎞ 2 ⎪
⎟V DS − ⎜ ⎟V DS ⎬
⎝2⎠
⎪
⎟
⎟
⎪
⎠
⎭
(9)
⎧⎛ N
⎪⎜ ∑ C i
β ⎪⎜
S
= ⎨⎜ i =1
I DS
2 ⎪⎜ CT
⎪⎜
⎩⎝
⎫
⎞
⎟
⎪
⎟
⎛1⎞ 2 ⎪
⎟V DS − ⎜ ⎟V DS ⎬
⎝2⎠
⎪
⎟
⎟
⎪
⎠
⎭
⎧⎛ N
⎫
⎞
⎪⎜ ∑ C i ⎟
⎪
β ⎪⎜
⎟
⎪
S
I DS
(12)
= ⎨⎜ i =1 ⎟VGS − VT ⎬
2 ⎪⎜ CT ⎟
⎪
⎟
⎪⎜
⎪
⎠
⎩⎝
⎭
The symbol and equivalent circuit for an N-input, FGMOS are
shown in Figs. 4(a) and (b) respectively, where Gi (for i=1,
2… N) are the control inputs and D, S and B are the drain,
source and substrate, respectively.
(8)
CT
⎞
⎟
⎟
⎟VGS − VT
⎟
⎟
⎠
⎫
⎪
⎞
⎛ C fs ⎞
⎛ C fb ⎞
⎟V DS + ⎜
⎟V SS + ⎜
⎟V BS −VT ⎪⎬
⎟
⎜C ⎟
⎜C ⎟
⎪
⎠
⎝ T ⎠
⎝ T ⎠
⎪
⎭
2
IV. CASCODE CURRENT MIRROR
A conventional gate-driven cascode current mirror is shown in
Fig. 5. Here if (W/L)2/(W/L)1 = (W/L)4/(W/L)3 then, VGS2 =
VGS1 and hence VX = VY. Where W/L represents the aspect ratio
of the MOSFET and VX and VY are the voltages at node X and
Y respectively. This relation holds even if M1 and M2 suffer
from body effect. Though cascode current mirror consumes
substantial voltage headroom as compared to a simple current
mirror, it gives higher accuracy with high output impedance
[9].
(10)
The drain current equations in the ohmic and saturation
region for the n-channel FGMOS are given in (9) and (10).
These equations have been obtained by modifying the
conventional
n-channel
MOSFET
equations.
N
Assuming, ∑ C i >> C fd , C fs , C fb , (9) & (10) can be
V. LOW VOLTAGE CASCODE CURRENT MIRROR
i =1
approximated as:
A. Bulk-driven PMOS CCM in linear region:
A low voltage Bulk-driven PMOS, CCM working in linear
region is proposed in Fig. 6. Here the gate terminals of all the
PMOS transistors are connected to a fixed voltage Vb1 (usually
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it occupies more silicon area due to multiple polysilicon layers
required for the fabrication.
VSS
M5
M6
IIN
600uA
IOUT
400uA
M1
M2
200uA
VX
Vb1
VY
0A
M3
M4
Vb1
-200uA
0
50uA
100uA
I(iin)
A I(vout)
VDD
150uA
200uA
250uA
300uA
iin
350u
A
400uA
450uA 500uA
Fig. 8. Simulation of Simple CCM
Fig. 7. FGMOS Cascode Current Mirror
VSS). This voltage must be greater than or equal to |VT| to form
the conduction channel between source and drain terminals.
Here, N-well (the bulk of PMOS) terminal is used to apply the
input instead of gate terminal, as is done in case of gate-driven
MOSFET. In Bulk-driven PMOS VSB has to be kept below the
switch-on voltage of diode (formed between bulk and source
terminals) else a large amount of the MOSFET drain current
will be lost in bulk terminal as leakage current. Bulk currents
of M1 and M3 can be reduced if they are operated in linear
region as their bulk-to-source junctions are already forwardbiased.
For a bulk-driven MOSFET the dependence of drain current
ID in linear region is given as:
⎡
I D = β ⎢V SG − VTO − γ 2φ F − V BS + γ
⎣
120uA
80uA
40uA
0A
0A
I(vout)
20uA
I(iin)
60uA
40uA
80uA
100uA
120uA
iin
Fig. 9. Simulation of Bulk-Driven CCM
200uA
1
⎤
2φ F − V SD ⎥V SD
2
⎦
(13)
100uA
Now from Fig. 6, we can get, VSB1 = VSD1, VSB3 = VSD3, VSB3 =
VSB4, and VSD4 = VSD3+ VSB1- VSB2 or VSD4+ VSB2 = VSD3+ VSB1.
Since M1 and M3 are operating in linear region and due to
above mentioned conditions M2 and M4 will also operate in
linear region due to which IOUT is forced to match with IIN.
0A
-100uA
0A
B. FGMOS based Cascode Current Mirror:
A low voltage CCM based on FGMOS is shown in Fig. 7.
Here M1, M2, M3 and M4 are two input FGMOS. In
these MOSFET’s, one gate terminal is used as normal input
terminal and a biasing voltage is applied at the second gate
terminal to form the conduction channel between source and
drain terminals. Here also like a simple gate-driven CCM if
(W/L)2/(W/L)1 = (W/L)4/(W/L)3, then, VGS2 = VGS1 and hence
VX = VY. This forces same current in both the branches and
IOUT becomes equal to IIN. Also, in this circuit all the
MOSFET’s are working in saturation region.
Thus, in FGMOS based CCM same current equation is
obtained at low voltage, as compared to gate-driven CCM, but
20uA
40uA
I(vout)
I(iin)
60uA
80uA
100uA
120uA
140uA
160uA 180uA
iin
Fig. 10. Simulation of FGMOS CCM
TABLE I
COMPARISON OF CASCODE CURRENT MIRRORS BASED ON THREE
TECHNIQUES
Parameters
Simple
Bulk-Driven
FGMOS
CCM
CCM
CCM
Voltage
±1.5V
±0.6V
±0.45V
-3
-4
Power
2.33X10
5.58X10
9.65X10-5
Input Resistance
7.67X102
7.66X103
1.99X103
4
3
Output Resistance
8.1X10
5.72X10
1.53X105
Range
0-350µA
20-90µA
0-150µA
Region of operation of
Saturation
Linear
Saturation
MOSFET
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VI. SIMULATION RESULTS
VI. REFERENCES
[1]
The proposed low voltage CCMs are simulated using SPICE
of 0.25um CMOS technology. The simulation results of all
the three techniques are shown in Figs. 8, 9 and 10. The
comparison of all the three CCMs is tabulated in Table I. As
can be seen from the table, conventional CCM works at
higher supply voltage of ±1.5V. Bulk-driven CCM is one of
the good alternatives as the required supply voltage here is
±0.6V. But here the range of operation is limited to 20-90uA.
In this regard FGMOS based CCM is better than bulkdriven CCM as the supply voltage required is even lesser
approx. ±0.45V and range of operation is 150uA. However,
the silicon area occupied is greater than that of bulk-driven
CCM.
[2]
[3]
[4]
[5]
[6]
[7]
V. CONCLUSIONS
[8]
Two different approaches of achieving low voltage CCM
using bulk-driven MOSFET and FGMOS have been
presented. The simulations for the proposed circuits were
carried out using SPICE of 0.25um technology and their
results were compared with that of conventional CCM and
suitability of low voltage CCM based on FGMOS was found.
[9]
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