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1010CD_TOC.doc # Cover Story—Focus Report The Growing Need For Concurrent Design By Ed Sperling 33 Features Time for a Change – Making Clock Domain Crossing Analysis Usable and Useful Stage A Case Study By Ayon Dey, Texas Instruments, Namit Gupta and Paras Mal Jain, Atrenta. Characterizing Nanometer Analog/RF Circuits By Kurt Johnson, Berkeley Design Automation Floating-Body Memory for High-Density Memory Applications New solutions reduce dependence on functional simulation and provide increased confidence. By Carlo Del Giglio and Alok Sanghavi, Jasper Design Automation Seven Things You Should Know About Developing DSP Applications on FPGAs By Tom Hill, Xilinx Inc. Shaping Efficiency using CHiL Semiconductor Digital Algorithms, Algorithms like dynamic phase control and variable gate drive promise to raise efficiency across the entire load line. By David Williams, CHiL Semiconductor Corporation Departments # Editor's Note: New Semiconductor Fab Comes to Oregon) By John Blyler, Editor in Chief # In the News--People in the News By Jim Kobylecky, Managing Editor # Head2Head2Head: Will IP & EDA Be Better Together By Mike Gianfagna, Atrenta Inc, Kalar Rajendiran, eSilicon Corp., Steven E. Schulz, Silicon Integration Initiative Inc. # Top view-- Having a Bad (Electronics) Day? Blame It on Variability. By Rudy Lauwereins, PhD, VP Smart Systems Technology Office, imec # Dot.Org-- T UVM: Extending Standardization from Language to Methodology By Tom Anderson, Cadence Design Systems Inc. # No Respins— Advanced Process Nodes Demand Next-Generation Shape-Based Routing By Mark Waller, Pulsic Ltd.
