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Memory System 5-1 Address Bus (A0 – A19) 1M x 8 Data Bus ( D0 – D7) Logical Memory Map. Each location size is one byte (Byte Addressable) Address Bus (A0 – A19) 512K x 8 512K x 8 D0 – D7 D8 – D15 Data Bus (D0 – D15) Logical Memory Map. Each location size is one byte (Byte Addressable) Address Bus (A0 – A19) EVEN addresses goes to bank 0 Bank 0 512K x 8 ODD addresses goes to bank 1 Bank 1 512K x 8 D0 – D7 D8 – D15 Data Bus (D0 – D15) Logical Memory Map. Each location size is one byte (Byte Addressable) Address Bus (A0 – A19) 512K x 8 EVEN addresses goes to bank 0 ODD addresses goes to bank 1 Bank 0 Bank 1 AL AH 512K x 8 D0 – D7 D8 – D15 Data Bus (D0 – D15) MOV [1000], AX DS:1000 = AL DS:1001 = AH Logical Memory Map. Each location size is one byte (Byte Addressable) Address Bus (A0 – A19) EVEN addresses goes to bank 0 Bank 0 512K x 8 Data Bus (D0 – D15) DS:1001 = AL DS:1002 = AH Bank 1 512K x 8 D0 – D7 MOV [1001], AX ODD addresses goes to bank 1 D8 – D15 AH AL Logical Memory Map. Each location size is one byte (Byte Addressable) BHE' A0 Function 0 0 Both banks are enabled for a 16-bit transfer 0 1 High bank enabled for an 8-bit transfer 1 0 low bank enabled for an 8-bit transfer 1 1 No banks enabled Designing Larger Memories 64M X 32 memory using 16M X 16 chips 5-9 Memory Mapping Full mapping 5-10 Memory Mapping (cont’d) Partial mapping 5-11 Interleaved Memory • In our memory designs – Block of contiguous memory addresses is mapped to a module • One advantage – Incremental expansion • Disadvantage – Successive accesses take more time » Not possible to hide memory latency • Interleaved memories – Improve access performance • Allow overlapped memory access • Use multiple banks and access all banks simultaneously – Addresses are spread over banks » Not mapped to a single memory module 5-12 Interleaved Memory (cont’d) 5-13 Interleaved Memory (cont’d) Interleaved memory allows pipelined access to memory 5-14 Interleaved Memory (cont’d) • Number of banks – M = memory access time in cycles – To provide one word per cycle • Number of banks M • Drawbacks of interleaved memory – Involves complex design • Example: Need MDR or MAR – Reduced fault-tolerance • One bank failure leads to failure of the whole memory – Cannot be expanded incrementally 5-15 1. Static RAM (SRAM) • Essentially uses flip-flops to store charge (transistor circuit) • As long as power is present, transistors do not lose charge (no refresh) • Very fast (no sense circuitry to drive nor charge depletion) • Complex construction • Large bit circuit • Expensive • Used for Cache RAM because of speed and no need for large volume 5-16 Static RAM Structure 1 1 0 “NOT” 1 six transistors per bit (flip flop) 0 0 1 0/1 = example 0 5-17 2. Dynamic RAM (DRAM) • • • • • • • Bits stored as charge in capacitors Simpler construction Smaller per bit Less expensive Slower than SRAM Typical application is main memory Essentially analogue -- level of charge determines value 5-18 Dynamic RAM Structure ‘High’ Voltage at Y allows current to flow from X to Z or Z to X Y X Z + one transistor and one capacitor per bit 5-19 SRAM v.s. DRAM Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Storage element Advantages 1. 2. Fast No refreshing operations 1. High density and less expensive Disadvantages 1. 2. Large silicon area expensive 1. 2. Slow Require refreshing operations Applications High speed memory applications, Such as cache Main memories in computer systems 5-20 latch latch • Two dimensional matrix • Bits are accesses by: – Accepting row and column addresses ras down the same multiplexed address bus Row – First: address is presented and latched by ras signal A[n:0] – Next: column address is presented and latched by cas signal cas decoder DRAM Organisation array of memory cells Output register mux Data out 5-21 Typical 16 Mb DRAM (4M x 4) RAS = Row Addr. Select CAS = Column Addr. Select WE = Write Enable OE = Output Enable 2kx2k = 4M nybble 5-22 Accessing DRAMs DRAM block diagram Addr[7:0] Column decoder Row decoder RAS CAS Storage Array 5-23 Accessing DRAMs Address bus selection circuit Row Address MUX To DRAM Column Address RAS address decoder D CLK Q set D Q Q set D Q CAS set IO/M 5-24 Accessing DRAMs Refreshing operations — Because leakage current will destroy information stored on DRAM capacitors periodic refreshing operations are required for DRAM circuits — During refreshing operation, DRAM circuit are not able to response processor’s request to perform read or write operations — How to suspend memory operations? — DRAM controllers are developed to take care DRAM refreshing operations 5-25 5-26