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ISSN 2319-8885 Vol.03,Issue.31 October-2014, Pages:6186-6190 www.ijsetr.com A Comparative Analysis of 6-Transistor SRAM and 6T ROM Embedded SRAM P.BALANARASIMHULU1, G.KARTHIK REDDY2 1 G. Pulla Reddy college of Engineering (Autonomous), Andhrapradesh, India, Email: [email protected]. 2 G. Pulla Reddy college of Engineering (Autonomous), Andhrapradesh, India, Email: [email protected]. Abstract: Power consumption has become a primary design constraint for a VLSI circuit. In this paper, a new approach towards the design of ROM Embedded SRAM cache design for low power has been proposed. The main objective of this project is to reduce the area and power in modified ROM embedded SRAM cell. This modified ROM embedded SRAM cell is implement with four NMOS transistors and two PMOS transistors and also one extra word line is used compared to 6 Transistor SRAM cell. Most of the SRAM are used in 6 transistor SRAM cell because 6T SRAM cells having good electrical performance. But these SRAM cell consumes more area and also more power. This area and power consumption is reduced by ROM Embedded SRAM Design. LT SPICE Software tool are used to measure the Power. Proposed ROM Embedded SRAM cell working in two modes i.e SRAM mode and ROM mode. These two modes operation is performed based on the Word line connection in RSRAM operation. In the proposed ROM Embedded SRAM, During SRAM operation, ROM data is not available. During ROM mode operation SRAM data temporarily stored in buffer generators (PRPGs) produce test data to avoid storing test data in on-chip ROMs for built-in self-test (BIST) [4]. Note that on-chip ROMs can significantly improve the performance of such applications. For evaluation of math functions, math libraries are used. Such libraries are usually stored off-chip, leading to degradation in performance. The speed gap between a processor and an external memory grows with every technology generation, resulting in major roadblocks to highperformance system design. Keywords: SRAm Design, ROM, BIST, NMOS Transistors. I. INTRODUCTION A. Existing Method 1. Conventional 6t SRAM Cell: The most commonly used SRAM type is the 6T SRAM which offers better electrical performances from all aspects (speed, noise immunity, standby current). The smallest 6T SRAM cell that has been fabricated till today has an area of 0.08µm2 and it was fabricated in the 22nm process using immersion and EUV lithography [6]. Conventional SRAM cell is implementing with six transistors. in these SRAM cell two cross coupled inverter are used to store one bit of data. Word line is used to enabling the process of conventional SRAM cell and two access transistors are used to perform read and write operations. An SRAM cell is the key SRAM component storing binary information. A typical SRAM cell uses two cross-coupled inverters forming a latch and access transistors. Access transistors enable access to the cell during read and write operation. An SRAM cell is designed to provide non-destructive read access, write capability and data storage (or data retention) for as long as cell is powered. In general, the cell design must strike a balance between cell area, robustness, speed, leakage and yield. Power reduction is one of the most important design objectives. However, the power cannot be reduced indefinitely without compromising the other parameters. Low-power can compromise the cell area also speed of operation. The mainstream six-transistor (6T) CMOS SRAM cell is shown in Fig1, four transistors (Q1−Q4) comprise cross-coupled CMOS inverters and two NMOS transistors Q5 and Q6 provide read and write access to the cell. A 6T CMOS SRAM cell is the most popular SRAM cell due to its superior robustness, low power and low-voltage operation. connected to the input of inverter Q2−Q4 (Figure -1). Sizing of Q1 and Q5 should ensure that inverter Q2−Q4 do not switch causing a destructive read. B. Write Operation of Conventional 6T SRAM Cell Fig1. Conventional 6T SRAM cell. Copyright @ 2014 IJSETR. All rights reserved. P.BALANARASIMHULU, G.KARTHIK REDDY Fig. 1 describes the schematic of conventional 6T SRAM volt and is During write operation one of the bit lines, BL is bit cell. Note that the thin-cell layout topology is a de facto driven from precharged value (VDD) to the ground potential standard in the industry because of its compact area, better by a write driver through transistor Q6. If transistors Q4 and tolerance to variability, and high performance [7]–[8]. Also, Q6 are properly sized, then the cell is flipped and its data is note that the contact for WL signals is shared by two effectively overwritten. A statistical measure of SRAM cell neighboring SRAM bit cells. For each row, there is one write ability is defined as write margin. Write margin is metal line of WL. Hence, gate signals of all the access defined as the minimum bit line voltage required flipping the transistors in the same row are turned on and off state of an SRAM cell. The write margin value and variation simultaneously. is a function of the cell design, SRAM array size and process variation. A cell is considered not writeable if the worst-case write margin becomes lower than the ground potential. Note B. Read Operations of Conventional 6T SRAM Cell In this read operation, the bit lines are precharged to that the write operation is applied to the node storing a “1”. VDD. The read operation is initiated by enabling the word This is necessitated by the non-destructive read constraint line (WL) and connecting the precharged bit lines, BL and that ensures that a “0” node does not exceed the switching BLB, to the internal nodes of the cell. The bit line voltage threshold of inverter Q2−Q4. The function of the pull-up VBL remains at the precharge level. The complementary bit transistors is only to maintain the high level on the “1” line voltage VBLB is discharged through transistors Q1 and storage node and prevent its discharge by the off-state Q5 connected in series. Effectively, transistors Q1 and Q5 leakage current of the driver transistor during data retention form a voltage divider whose output is now no longer at zero and to provide the low-to-high transition during overwriting. Fig2. Schematic of 6-Transistor ROM Embedded SRAM cell. II. PROPOSED METHOD A. ROM Embedded 6T SRAM Cell: The proposed ROM embedded SRAM cell is implement with four NMOS transistors and two PMOS transistors and two word lines and bit lines. Proposed ROM Embedded SRAM cell working in two modes, i.e SRAM mode operation and ROM mode operation. Existing 6T SRAM cell consumes more power and also volatile property i.e when the power is off total data will be erasing. These disadvantages overcome by the proposed ROM Embedded SRAM cell. ROM mode, to retrieve ROM data from R-SRAM, we perform following two steps shown in below: 1. write '1' to all the bit cells with Word Line1 and Word Line2 are turned on(BL=1,BLB=0,WL1=onWL2=on). 2. Write '0' to all the bit cells with Word Line1 turned off and WL2 turned on (BL=0, BLB=1,WL1=OFF,WL2=ON). The schematic of 6-Transistor ROM Embedded SRAM cell is shown in Fig. 2. Compared to conventional 6T SRAMs, 6T R-SRAM bit cells have an extra WL. Depending on the ROM data to be embedded into the R-SRAM, the gate of an access transistor is connected to WL1 or WL2. Since the R-SRAM is based on the thin-cell layout topology of the SRAM, two neighboring access transistors should be connected to the same WL, as shown in Fig. 2. If an R-SRAM bit cell stores “0”(“1”), the left access transistor (AXL) is connected to WL2(WL1). The right access transistor (AXR) of an RSRAM bit cell follows the connectivity of the AXL of the right-side neighboring bit cell. Connectivity of the AXR of the end cell, which resides at the end of a row, is determined by the connectivity of the AXL of the end cell. 6 Transistor ROM Embedded SRAM cell working in two modes, i.e Normal SRAM mode and ROM mode. In the proposed ROM Embedded SRAM cell, During the normal SRAM mode, two WLs are always turned on and off at the same time so as to operate conventional 6T SRAM functions. During Normal SRAM mode, ROM data is not available. International Journal of Scientific Engineering and Technology Research Volume.03, IssueNo.31, October-2014, Pages: 6186-6190 A Comparative Analysis of 6-Transistor SRAM and 6T ROM Embedded SRAM In the During the ROM mode operation, SRAM data is temporally stored in buffer. After Step I Row stores all one’s, i.e “1111”. That means each bit cell stores “1”, after first step left access transistors of cell 1 and cell 2 connected to word line 2, that means in step 2 cell 1 and cell 2 storing “0” value. After the above two steps, we can read retrieved ROM data from R-SRAM bit cells using the conventional SRAM read operation (WL1 and WL2 are turned on). Note that the ROM data to be embedded is determined by the connectivity of the access transistors, as shown in Fig. 2. The proposed ROM embedded SRAM cell increase the Speed and Performance without Area penalty. Note that two write steps of ROM data retrieval destroy the corresponding SRAM content [6]-[8]. Hence, before ROM data retrieval, SRAM data of the corresponding block is written into a buffer (that takes an area of a block). The proposed 6 Transistor SRAM cell have two write operations in ROM mode operation, for Fig. 3(b) these two steps write stability problem occur. In step2 of Fig.3. (a) Schematic of 8 Transistor ROM Embedded ROM mode write stability problem occur, because two SRAM storing “0.” (b) Schematic of 8 Transistor ROM neighboring cells storing different data. i.e it acts like a five Embedded SRAM storing “1. transistor SRAM cell. III. 8T ROM EMBEDDED SRAM DESIGN The proposed SRAM cell implement with six NMOS transistors and two PMOS transistor. 6 Transistor ROM embedded SRAM cell having the write stability problem, this disadvantage overcome by the 8 Transistor SRAM cell. The 8T SRAM cells isolate read and write operations using two additional transistors. The read and the write operations can be separately optimized for improved read and write stabilities, and the 8T SRAM is suitable for process variation tolerance and low-voltage operation in scaled technologies [7].Below figure shows the Schematic of 8 Transistor ROM embedded SRAM cell. 8 Transistors RSRAM cell has two separate word lines for read and write operations. RCON is the ROM control signal, Transistor RD of the 8T RSRAM can be connected to either ground or ROM control signal. In standard 8T SRAM mode operation Transistor RD is always connected to ground, during normal SRAM operation of 8T RSRAM ROM control signal (RCON) is connected to ground. Two additional transistors in 8T RSRAM layout create enough routing space for RCON metal layer. To perform ROM data retrieval from the 8T R-SRAM, we write “0”s to all bit cells, similar to the 6T R-SRAM. Then, all RD transistors of the 8T R-SRAM are turned on. When we read ROM data after write “0”s, RCON is driven by the supply voltage. If RD is connected to the ground, we can read “0” through read bit line (RBL) [Fig. 3(a)]. On the other hand, if RD is connected to RCON (supply voltage), the RBL maintains the precharged voltage level, and we can read “1” [Fig. 3(b)]. Compared to the two write steps of the 6T RSRAM (during the ROM data retrieval), the 8T RSRAM requires only one write step. IV. SIMULATION RESULTS Fig4. Waveform Results of 6T SRAM cell. Fig. 3(a) International Journal of Scientific Engineering and Technology Research Volume.03, IssueNo.31, October-2014, Pages: 6186-6190 P.BALANARASIMHULU, G.KARTHIK REDDY V. CONCLUSION In this paper proposed a new RSRAM cell design without any Area or performance penalty on the SRAM cell. Proposed RSRAM uses one extra word line and SRAM access transistors are connected to any one of the two word lines depending on the data to be stored in the ROM. For simulations purpose LT SPICE Software tool is used. This tool is used to checking the functionality and also measuring the power. In 6T RSRAM cell stores different data write stability problem occurs, because in this case it acts as a 5T SRAM cell. this write stability problem overcome by the 8T ROM Embedded SRAM cell. Fig5. Waveform Results of 6T ROM Embedded SRAM Cell. Fig6. Waveform Results of 8T RSRAM Cell. Table.1 Power Comparisons VI.REFERENCES: [1]Infineon. (2007). 90 nm CMOS Platform Technology, Neubiberg,Ger-many[Online].Available:http://www.infineon. com. [2]M.Frigg and S. G. Johnson, “The design and implementation of FFTW3,” Proc. IEEE, vol. 93, no. 2, pp. 216–231, Feb. 2005. [3]M. Shin and I. Park, “SIMD processor-based turbo decoder supporting multiple third-generation wireless standards,” IEEE Trans. Very Large Scale Integration. (VLSI) Syst., vol. 15, no. 7, pp. 801–810, Jul. 2007. [4]D. Lee, S. P. Park, A. Goel, and K. Roy, “Memory-based embedded digital ATE,” in Proc. VLSI Test Symp., May 2011, pp. 266–271. [5]J. Hennesy and D. Patterson, Computer Architecture: A Quantitative Approach. San Mateo, CA: Morgan Kaufman, 2007. [6]O.Wood, C.Koay, K. Petrillo, H. Mizuno, S. Raghunathan, J. Arnold, D. Horak, M. Burkhardt, G. McIntyre, Y. Deng, B. La Fontaine, U. Oko- roanyanwu, A. Tchikoulaeva, T. Wallow, H.-C. James, M. Colburn, S. S. C. Fan, Bala S. Haran, and Y. Yin, ‘‘Integration of EUV lithography in the fabrication of 22-nm node devices,’’ Proc. SPIE vol. 7271, pp. 727104-1– 727104-2, 2009. [7]L. Chang, R. K. Montoye, Y. Nakamura, K. A. Batson, R. J. Eickemeyer, R.H. Dennard, W. Haensch, and D. James, “An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 956–963, Apr. 2008. [8]S. Nalem and B. H. Calhoun, “Asymmetric sizing in a 45 nm 5T SRAM to improve read stability over 6T,” in Proc.Custom. [9]T. Brandon, D. Elliott, and B. Cockbum, “Using stacked bit lines and hybrid ROM cells to form ROM and SRAMROM with increased storage density,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2595–2605, Dec. 2006. [10]P. Ndai, A. Goel, and K. Roy, “A scalable circuitarchitecture co-design to improve memory yield for highperformance processors,” IEEE Trans. Very Large Scale Integration. (VLSI) Syst., vol. 18, no. 8, pp. 1209–1219, Aug.2010. [11] Nanoscale Integration and Modeling (NIMO) Group. (2007). Predictive Technology Model (PTM), Tempe, AZ [Online] Available: http://www.eas.asu.edu/ptm. Above table shows the power comparisons of 6T SRAM cell, 6T RSRAM cell and 8T RSRAM cell. Above wave forms shows the results of 6T SRAM cell and 6T RSRAM cell. 6T RSRAM cell working in SRAM mode and ROM mode. International Journal of Scientific Engineering and Technology Research Volume.03, IssueNo.31, October-2014, Pages: 6186-6190 A Comparative Analysis of 6-Transistor SRAM and 6T ROM Embedded SRAM [12]S. Mukhopadhyay, R. Rao, J. Kim, and C. Chuang, “SRAM write-ability improvement with transient negative bit-line voltage,” IEEE Trans. Very Large Scale Integration. (VLSI) Syst., vol. 19, no. 1, pp. 24–32, Jan. 2011. [13]N. A.Touba, “Survey of test vector compression techniques,” IEEE Design. Test Comput., vol. 23, no. 4, pp. 294–303, Apr. 2006. [14]Y.Li, S.Makar, and S.Mitra, “CASP: Concurrent autonomous chip self-test using stored test patterns,” in Proc. Design Autom Test Eur., 2008, pp. 885–890. [15]S. Mitra and K. S. Kim, “X-compact: An efficient response compaction technique,” IEEE Trans. Comput.Aided Design, vol. 23, no. 3, pp. 421– 432, Mar. 2004. [16] K. Constantinides, O. Mutlu, T. Austin, and V. Bertacco, “Software-based online detection of hardware defects: Mechanisms, architectural support, and evaluation,” in Proc. MICRO, 2007, pp. 97–108. International Journal of Scientific Engineering and Technology Research Volume.03, IssueNo.31, October-2014, Pages: 6186-6190