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ECE 3300 Lab 2
ECE 1250 Lab 6
Measuring Voltage
Building: Logic Gate Circuits
Design a Logic Circuit
Overview: In Lab 3 you will:
 Simulate basic logic gates.
 Measure input and output voltages for basic logic gates.
 Design, build, and test logic gate circuits to implement specified logic functions.
This lab introduces logic gates that are the basis for computer circuits. You will learn
about basic types of gates, and you will design a simple circuit for summing one-digit
binary numbers. Logic gates will also be useful in your final project if you need to turn
on an LED or motor when a certain combination of sensor inputs occurs, such as "the
output of sensor 1 is low and the output of sensor 2 is high."
Equipment List:
 MyDAQ board with cables. (You can hook them to the lab computers if you don’t
want to bring your laptop.)
 Multisim software.
 From Labs 1 and 2:
o Protoboard & wire kit
o Resistor (1kΩ)
o Red LED
 Additional parts:
o Resistors: 1kΩ, 1MΩ (two)
o Red LED
Safety Precautions:
1) Logic gate power supplies: The logic gates we will use (74HC00 and 74HC86) need
a single +5 V power supply (available on the opposite end of the myDAQ from the
±15 V analog power supplies). Using the wrong power supply voltage may burn out
the logic gate chip and may also cause it to become extremely hot, smoke, or shatter.
Reversing the power supply polarity has a similar effect. Depending on whether
protective circuitry is built into the chip, if apply power improperly you will probably
have to buy a new chip. Note that the IC can easily be plugged into the breadboard
backwards. Make sure the notch or dot on the chip is close to the +5 V connection
(which is on pin 14 for both the 74HC00 and 74HC86).
2) Shorting gate outputs: One logic gate output can safely drive multiple logic gate
inputs, which is known as fan-out, but logic gate outputs cannot be connected to other
logic gate outputs. The latter situation would cause the logic gate outputs to fight one
another. A logic gate may or may not survive having its outputs shorted together.
1
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu
ECE 1250 LAB 3
Instructions & Reference Material:
 MyDAQ as voltmeter
https://utah.instructure.com/courses/266578/assignments/1347122
 Data Sheets:
74HC00 NAND gate: http://www.digikey.com/product-search/en?x=-1004&y=74&lang=en&site=us&KeyWords=TC74HC00apf-nd
74HC86 XOR gate: http://www.digikey.com/product-search/en?x=-1004&y=74&lang=en&site=us&KeyWords=tc74hc86
Prelab: Videos and Multisim
1. Review the videos and written material (see videos on website).
2. (Optional) You will be faster if you do the Multisim simulations before you come to
lab. If you do not have Multisim running on your PC yet, then just do the Multisim
simulations on the lab computers.
WRITE-UP: In your lab notebook, take notes during the videos and record key
information from reading assignments so you don’t have to go back and watch or
review them again. Make sure to label each section in your notebook with the
same headings as highlighted above and below in yellow as you write the
information mentioned for each write-up section.
Experiment 1: NAND gate operation (25 points)
The MyDAQ puts out +5 V and gnd for powering digital circuits. These are on the
opposite end from the ±15 V analog supplies. The only difference between the +5 V and
the ±15 V supplies is the voltage. Note that the digital gnd is isolated from the analog
gnd, however, so you would need to connect the gnd's together if you wanted to use the
digital and analog supplies in the same circuit.
Use the MyDAQ as a Voltmeter to measure the voltages for all the logic circuits in this
lab. 0 V or gnd represents a logical 0 (or FALSE), and +5 V represents a logical 1 (or
TRUE).
The 74HCxx logic gates we use in this lab have inputs that can be connected to 0 V (gnd)
or +5 V. You will make or change these inputs by moving wires on your breadboard.
The chip itself also requires power supply connections of +5 V on pin 14 and 0 V on
pin 7, as shown in Fig. 1. The power supply connections must always be present and do
not change. There are four gates on the chips we use. For the first part of the lab, you
will use only one gate. It is a good idea to connect all the other unused gate inputs to 0 V
or 5 V.
Note the pin numbers on the 74HC00 chip, shown in Fig. 1. Pin 1 is left of the notch, or
dot, on one end of the chip. Pin increase in the clockwise direction around the chip.
A 74HC00 contains four NAND gates. "NAND" stands for "not and," and means the
gate outputs a 1 (or TRUE) if and only if it is not the case that both input A is a 1 (or
TRUE) and input B is a 1 (or TRUE).
2
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu
ECE 1250 LAB 3
(a) Schematic
(b) Breadboard
Fig. 1. NAND gate circuit.
3
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu
ECE 1250 LAB 3
Simulate, Build, and Test the NAND gate circuit in Fig. 1:
a) When you run the Multisim file for Fig. 1, available for download on the course
website, click on the switches to change the NAND gate inputs from 0 V to 5 V or
vice versa. Switch the A and B inputs to either 0 V (gnd) or +5 V in all four
possible combinations to verify the "truth table" below in Table I. Note that
0 V = logical 0 and +5 V = logical 1. Observe the output voltage of the gate and
translate it into 0 or 1.
Note how VCC and Gnd for the NAND gate chip are specified behind the scenes.
When adding logic gate chips in Multisim, be careful to avoid redefining VCC,
which might confuse Multisim.
TABLE I
NAND GATE TRUTH TABLE
Input A
0
0
1
1
Input B
0
1
0
1
Output Y
1
1
1
0
b) Construct the circuit in Fig. 1 on your breadboard, and connect the A and B inputs
to either 0 V (gnd) or +5 V in all four possible combinations to verify the "truth
table" in Table I. Use the MyDAQ voltmeter to measure the output of the NAND
gate on pin 3.
c) Connect a 1 kΩ resistor and LED in series from the NAND gate output to Gnd,
and use the LED on to indicate a 1 and LED off to indicate a 0. (Try turning the
LED around if it doesn't light when it should.) Try the combinations of inputs in
the NAND gate truth table again to verify the gate is working as expected.
WRITEUP: Explain your procedure. Make sure the expected and measured
truth tables for simulation and actual circuit are in your notebook, along with a
note about whether the LED indicator worked.
Experiment 2: XOR gate truth table (10 points)
A 74HC86 contains four XOR (exclusive-or) gates. An XOR gate outputs a 1 (or TRUE)
if input A is a 1 (or TRUE) or input B is a 1 (or TRUE) but not both (exclusivity).
Simulate, Build and Test the XOR gate circuit in Fig. 2. Fill in the truth table below for
the XOR gate by trying all possible combinations of input values (0 or 1) for inputs A
and B.
TABLE II
XOR GATE TRUTH TABLE
Input A
0
0
1
Input B
0
1
0
Output Y
4
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu
ECE 1250 LAB 3
1
1
(a) Schematic
(b) Breadboard
Fig. 2. XOR gate circuit.
5
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu
ECE 1250 LAB 3
Experiment 3: NOT gate and NAND gate (10 points)
Build and Test the gate circuit in Fig. 3. Before testing it, analyze the circuit by
determining on paper what the output at Y will be given the A and B input values. Fill in
the truth table in Table III for the circuit by considering all possible combinations of
input values (0 or 1) for inputs A and B. Note that one of the NAND gates acts like a
NOT gate that simply inverts its input: 0 in gives 1 out, and vice versa.
Repeat the exercise of filling out the truth table with the actual circuit.
TABLE III
LOGIC CIRCUIT TRUTH TABLE
Input A
0
0
1
1
Input B
0
1
0
1
Output Y
Fig. 3. Not gate and NAND gate circuit.
Experiment 4: DeMorgan's theorem (25 points)
Invert the inputs for a NAND gate (i.e., add NOT gates made from NAND gates, as in
Fig. 3 for input A, to both inputs) and show that you get an OR gate. That is, show that
you get a circuit that outputs a 1 when input A or input B is a 1. Use one 74HC00 chip
for the three gates needed. Be sure to record the circuit schematic and truth table.
Experiment 5: LED decoder (30 points)
A 7-segment LED display is shown in Fig. 4. Logic gates are used to make display
decoders (and everything else in a computer). The 74HCxx series of logic chips can
directly drive an LED, so we can use the 74HC00 (or 74HC86) chips to build a decoder.
The first step in the decoder design process is to make a truth table showing which
segments should light up when displaying a given number. We consider a circuit, with
three buttons, that displays a 0, 1, or 2, depending on which button is pressed. Table IV
shows the truth table for the circuit.
6
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu
ECE 1250 LAB 3
Fig. 5 shows the logic for segments a, d, e, f, and g. Using only NAND gates, complete
the design of the decoder. That is, design the circuitry to drive segments b, and c to
match the truth table in Table IV.
Fig. 4. 7-segment LED display segment labels.
TABLE IV
LED DECODER TRUTH TABLE
A
1
0
0
Inputs
B
0
1
0
Display
C
0
0
1
a
1
0
1
b
1
1
1
c
1
1
0
Outputs
d
1
0
1
e
1
0
1
f
1
0
0
g
0
0
1
Fig. 5. 7-segment LED display decoder partial schematic.
7
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu
ECE 1250 LAB 3
Extra Credit: Build the complete 7-segment display circuit (15 points)
Use your design from Experiment 5 to build the 7-segment display. You can get a 7segment LED display from the stockroom. (Make sure the display is a common cathode
display. The LED's are reversed in a common anode display.) Unfortunately, you will
have to experiment to figure out the pins on the display. Use a 1 kΩ resistor in series
with your myDAQ 5V supply as a test signal to drive a random pin. Connect another pin
to gnd. Try different pins until segments light up. Some displays have the common
cathode pin on pin 1, but nothing is guaranteed.
For the switches, you may purchase a DIP switch from the stockroom. These modules
are typically the size of a 16-pin integrated circuit and contain eight switches. The switch
looks like an open or a wire. When the switch is closed, the input (A, B, or C) is
connected to 5 V and is a one. When the switch is open, the input (A, B, or C) is pulled
down to gnd by a 1MΩ resistor.
Test your completed circuit and show it to the TA, as well as documenting it in your lab
notebook.
Extra Credit: How to make a NOT gate (inverter) out of an XOR gate (5
points)
Figure out how to use an XOR gate as a NOT gate. Hint: connect one input to a 0 or 1
(gnd or 5 V) power supply permanently. Draw, build, and test the circuit. Make a truth
table.
Extra Credit: How to make an XOR gate from four NAND gates (10 points)
Use four NAND gates to make an XOR gate. You may look online for the answer, but
this is a great puzzle to figure out on your own! Build the circuit and verify its truth
table.
8
UNIVERSITY OF UTAH DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
50 S. Central Campus Dr | Salt Lake City, UT 84112-9206 | Phone: (801) 581-6941 | Fax: (801) 581-5281 | www.ece.utah.edu