Download Improved 2nd-Order Multi-bit Noise-Coupled Sigma

北 京 大 学学 报 (自 然 科 学版 ), 第 48 卷 , 第 2 期 , 2012 年 3 月
Acta Scientiarum Naturalium Universitatis Pekinensis, Vol. 48, No. 2 (Mar. 2012) Improved 2nd-Order Multi-bit Noise-Coupled
Sigma-Delta Modulator for GSM Standard
LI Hongyi, WANG Yuan†, JIA Song, ZHANG Xing
Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing 100871;
† Corresponding author, E-mail: [email protected]
Abstract The authors propose an improved 2nd-order 3-bit noise-coupled SDM in which all the summation
before quantizer is moved to the input of the 2nd integrator, and time-constraint of the feedback DAC is relaxed by
introducing feedback path and delayed input signal. The modulator was designed and fabricated in a 0.35 μm
CMOS process using two active blocks. Under 100 kHz signal bandwidth and 12.8 MHz sampling frequency, 86.4
dB SNDR and 95.8 dB DR can be reached dissipating 9.84 mW power from a 3.3 V supply. The modulator can
satisfy the requirements of GSM systems.
Key words sigma-delta modulator; noise-coupled; feedforward; multi-bit; switched-capacitor circuit
改进的基于 GSM 标准二阶多位噪声耦合过采样调制器
王源 †
李宏义
贾嵩
张兴
北京大学微电子研究院器件与线路重点实验室, 北京 100871; † 通信作者, E-mail: [email protected]
提出一个改进的二阶三位噪声耦合过采样调制器, 它将量化器前所有的加法运算移动到第 2 个积分器的前
摘要
面, 并通过引入反馈通道和延时输入信号, 使反馈数模转换器的苛刻时序得到缓解。此调制器在 0.35 μm
CMOS 工艺下设计并生产, 整个调制器使用了两个有源模块。在 100 kHz 信号带宽和 12.8 MHz 时钟频率下, 完成
了 86.4 dB 的 SNDR 和 95.8 dB 的 DR, 3.3 V 电源电压下, 消耗 9.84 mW。此调制器能满足 GSM 系统的需求。
关键词
过采样调制器; 噪声耦合; 前馈; 多位; 开关电容线路
中图分类号
TN492
Sigma-delta analog-to-digital converter (SDADC)
using
oversampling
shaping
oversampling ratio and quantizer & feedback DAC
techniques is widely used under global system for
(digital-to-analog converter) resolution, respectively.
mobile
where
As seen from Eq. (1), the DR can be enhanced by
dB high dynamic range (DR) and
increasing anyone of the above three parameters,
100 kHz medium signal bandwidth with low power
however, besides the limitation of power dissipation
communications
typically
80-90
and
(GSM)
noise
where L, OSR and B denote loop filter order,
standard
[1]
dissipation are required . The performance of a
and die area, high L results in instability, the device fT
SD-ADC is dominated by its sigma-delta modulator
and wideband limit OSR, and B is constrained due to
[2]
(SDM), the DR
of which can be expressed ideally as:
DR = 1.5 ⋅ (2 B − 1) 2 ⋅
(2 L + 1) ⋅ OSR
π2 L
(2 L +1)
,
(1)
the exponential growth in circuit complexity. Thus, to
make a good trade-off among these design parameters,
novel and effective structures are needed to be
国家杰出青年科学基金(60925015)资助
收稿日期: 2011-03-25; 修回日期: 2011-06-17; 网络出版日期: 2011-12-21
网络出版地址: http://www.cnki.net/kcms/detail/11.2442.N.20111221.1620.014.html
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第2期
李 宏义 等 : 改 进 的 基于 GSM 标 准 二阶 多 位 噪声 耦合 过 采 样调 制器
since
developed continuously.
it
has
well-defined
gain
and
increased
[5]
Among all kinds of SDM topologies, noise-
no-overload range . And moreover, sampled-data
coupled (NC) with low-distortion, as shown in Fig.1,
method is more used for high resolution and medium
[3]
is no doubt a high power efficiency choice . After
bandwidth than continuous-time’s which suffers from
calculation, the output of Fig. 1 can be shown as
clock jitter, excess loop delay and poor linearity of the
Y ( z ) = STF( z ) ⋅ U ( z ) + NTF( z ) ⋅ E ( z ) ,
where STF( z ) = 1 , NTF( z ) =
(2)
1 − C ( z)
. Here H(z) is
1 + H ( z)
the loop filter, U(z) and E(z) are modulator’s input
signal and quantization error, STF(z) and NTF(z)
stand
for
signal
and
noise
transfer
function,
respectively.
As shown in Fig. 1, in a noise-coupled
modulator, the shaped quantization noise is introduced
feedback DAC[6].
In this paper, an improved 2nd-order single-loop
3-bit noise-coupled SDM has been fabricated in a 0.35
μm CMOS technology. The integrated modulator
shows a 95.8 dB DR with a signal bandwidth of
100 kHz and 12.8 MHz sampling rate, and the total
power consumption is 9.84 mW from a 3.3 V supply.
1
1.1
Proposed SDM Architecture
Modulator structure
by the additional C(z) branch. From Eq. (2), when C(z)
A classic 2nd-order 3-bit noise-coupled low-
=z−1, the quantization noise is extracted and then
distortion discrete-time SDM, as displayed in Fig. 2,
subtracted from the output of loop filter after a
owns all the advantages mentioned above. However,
one-cycle delay so that a 1st-order noise-shaping
there are two evidently drawbacks that restrict its
enhancement is obtained without an extra integrator .
circuit realization. On one hand, a fast adder for
And meanwhile, through adding a direct feedforward
summing up the modulator’s input, integrators’ output
path from the modulator input to the quantizer, ideally,
and noise-coupled output is required before the
low-distortion structure can cancel the input signal
quantizer so that an unpractical power-hungry active
form the loop filter and this leads to the reduced
adder or passive adder without signal attenuation has
[3]
multi-bit
to be employed. On the other hand, multi-bit feedback
quantizer should be used to improve loop stability,
DAC can not provide a delay-free path to cancel the
internal
signal
[4]
swings .
In
addition,
input signal at the input of the loop filter entirely. As a
result, ideal low-distortion cannot be realized using
non-ideal circuit blocks.
For the sake of overcoming the drawbacks of the
traditional noise-coupled feedforward SDM, a new
Fig. 1
Linear model of a single-loop noise-coupled
low-distortion SDM with an ideal feedback DAC
Fig. 2
structure has been proposed in Fig. 3. Here, a series of
signal flow graph (SGF) transformations have been
Block diagram of the traditional 2nd-order 3-bit noise-coupled feedforward SDM
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Fig. 3
第 48 卷
Block diagram of the proposed 2nd-order 3-bit noise-coupled SDM
performed as following. First, the input feedforward
b1 = 11/25, c2 = 12/25, d1 = 39/50, g = 0.0025 have
path to the quantizer has been moved to the
been chosen, and other coefficients of Fig. 3 can be
2nd-integrator’s input by introducing (1+b2z−1)
calculated by the above relations.
feedforward branch, d1 feedback path and a one-cycle
delay
of
the
modulator input[7].
Second,
the
noise-coupled path has been coupled to the loop filter
1.2
Stability analysis
After determining the topology and coefficients,
the NTF of Fig. 3 can be calculated as:
from quantizer input to the 2nd-integrator’s input by
NTF( z ) =
the d2 branch. And then zero optimization of NTF has
z 3 − 3z 2 + 3 z − 1
.
z − 1.2175z 2 + 0.4287z
3
(4)
been realized by importing g path[8]. Consequently,
From Eq. (4), we know that h(0) = NTF(∞) = 1 ,
the adder before quantizer is cancelled completely and
where h(n) is the inverse z-transform of NTF(z).
the strict time-constraint of the feedback DAC is
Therefore, there is no physically unrealizable delay-
relaxed by importing feedback path and delayed input
free loop in the SDM of Fig. 3 so that the proposed
signal to the loop filter. The STF of the proposed
structure is efficient[6].
modulator could be obtained by signal flow graph
Performing long division to Eq. (4), it yields
(SGF) and be shown as
NTF( z ) = 1 − 1.7825 ⋅ z −1 + 0.4011 ⋅ z −2
−1
STF( z ) = z ⋅
−2
+ 0.2526 ⋅ z −3 + 0.1355 ⋅ z −4 + ...
−1
c3 (b1c2 − b2 ) ⋅ z + c3 (b2 − 1) ⋅ z + c3
,
[1 + c3 (b1c2 − d1 − g )] ⋅ z −2 + [c3 (d1 + g ) − 2] ⋅ z −1 + 1
(3)
and
h(n) = 1.2175h(n − 1) − 0.4287 h(n − 2), n = 4,5, 6,...
When
After simple proof, we can obtain
⎧c3 = 1,
⎨
⎩b2 = d1 + g − 1,
h 1 = ∑ n = 0 h(n) ≈ 3.72 .
∞
(5)
Owing to multi-bit quantization, using Eq. (5),
we can obtain
STF( z ) = z −1 ,
any input with
i.e. a unity STF with a simple delay. Using the
max u (n) ≤ 2 B + 2 − h 1 = 23 + 2 − 3.72 = 6.28
n
well-known “delsig” toolbox[9] with 64x OSR and an
inverse Chebyshev NTF whose maximum out-of-band
is guaranteed not to overload the 3-bit SDM, and that
gain is 1.5, the coefficients of Fig. 2 can be obtained.
is −2.1 dBFS input amplitude[6].
Otherwise, along with the transformations from Fig. 2
1.3
to Fig. 3, d2 = 1/c3 has to be satisfied. Consequently,
202
Ideal behavior simulation
The ideal output spectrum of the traditional and
第2期
李 宏义 等 : 改 进 的 基于 GSM 标 准 二阶 多 位 噪声 耦合 过 采 样调 制器
proposed 2nd-order 3-bit noise-coupled SDM are
2
shown in Fig. 4 using 31.25 kHz and −5 dBFS sine
wave input with 8k samples. We can find an obvious
3rd-order noise shaping characteristic in both the two
SDMs, and an in-band notch appears in the output
spectrum of proposed SDM thanks to the zero
optimization scheme. Ideally, the two modulators both
can present more than 16-bit resolution.
After further signal scaling, the histogram of
integrators’ output swings of the proposed structure is
shown in Fig. 5. Since the output swings of the two
integrators are both suppressed to less than 25% of the
reference voltage. The swing requirements of their
operational transconductance amplifiers (OTAs) can
be relaxed.
Circuit Design
A
fully-differential
switched-capacitor
(SC)
circuit shown in Fig. 6 realized the proposed 2nd-order
3-bit noise-coupled SDM as Fig. 3. Two phase,
non-overlapping clocks Φ1 and Φ2 provide the
sampling and integrating phase for the overall
modulator, and the delay functions are implemented
by the Φ1e, Φ1o, Φ2e, Φ2o phases shown in Fig. 6 where
delayed clocks are used to reduce the effects of charge
injection. As for delay operation, a sampling branch is
divided into two absolute ones controlled by the two
pairs of non-overlapping clocks Φ1e, Φ2o, and Φ1o, Φ2e
respectively, and Φe and Φo will be only one efficient
during every Φ period. In the phase of Φ1o, the input
signal is sampled onto its branch. After a half cycle,
Φ2o arrives, and then the preceding input signal
sampled at adjacent Φ1e before one cycle of the Φ1o
mentioned above and held in this Φ2o branch will be
extracted for integrating. The following operations
perform the same. Thus, input delay can be realized.
By the above delay paths, an extra active component[3]
can be avoided to realize the noise-coupled function.
The input and output common-mode volta- ges are
both set to VDD/2 (1.65 V), and the reference voltages
Vref+ and Vref− are chosen as the single power supply
rails VDD (3.3 V) and ground. The key building blocks
of the modulator are explained as follows.
Fig. 4
Simulated output power spectrum density of the
SDMs shown as Fig. 2 and Fig. 3
2.1
Integrators
A
fully-differential
SC
integrator
typically
consists of an OTA, capacitors and switches, and their
non-idealities all can limit the performance of the
overall SDM[2]. Since the non-idealities of the latter
integrators could be suppressed by all the former ones
in
a
SDM,
the
1st
integrator
dominates
the
performance of the overall modulator.
As for an equivalent 3rd order, 3-bit SDM, using
linear and ideal analysis[2], the in-band quantization
noise power PQ can be calculated as
PQ =
Δ 2 ⋅ π2 L
12 ⋅ (2 B − 1) 2 L +1 ⋅ (2 L + 1) ⋅ OSR 2 L +1
,
(6)
where Δ is the full-scale range of the differential
Fig. 5
Integrators’ output swings of the proposed SDM as
Fig. 3 (Normallizing Vref+/− to +1/−1)
circuit. Using the parameters in this design, an ideal
−116.36 dB in-band quantization noise power can be
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北 京 大 学学 报 (自 然 科 学版 )
Fig. 6
第 48 卷
Schematic of the proposed SC 2nd-order 3-bit noise-coupled SDM
obtained. And then, the thermal noise power PkT/C for
where Sn is the 1st OTA’s input-referred noise power
the fully-differential SC circuit is about:
4kT
,
PkT/C =
Cs1 ⋅ OSR
spectral density. When 80 MHz GBW, 1 kΩ Ron and 10
(7)
where Cs1 is the sampling capacitor of the 1st
integrator. If Cs1 is chosen as 4 pF, a −101.9 dB kT/C
noise power is expected. Furthermore, the OTA’s
noise leakage and defective settling error power POTA
also limits the accuracy available of the SDM. On the
one hand, the noise leakage error due to finite OTA
DC gain of the 1st integrator can be estimated as:
b12 ⋅ Δ 2 ⋅ π2 L − 2
,
Pg =
12 ⋅ A2 ⋅ (2 L − 1) ⋅ OSR 2L −1
nV/(Hz)1/2 OTA input-referred noise are chosen, the
noise power can reach −101.07 dB. From the above
analysis, we can see that, under ideal quantization,
integrator dynamic response and the value of sampling
capacitor dominant the performance of the overall
SDM. Based on the above specifications, real SC
circuits could be implemented with essential design
margins.
Two traditional two-stage OTA with powerefficient dynamic common mode feedback loop
(8)
(CMFB)[10] has been used for the two integrators.
Table 1 presents the basic performance parameters of
the OTA used in the first integrator with 10 pF load
where A is the 1st OTA’s finite open-loop DC gain. As
capacitor. As seen from the table, the parameters of
A = 50 dB, the noise power could be −128.95 dB. On
real OTA circuit reach the specifications as above
the other hand, taking the integrator dynamic response
analysis. The output and input common mode voltage
into account, the OTA’s gain-bandwidth product
were both set to be VDD/2. Since the noise caused by
(GBW) and switch on-resistance Ron affect proper
the non-idealities of the 2nd integrator can be shaped
integrator settling, and their noise contribution can be
by the front-end one, its OTA could be relaxed and
shown as:
implemented based on smaller current consumption.
π ⋅ GBW ⋅ S n
,
Pd =
OSR ⋅ (1 + 4π ⋅ GBW ⋅ Ron ⋅ Cs1 )
204
(9)
In addition, correlated double sampling (CDS)
technique, which is a particular case of autozero (AZ)
第2期
李 宏义 等 : 改 进 的 基于 GSM 标 准 二阶 多 位 噪声 耦合 过 采 样调 制器
Table 1
1st OTAs’ performance (10 pF load capacitor)
Parameter
OTA’s is used up by the DEM circuit. Furthermore, in
order to realize a 3-bit feedback DAC path, compared
Value
DC gain
50.5 dB
with 1-bit one, extra fourteen SC branches have to be
GBW
125.1 MHz
used for a fully-differential circuit so lots of extra
Phase margin
64.2°
power and die area would be consumed.
Slew rate
82.5 MV/s
Output swing
± 3.1 V
In this work, a fully-differential flash topology
with static input scheme and a resistor ladder DAC[2]
Input-referred noise
9.6 nV/(Hz)
Power consumption
2.1 mW
1/2
are used as the 3-bit quantizer and 3-bit feedback
DAC, respectively, as shown in Fig. 7. By using this
structure, fifty-six SC branches for the feedback
technique based on sampling, is used to further reduce
DACs have been avoided, thus, plenty of power and
the effect of low-frequency flicker noise, offset and
die area for the extra switches are saved and the layout
finite DC gain of the 1st OTA. The hold capacitor,
workload is also relaxed. And moreover, as stated in
Ccds, which is used to store OTA’s noise and offset is
Ref. [12], resistor-based DACs have enough linearity
set to be large and equal to Ci1 as shown in Fig. 6 for
to implement multi-bit SDMs without DEM, and it
minimizing the flicker noise and enhancing the
also was proved by the 3-bit designs of Ref. [2]. In the
settling speed during integration phase[11].
flash ADC, the differential input signal is compared
Considering the above kT/C noise requirements,
OTAs’ load capacity, the realization of small feedback
coefficient of g path, and the design margin of real
circuits, the integrating capacitors of the 1st and 2nd
integrator have been chosen as 10 pF and 2.5 pF,
respectively. And then, the capacitance of other
capacitors
can
be
obtained
using
with a differential reference voltage, generated by the
resistor ladder, using a four inputs fully-differential
pre-amplifier, as shown in Fig. 8, followed by a
traditional latched comparator[13]. The seven latched
comparators provide thermometer code, and then, a
modulator’s
coefficients. In addition, sharing sampling capacitors
and redundant switches techniques are used to save
power and chip area. Here, both the input and
feedback signals are sampled onto the same sampling
capacitors to reduce kT/C noise effect, and the two
switches which connect the bottom plates of the
sampling capacitor have been simplified with a single
switch which shorts the bottom plates together. All
switches are realized by transmission gates and driven
by a pair of invert clock signals, and moreover, large
signal input positions have to use large size ones to
suppress switch non-idealities.
2.2
3-bit quantizer and feedback DAC
Multi-bit quantization with dynamic element
matching (DEM) is the most popular choices for the
realization of multi-bit SDMs. However, its penalty is
too large power consumption especially for a
noised-coupled SDM[3]. As seen from Ref. [3], over
40% of overall power which is comparable with all the
Fig. 7
Simplified schematic of the 3-bit ADA
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第 48 卷
estimate. The final experiment results are summarized
in Table 2. A −6 dB to full-scale magnitude 11.13 kHz
sinusoidal differential signal, which was used to
include the most significant 3rd, 5th and 7th harmonic
distortions within the bandwidth, was used as the
input of the presented SDM under a 12.8 MHz clock
rate,
and
the
modulator’s
output
output
power
voltage
spectrum
was
where
normalized
to
reference voltage is shown in Fig. 10 where the
1st-order noise-shaping enhancement could be found.
Fig. 8
Schematic of the fully-differential pre-amplifier
The plot of SNR and SNDR versus relative input
amplitude (dBFS) using 11.13 kHz input signal is
series of AND gates translate it into a 1-of-8 output
displayed in Fig. 11. As seen from the above two
code for the following encoder as shown in Fig. 6. The
figures, when the input amplitude becomes higher, the
1-of-8 output code is also used to select one of the
odd harmonic distortions appear, as a result, the
voltage references from the resistor ladder, and then
SNDR will be degraded. The figure-of-merit of
the DAC send it to modulator’s loop filter as feedback
SDMs[13] is defined as:
⎛ BW ⎞
FOM dB = DR + 10 log ⎜
⎟.
⎝ P ⎠
voltage. Fourteen 1 kΩ equal resistors are selected to
minimize the settling error of the generated reference
voltages, resistance mismatch and power consumption.
2.3
Other building blocks
(10)
A performance comparison of several designs
using 0.35 μm CMOS technology or noise-coupled
Two-phase non-overlapping clocks Φ1 and Φ2 as
shown in Fig. 6 were generated by a traditional clock
generator as Ref. [2], and other clocks for delayed
operation were generated by frequency dividers,
NAND gates and a series of inverters. As a result,
there were eight clocks to control the transmission
gate switches used for delay, and other eight clocks to
provide
common
non-delayed,
invert
non-delayed,
delayed
delayed,
phases
for
invert
the
transmission gates. A common ROM with clock
control is used to convert the 1-of-8 code to 3-bit
output.
3
Experiment Results
The proposed 2nd-order 3-bit noise-coupled
Fig. 9
Chip microphotograph of the proposed SDM
Table 2
Modulator performance summary
Parameter
Value
Supply voltage
3.3 V
Technology
Chartered 0.35 μm 2P4M CMOS
Sampling frequency
12.8 MHz
Oversampling ratio
64
Signal bandwidth
100 kHz
SDM was implemented using a 0.35 μm 2P4M CMOS
Peak SNR
94.7 dB
process, and Fig. 9 shows the die photo of the
Peak SNDR
86.4 dB
fabricated chip. The test bench was set up by Agilent
Dynamic range
95.8 dB
93 k SOC test environment and the output waves
ENOB
14.2 bits
present correct function. The output of the modulator
Power consumption
9.84 mW
was sent to an ideal 3-bit DAC the output of which
Core area
1.5 nm×0.6 mm
was further sent to a Matlab program for performance
FOM
165.9 dB
206
第2期
李 宏义 等 : 改 进 的 基于 GSM 标 准 二阶 多 位 噪声 耦合 过 采 样调 制器
Fig. 10
Output power spectrum density
with 65k samples of the SDM
Table 3
Reference
Dessouky, et al.
Yang, et al.
Ahn, et al.
[14]
[15]
[16]
Structure
Technology
Fig. 11
SNR and SNDR versus input amplitude
of the SDM
Performance comparison
VDD/V
BW/kHz
SNDR/dB
DR/dB
P/mW
FOM/dB
SC 1-bit
0.35 µm CMOS
1
25
85
88
0.95
162.2
SC 4-bit
0.35 µm CMOS
5
20
105
114
55
169.6
Switched RC
0.35 µm CMOS
0.6
20
81
82
1
155
Nguyen et al. [17]
Hybrid CTDT
0.35 µm CMOS
3.3
20
98
106
18
166.5
Lee et al.[3]
SC 3.9-bit NC
0.18µm CMOS
1.5
1900
81
82
8.1
165.7
This work
SC 3-bit NC
0.35µm CMOS
3.3
100
86.4
95.8
9.84
165.9
technique based on Eq. (10) was shown in Table 3. We
branches achieve delay function so that power-hungry
can see that this work presented excellent power-
active blocks are avoided. Consequently, the proposed
efficiency among them, so the effectiveness of the
SDM presents competitive FOM among a series of
proposed modulator could be validated.
mature designs.
4
Conclusion
References
Noise-coupled low-distortion SDMs have the
advantage of noise-shaping enhancement and reduced
internal
signal
swings.
However,
complicated
summation before quantizer, especially in a multi-bit
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