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TAPS Motherboard (V874) -- bugs, comparison with CAEN TDC, preliminary list 30nov99 TAPS test setup at Giessen TAPS Motherboards ser. no. 1 and 4 missing piggyback bitpattern readout via motherboard reprogramm motherboard eprom; presently being worked on bit AUXD4 partly remains on high. all other data lines are symmetric around WAUX (ca. 220 ns) at a certain VME-address (e.g. 0x120E) all AUXDs behave very strange (picture) Voff and Vset not controllable via VME commands presently we are using an external power supply for Voff and a potmeter and –5VA for Vset missing /W/R at motherboard DAC resistor R18 on motherboard not mounted smallest conversion time seems to be 14µs, and not 10µs 20 MHz clock instead of 32 MHz during data acquisition there are additional spikes on every (!!) signal on the motherboard (even without a piggyback) FASTRST and MBUSY are no longer stable if the repetition rate of the COM is larger than 2 kHz !!!! tested with and without a piggyback ================================================================== CAEN TDC ser. no. 5 Voff and Vset not controllable. How was this done in HADES test beam? by now we know that Voff is connected to AGND. Vset is still not controllable. zero- and overflow always suppressed TAPS Motherboard (V874) -- bugs, comparison with CAEN TDC, preliminary list 30nov99 Milano test setup at GSI (23.11.99) TAPS Motherboard ser. no. 1 Vset is not controllable – stays always at –11 Volts it must be a motherboard problem CAEN TDC ser. no. 7 Vset is controllable; Voff connected to AGND +/- 12V blocked with large capacities (µF) better resolution ? DGND and AGND are connected (on the piggyback or already on the motherboard?) +/- 12V coils shortened jumper S3 shortened ADC on the motherboard: pin 25 and 27 shortened (AGND and DGND), 100pF between pins 23 (positive analog input) and 25 ================================================================== Miscellaneous - we need actual schematics of the motherboard - one motherboard back to CAEN for checking TAPS Motherboard (V874) -- bugs, comparison with CAEN TDC, preliminary list 30nov99 TAPS TAC For TAPS the TAC should have a range of 600ns (500ns +/- 100ns). We want to measure the last 200ns. Maximum TAC-output should be +3.8V (DAC). That means for the analog TACOUT: 0V - 3.8V = - 7.6V - 0V = 400ns - 600ns 0ns - 400ns Two possibilities: 1) Voff of max. – 7.6V (specs of CAEN MB and Milano TAC: -4V) The possible maximum is –6V (TACOUT is collapsing). Not yet tested if this is stable and linear. With a Voff = -6V the TAC needs 4µs for the reset (FASTRST). 2) larger Feedback – capacity Tested with 660pF (instead of 330pF) working but: TAC needs more time for resetting. FASTRST should be 5.5µs wide worse resolution Questions concerning the Milano TAC - other components on the board than in the schematics (H – versions of ECL) why ? - Burr-Brown OPA413 instead of AD713 why ? - Voff < -6V we need ~ –8V - integrating capacity: 470pF why ? - resolution ?