Download ECE471-WIN15 [NEW] - Oregon State EECS

ECE 471 Midterm #1 WIN-2015
Name:
Student Number:
Midterm Score:
Problem 1 (Total 50 Points):
Problem 2 (Total 30 Points):
Problem 3 (Total 20 Points):
EXTRA CREDIT (TOTAL 10 Points):
Total:
NOTE: Make ALL Assumptions. Some partial credit given, given that
ALL assumptions are first made and written down.
When in doubt, use transistor models as assumed by the book, lectures, and HW.
When in doubt, MAKE ALL ASSUMPTIONS. I reward understanding, less
memorization.
Assume the front-stage min-size inverter is INV(min):
PMOS=8/2 [1.0um/0.25um]
NMOS=4/2 [0.5um/0.25um]
where 2=0.25um in your technology.
tOX = 10 Angstroms
Dielectric constant (Si-Oxide) = 3.9
PROBLEM 1: Logic Function
a) Implement logic function: Y
=
AB (C + D) in a single CMOS logic gate.
(10-points)
b) Size this logic gate, with its NMOS/PMOS transistors minimally sized to match
the minimum-sized inverter. Assume only CLOAD is the capacitance.
(SEE SIZING ON PAGE-1).
(10-points)
c) What is the input sequence that enables the fastest tPHL? Calculate this TDELAY,
assuming that you only have to worry about: RTRANS (of each transistor, which is
identical to the RTRANS of a minimum-sized inverter), CLOAD (loading on the
output Y), and CDIFF (Each transistor has ONLY-1 parasitic capacitance for both
the source/drain regions of the transistor -- you can ignore CGD and assume that
both CDB and CSB are equal to CDIFF).
(10-points)
d) What is the average dynamic power consumption of this gate? Assume CLOAD is
the only dynamic capacitance that is switching. (HINT: you need to know the
probability that the output will be switching from 0  1)
(10-points)
e) Draw a stick diagram for the logic gate from part a), with a goal to
minimize the diffusion capacitance. Please use horizontal lines for poly gates and
vertical lines for diffusion strips. Label your transistors, and if you make logical
connections, please show them.
DON'T FORGET SUBSTRATE VIA CONNECTIONS and the N-WELL!
(10-points)
f) Do this design using Pass-Gate Logic (NOT CMOS). Make sure you take care of all
possible input cases!
(EXTRA CREDIT: 20-points)
PROBLEM 2. Wire Resistance / Capacitance (30-points)
100um
M1
M8
100um
Gate oxide thickness of transistors
Dielectric Constant (Silicon Dioxide = SiO2)
Metal-1 Resistance RSQ (M1 closest to substrate)
Metal-8 Resistance RSQ (M8 farthest from substrate)
Distance M1 above grounded Si Substrate
Distance M8 above grounded Si Substrate
10 Angstroms
3.9
0.1 Ohms/sq.
0.01 Ohms/sq.
1.0 um
10.0um
a. Determine the optimal number of delay stages and the inverter sizing to drive
the final output capacitance (the output pad cap that is bonded to the off-chip PCB).
Assume no other wires nearby, and resistance/capacitance of Wire-1 are negligible.
(10-points)
b. The design from part-A is too optimistic, with respect to the package parasitics.
In reality, a 1-pF ESD diode is located on the output pad, preventing human ESD.
Still assume that Wire-1 resistance/capacitance is negligible.
Resize the tapered inverters and the final INV number to drive this output pad.
(10-points)
c. Now, a bad engineer who didn’t take ECE471, routed a VERY narrow M1 wire
between the final INV and the output metal pad (built in M8). This narrow wire
M1 is 0.01um wide and 10,000um long.
Assuming that the output resistance of the final INV is 1k-Ohms, how much
worse did the delay increase, with respect to part-a? (delay when Wire-1 is
negligible vs. Wire-1 is 0.01um(wide)/10000um(long). Ignore part-b for now.
(10-points)
d. Since you are such a nice guy, you decide to help him with his design by inserting
inverter buffers within this 10,000um wire and reduce it’s lossy-wire problem.
Determine the optimal number, positioning, and sizes of your “optimal buffer
insertion”.
(20-points EXTRA CREDIT)
PROBLEM 3. (20 pts) Scaling.
You are building a next generation cellphone CPU, in both a 10nm-CMOS processes.
The design specifications are tabulated below:
a) Tabulate the information below:
Supply Voltage (VDD)
Threshold Voltage (VTH)
# of Transistors / chip
Maximum Clock Frequency (1 / tD)
CLOAD(transistor) [capacitance/transistor]
ILEAK(transistor) [leakage-current/transistor]
Power (Dynamic)
Power (Static)
Energy (Dynamic)
Energy (Static)
10nm-CMOS
0.7V
0.2V
5 Billion
2GHz
0.1fF
100nA
10nm-CMOS
0.4V
0.2V
5 Billion
0.1GHz
0.1fF
10.0nA
NOTE: For dynamic power, assume chip is a HUGE inverter switching every CLK cycle!
(10 points)
b) Your company now ports the design to an embedded sensor that requires less
performance. The clock freq drops by 100x, VDD drops by 50%, the leakage current
drops by 10x.
Recalculate power (dynamic / static), and energy consumed (dynamic / static).
(10 points)