Download 6.7.3 Noise Margin Analysis

394
Chapter 6
Introduction to Digital Electronics
Exercise: Use the “Solver” on your calculator to find VH in Ex. 6.6.
Exercise: Repeat the calculations with γ = 0. Check your results with SPICE.
Answers: 1.90 V; 0 A; 0.235 V; 69.3 A
6.7.3 Noise Margin Analysis
We now explore the values of VI L , VO L , VI H , and VO H for the inverter with a saturated load
device. Remember that these voltages are defined by the points in the transfer function at which
the slope is equal to −1. In Fig. 6.27, the slope of the transfer function abruptly changes as M S
begins to conduct at the point where v I = VT N S . This point defines VI L :
VI L = VT N S = 1 V
for VO H = VH = VD D − VT N L = 3.4 V
(6.27)
Next let us find VI H and VO L . To find a relationship between v I and v O , we observe that the
drain currents in the switching and load devices must be equal. At v I = VI H , the input is at a
relatively high voltage and the output is at a relatively low voltage. Thus, we can guess that M S
will be in the triode region, and we already know that the circuit connection forces M L to operate
in the saturation region. Equating drain currents in the switching and load transistors:
i DS = i DL
vO
KL
K S v I − VT N S −
vO =
(VD D − v O − VT N L )2
2
2
W
W
K S = K n
and
K L = K n
L S
L L
(6.28)
The point of interest is dv O /dv I = −1. Solving for the corresponding value of v O is fairly involved,
so we will state the results here. The detailed calculations can be found on the MCD website.
VD D − VT N L
(W/L) S
VO L = √
with VT N L = VT O + γ
VO L + 2φ F − 2φ F and K R =
(W/L) L
1 + 3K R
VI H = VT N S
(6.29)
VO L
(VD D − VO L − VT N L )2
+
+
2
2K R VO L
Substituting the values from our saturated load inverter design gives
VO L = √
5 − VT N L
1 + 3(3.53)(3.39)
with
VT N L = 1 + 0.5
VO L + 0.6 −
√
0.6
These equations can be rearranged into a quadratic equation just as was done to find VH for the
saturated load inverter, but here we will use an iterative update process to find the solution to these
equations with our calculator or a spreadsheet. The steps in the iteration process are
1. Choose a starting guess for VO L .
2. Calculate the corresponding value of VT N L .
6.7
Static Design of the NMOS Saturated Load Inverter
395
3. Update the value of VO L .
4. Repeat steps 2 and 3 until convergence is obtained.
Table 6.9 provides an example of the iteration process for the inverter design in Fig. 6.26 with
K R = 3.53(3.39) = 12.0.
TABLE 6.9
ITERATION NUMBER
VO L
VT N L
V O L
1
2
3
4
0.5000
0.6359
0.6307
0.6309
1.1371
1.1686
1.1674
1.1674
0.6359
0.6307
0.6309
0.6309
Thus we have VO L = 0.63 V with VT N L = 1.17 V, and these values are used to find VI H .
VI H = 1 +
0.63
(5 − 0.63 − 1.17)2
+
= 1.99 V
2
2(3.53)(3.39)(0.63)
The values of VI H and VO L agree well with the transfer characteristic simulation results in Fig. 6.27.
The noise margins are given by
NM L = VI L − VO L = 1 − 0.63 = 0.37 V
NM H = VO H − VI H = 3.39 − 1.99 = 1.40 V
Compared to the inverter with the resistor load, the value of NM L is unchanged, but the value of
NM H has deteriorated because of the reduction of the high output level VH . In Eq. (6.29), K R
compares the transconductance of M S to that of M L , and we see that the noise margins improve
as the value of K R increases.
EXAMPLE 6.7
NOISE MARGIN CALCULATION FOR THE SATURATED LOAD INVERTER
Use the results of the noise margin analysis to find numerical values of the noise margins for
the 3.3-V saturated load inverter design from the last example.
PROBLEM Calculate the noise margins for the inverter in Design Example 6.5.
SOLUTION Known Information and Given Data: The NMOS saturated load inverter circuit in Design
Ex. 6.5 with VD D = 3.3 V, (W/L) S = 4.76/1, (W/L) L = 1/2.19, K n = 25 A/V2 , VT O =
0.75 V, γ = 0.5, and 2φ F = 0.6 V
Unknowns: The values of VI L , VO H , VI H , VO L , NM L , NM H
Approach: Use the given data to evaluate Eqs. (6.29); use the results to find the noise margins:
NM H = VO H − VI H and NM L = VI L − VO L
Assumptions: Equation (6.28) assumes M L is in the saturation region and M S is in the triode
region. Assume VI L = VT N S and VO H = VH as in Fig. 6.27.
396
Chapter 6
Introduction to Digital Electronics
Analysis: Based on these assumptions, noting that VT N S = VT O = 0.75 V, and finding VH =
2.11 V in Ex. 6.6, we have
VI L = 0.75 V
and
VO H = VH = 2.11 V
To find VO L and VI H , we first need to find the simultaneous solution to Eq. (6.29)
VD D − VT N L
3.3 − VT N L
3.3 − VT N L
VO L = √
=√
=
5.68
1 + 3(4.76)(2.19)
1 + 3K R
and the threshold voltage expression for the load device.
√ VT N L = 0.75 + 0.5 VO L + 0.6 − 0.6
Using our calculator or computer to help find the solution gives VO L = 0.428 V with VT N L =
0.870 V. VI H can now be calculated:
VI H = VT N S +
VO L
(VD D − VO L − VT N L )2
+
2
2K R VO L
0.43 (3.3 − 0.43 − 0.87)2
+
= 1.41 V
2
2(2.19)(4.76)(0.43)
Using the values just calculated, the noise margins are
VI H = 0.75 +
NM H = VO H − VI H = 2.1 − 1.41 = 0.69 V
and
NM L = VI L − VO L = 0.75 − 0.43 = 0.32 V
Check of Results: The noise margins are smaller than those calculated for the inverter in
Fig. 6.26(b), that was designed with a 5-V power supply but appear reasonable. We need to
check the assumptions underlying Eq. (6.29). For VI H and VO L ,
For M S :
VG S − VT N = VI H − VT N = 1.41 − 0.75 = 0.66 V
and
VDS = VO L = 0.43 V
For M L :
✔ Triode region is correct
VG S − VT N = VD D − VO L − VT N = 3.3 − 0.43 − 0.87 = 2.00 V
and
VDS = VD D − VO L = 3.3 − 0.43 = 2.87 V
✔ Saturation region is correct
Discussion: Our analysis indicates that a long chain of inverters can tolerate electrical noise and
process variations equivalent to 0.32 V in the low input state and 0.69 V in the high state. We
again observe that the values of the two noise margins are not equal.
Computer-Aided Analysis: The circuit shown here can be used to find the nose margins by
plotting the voltage transfer characteristic for the inverter. A dc sweep analysis is used to change
the value of VS from 0 V to 2.5 V in 10 mV steps. The NMOS transistors use the LEVEL = 1
model with KP = 2.5E-5, VTO = 0.75 V, GAMMA = 0.5, and PHI = 0.6 V. The transistor
sizes are specified as W = 4.76 U and L = 1 U for M S , and W = 1 U and L = 2.19 U for M L .
SPICE gives VH = 2.11 V and VL = 0.196 V. The VTC values agree closely with our hand
calculations.
6.8 NMOS Inverter with a Linear Load Device
397
ML
VDD
3.3 V
MS
VS
0
2.000
1.500
1.000
Slope = –1
0.500
VOL
0
VIL
0
+0.500
VIH
+1.000
+1.500
+2.000
+2.500
vS
Exercise: (a) Use your calculator to perform a “trial-and-error” analysis to find VOL and
VT N L = 0.87 V beginning with a guess of VOL = 0.80 V. (b) Verify that VOL = 0.429 V and
VT N L = 0.87 V indeed satisfy the two simultaneous equations in this example.
Answers: VOL sequence: 0.800 V, 0.413 V, 0.429 V, 0.428 V
6.8 NMOS INVERTER WITH A LINEAR LOAD DEVICE
Figure 6.21(d) provides a second workable choice for the load transistor M L . In this case, the
gate of the load transistor is connected to a separate voltage VGG . VGG is normally chosen to be
at least one threshold voltage greater than the supply voltage VD D :
VGG ≥ VD D + VT N L
For this value of VGG , the output voltage in the high output state VH is equal to VD D .