Download AN98507 - Connecting Cypress SPI Serial Flash to Configure Xilinx

AN98507
Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
Author: Takahiro Kuwano
AN98507 describes compatibility information between Cypress SPI Flash and Xilinx FPGAs, SPI Flash basics, and
considerations required in some cases.
1
Introduction
Xilinx FPGAs are programmable logic devices used for basic logic functions, chip-to-chip connectivity, signal
processing, and embedded processing. These devices are programmed and configured using an array of SRAM
cells that need to be re-programmed on every power-up. Several different methods of configuring FPGAs are
normally used. They include programming by a microprocessor, JTAG port, or directly by a serial PROM or flash.
Cypress's Serial Peripheral Interface (SPI) flash can be easily connected to Xilinx FPGAs in order to configure the
FPGA at power-up. The SPI configuration mode is supported for Xilinx FPGA families.
Table 1 through Table 3 show compatibility matrix of Cypress SPI Flash and Xilinx FPGA families.
Table 1. Xilinx Ultrascale FPGAs
Xilinx FPGAs
Kintex Ultrascale
IO Voltages
3.3V, 2.5V, 1.8V,
Cypress SPI Flash[1]
SPI Modes
x1, x2, x4
S25FL512S
1.5V[2]
S25FL256S[3]
S25FL128S[3]
Virtex Ultrascale
3.3V, 2.5V, 1.8V,
1.5V
x1, x2, x4, Dual x4 [4]
S25FL512S
[2]
S25FL256S[3]
S25FL128S[3]
Notes
1.SPI flash devices listed are supported by Xilinx Vivado v2014.1 and later version.
2.S25FL-S flash devices require 2.7-3.6V for VCC voltage and 1.8V, 2.5V or 3.3V for VIO voltage.
3.Supports both 64KB and 256KB sector sizes.
4.Virtex Ultrascale only supports 1.8V IO voltage for dual x4 mode.
Table 2. Xilinx 7-Series FPGAs and Zynq-7000 All Programmable SoC (Sheet 1 of 2)
Xilinx FPGAs
I/O Voltages
SPI Modes
Cypress SPI Flash [1]
S25FL512S
S25FL256S [2]
S25FL128S [2]
Artix-7
3.3V, 2.5V, 1.8V
x1, x2, x4
S25FL164K
S25FL132K
S25FL064P
S25FL032P
S25FL512S
S25FL256S [2]
Kintex-7
3.3V, 2.5V, 1.8V
x1, x2, x4
S25FL128S [2]
S25FL164K
S25FL064P
S25FL032P
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Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
Table 2. Xilinx 7-Series FPGAs and Zynq-7000 All Programmable SoC (Sheet 2 of 2)
Xilinx FPGAs
Virtex-7
I/O Voltages
1.8V
SPI Modes
x1, x2, x4
Cypress SPI Flash [1]
S25FL512S [3]
S25FL256S [2, 3]
S70FL01GS[4]
S25FL512S [4]
Zynq-7000
3.3V, 2.5V, 1.8V
x1, x2, x4
S25FL256S [4]
S25FL128S [4]
S25FL129P [4]
Note:
1.SPI flash devices listed are supported by Xilinx ISE v14.7 and Vivado v2013.3 and later version.
2.Supports both 64KB and 256KB sector sizes.
3.Virtex-7 only supports 1.8V IO on flash controller. Only VIO devices are qualified.
4.128Mb, 256Mb and 512Mb SPI are supported in single, dual parallel (higher throughput) and dual stacked (higher
memory) modes. 1Gb SPI only supported in dual stacked mode. Both 3V and 1.8V IO supported.
Table 3. Xilinx 3-Series, 5-Series and 6 Series FPGAs
Xilinx FPGAs
Spartan-3A
Spartan-3A DSP
I/O Voltages
SPI Modes
Cypress SPI Flash[1]
S25FL129P
3.3V
x1, x2, x4
S25FL064P
S25FL032P
S25FL129P
Virtex-5
3.3V, 2.5V, 1.8V
x1, x2, x4
S25FL064P
S25FL032P
S25FL128S
Spartan-6
3.3V
x1, x2, x4
S25FL129P
S25FL064P
S25FL032P
S25FL256S[2, 4]
S25FL128S [4]
Virtex-6
1.8V
[3]
x1, x2, x4
S25FL129P
S25FL064P
S25FL032P
Notes
1.SPI flash devices listed are supported by Xilinx ISE iMPACT flash programming tool 14.4.
2.Supports both 64KB and 256KB sector sizes.
3.Virtex-6 only supports 1.8V IO on flash controller. Use VIO devices or level shifters to interface.
4.Supported in ISE v14.6.
2
SPI Basics
Serial Peripheral Interface (SPI) is a simple 4-wire synchronous interface protocol which enables a master device
and one or more slave devices to intercommunicate. The SPI bus consists of four signal wires in a x1 data width
mode:

Master Out Slave In (MOSI) signal generated by the master (data to slave)

Master In Slave Out (MISO) signal generated by the slave (data to master)

Serial Clock (SCK) signal generated by the master to synchronize data transfers

Slave Select (SS#) signal generated by master to select individual slave devices, also known as Chip Select
(CS#) or Chip Enable (CE#)
In the x2 data width mode the MOSI signal becomes bidirectional. In the x4 data width mode the HOLD# and W#
pins are used for additional data output pins. Following SPI protocol, the master is assigned to the FPGA device
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Document No. 001-98507 Rev. *C
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Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
and the slave to the SPI flash device, as shown in Figure 1. Per this connection, the SPI flash is available to
configure the FPGA at power-up.
Figure 1. Direct Configuring FPGA Interface with SPI Flash - x1 Data Width
Master
MOSI
Slave
MISO
SCK
SS#
SPI Flash
FPGA Device
3
SPI Flash Connections to FPGAs
Figure 2 displays a simplified block diagram of the connection between SPI flash and FPGA. It shows the
configuration interface between FPGA and SPI flash, as well as the header for direct programming the SPI flash
for configuration data updates from a PC or embedded host.
Figure 2. Block Diagram of Configuration Interface with Re-programming Capability
SPI
Flash
FPGA
Header for
SPI Direct
Programming
PC
The detailed explanations of connection between Xilinx FPGA and Cypress SPI Flash are described in Xilinx user
guides and application notes below.
4

UltraScale Architecture Configuration User Guide (UG570)

SPI Configuration and Flash Programming in Ultrascale FPGAs (XAPP1233)

7 Series FPGAs Configuration User Guide (UG470)

Using SPI Flash with 7 Series FPGAs (XAPP586)

Virtex-6 FPGA Configuration User Guide (UG360)

Spartan-6 FPGA Configuration User Guide (UG380)

Virtex-5 FPGA Configuration User Guide (UG191)

Spartan-3 Generation Configuration User Guide (UG332)

Configuring Xilinx FPGAs with SPI Serial Flash (XAPP951)
Applying Voltages at Power-On
A race condition can exist between the SPI flash and FPGA at power-on. After completing its power-on reset
sequence, the FPGA sends a read command to the SPI flash to acquire the configuration data bitstream. If the
SPI flash has not yet completed its own power-on reset sequence, then it is not ready to respond to the FPGA
read command, which is issued only once. Under this scenario, the FPGA does not configure.
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Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
Let's focus on each device. After the three FPGA voltages reach their Power On Reset thresholds, the FPGA
starts its configuration process:

Clears its internal configuration memory (which takes approximately 1 millisecond)

De-asserts INIT_B, and selects SPI flash

Sends the appropriate read command to start configuration bitstream from SPI flash
After Cypress SPI flash reaches its minimum voltage, a power-up time delay (tPU) must be added to the SPI flash
power-on before it is available for read operations. Cypress S25FL-S and S25FL-P series requires 300
microseconds and S25FL1-K series requires 10 milliseconds for the minimum tPU.
The power-on time difference is considerable between the FPGA and SPI flash devices, which requires a circuit
solution to guarantee power-on compatibility between FPGA and SPI flash. The following solutions by Xilinx are
candidates for the designer:
1.
Use external control to hold the INIT_B or PROG_B pin Low until SPI flash has powered up reliably and is
ready to accept commands. For this solution, use an open-drain or open-collector output when driving
INIT_B or PROG_B pins. One example of external control is using a Power Monitor Supervisor device as
seen in Figure 3, and there are many available devices on the market from companies such as TI and
Analog Devices.
This is Cypress’s recommended method, due to its tolerance to temperature and voltage variations.
Figure 3. Power-on Reset Using Power Monitor Supervisor
+3.3V
VCCO_2
VCC
SPI
FPGA
INIT_B
Power
Monitor
RESET#
One example of the Power Monitor Supervisor is the Cypress MB3793. The RESET# signal from this device
is held Low until its power supply voltage reaches 2.76 V (VSH) + 30 ms tPR, which is shown in Figure 4.
Figure 4. RESET# Signal at Power-on for MB3793-27A
VCC
RESET#
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VSH
tPR
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Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
2.
Attach the R-C delay circuit to the INIT-B pin as seen in Figure 5, which forces the FPGA to wait for a
preselected period of time after its memory clearing process before allowing the FPGA to continue its
configuration process. Minimum INIT_B threshold voltage is used in determining the R-C component
values. In this case, the voltage input to INIT_B is 0.8 V. Using the component values recommended by
Xilinx. In Figure 5, the delay to configuration start is 90 milliseconds.
Note that this method is highly susceptible to temperature and voltage conditions. This method is not
recommended by Cypress.
Figure 5. Power-on Reset Using R-C Delay Circuit
+3.3V
VCCO_2
VCC
SPI
FPGA
150 kΩ
INIT_B
2.2 μF
4.1
Using Cypress S25FL 3V SPI Flash with Virtex-6
Interfacing Cypress S25FL 3V SPI flash with Virtex-6 2.5V I/O requires special considerations and automatic level
shifters are required for bidirectional signals. For further information, review the Xilinx Application Note XAPP899:
Interfacing Virtex-6 FPGAs with 3.3V I/O Standards at
http://www.xilinx.com/support/documentation/application_notes/xapp899.pdf.
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Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
5
References
1.
UltraScale Archtecture Configuration User Guide (UG570)
2.
SPI Configuration and Flash Programming in Ultrascale FPGAs (XAPP1233)
3.
7 Series FPGAs Configuration User Guide (UG470)
4.
Using SPI Flash with 7 Series FPGAs (XAPP586)
5.
Virtex-6 FPGA Configuration User Guide (UG360)
6.
Spartan-6 FPGA Configuration User Guide (UG380)
7.
Virtex-5 FPGA Configuration User Guide (UG191)
8.
Spartan-3 Generation Configuration User Guide (UG332)
9.
Configuring Xilinx FPGAs with SPI Serial Flash (XAPP951)
10. Xilinx Application Note XAPP899: Interfacing Virtex-6 FPGAs with 3.3V I/O Standards
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Document No. 001-98507 Rev. *C
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Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
Document History Page
Document Title: AN98507 - Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
Document Number: 001-98507
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
10/25/2007
Initial version
*A
03/03/2008
Updated Figures 3.1 and 3.2
Added section 4.3
*B
03/31/2011
Introduction: Added Spartan-6, Virtex-6
Updated section
SPI Flash Connections to FPGAs:
Added DOUT to table: Pin Descriptions for FPGA Configuration from SPI Flash
Updated table: SPI Flash Selection for Spartan Family FPGA Devices
Updated tabel: SPI Flash Selection for Virtex-5 Family FPGA Devices
Added table: SPI Flash Selection for Spartan-6 Family FPGA Devices
Added table: SPI Flash Selection for Virtex-6 Family FPGA Devices
Added figure: Spartan-6 serial (x1, x2, x4) Configuration from Cypress S25FL-P and
S25FL-K SPI Quad I/O Serial Flash Connection Diagram
Direct Programming SPI Flash:
Updated section
Using Cypress S25FL 3V SPI Flash with Virtex-6:
Added section
References:
Added references
*C
4909568
www.cypress.com
TKUW
09/05/2015
Added Table 1, Table 2, Table 3
Updated Table 1
Replaced detailed descriptions of Xilinx products with links to relevant Xilink application notes
Updated 4 Applying Voltages at Power-On
Updated Figure 4
Removed sections Direct Programming SPI Flash and Fastest Configuration Time
Updated links in 5 References
Updated in Cypress template
Document No. 001-98507 Rev. *C
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Connecting Cypress SPI Serial Flash to Configure Xilinx® FPGAs
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