Download Flash FPGAs need only 1 mW of static power

Flash FPGAs need only 1 mW of static power
Chips have 40% lower dynamic and 90% lower static power than previous devices
Typically using just 100 mA of dynamic current and 1 mW of static power, the
ProASIC3L flash FPGA devices feature 250 k to 3 M system gates with 40% lower
dynamic and 90% lower static power than previous-generation devices. The chips run at
1.2 to 3.3 V and have 36 to 504 Kbits of SRAM.
The devices operate at 350 MHz in 1.5 V and 250 MHz in 1.2-V systems and provide
FlashFreeze technology that enables instant on/off cycling. A license- and royalty-feefree implementation of the FPGA-optimized 32-bit ARM Cortex-M1 processor is also
available.
Offered in both commercial and industrial temperature grades, they feature 157 to 620
I/Os, one to six PLLs, and nonvolatile memory. (ProASIC3L family, from $3.95 ea/large
qty — samples available now.)
Actel, Mountain View, CA
Sales 650-318-4200
[email protected]
http://www.actel.com
Architecture Block Diagram
Product Table
Information
In the News
Related
Offering Low Power, High Performance, and Low Cost
As geometries shrink and focus on power budgets become increasingly
important, designers are turning to vendors for low-power solutions. Featuring
40 percent lower dynamic power and 90 percent lower static power than its
previous generation ProASIC3 FPGAs, and orders of magnitude lower power
than SRAM competitors, the new flash family combines dramatically reduced
power consumption with up to 350 MHz operation. As a result, designers in
high-performance market segments, such as industrial, medical, and scientific,
now have access to flexible, feature-rich solutions that offer speed, low power,
and low cost. The ProASIC3L family also supports the free implementation of an
FPGA-optimized 32-bit ARM® Cortex™-M1 processor, allowing system designers
to select the Actel flash FPGA solution that best meets their speed and power
design requirements regardless of application or volume. Combined with
optimized software tools using Power-Driven Layout (PDL), this provides instant
power reduction capabilities.
Actel News
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Actel's ProASIC3L Family Balances Low Power, Speed and Low Cost
Webcasts
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Actel - Redefining Power
Cortex-M1 with Actel — Small, Fast, and Free
Actel's Low Power IGLOO FPGAs
The Only True Nonvolatile Flash FPGAs
Product Features
Key Features
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40% dynamic power savings
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Up to 90% static power savings
Single-chip, single-voltage operation and live at power-up
Optimized for high performance
Cost-optimized, reprogrammable, and nonvolatile
1.2 V or 1.5 V core voltage support
Wide range of I/O voltage support from 1.2 V
Innovative Flash*Freeze technology for instantaneous switching from
active to static mode
Free Cortex-M1 (ARM FPGA Processor) support for all devices
In-System Programming (ISP) with optional on-chip AES decryption
Firm error immune
Architecture Block Diagram
Move the cursor over the numbers below to learn more about ProASIC3L flash
FPGA architecture.
Flash*Freeze enables ProASIC3L devices to switch between active and static
states instantaneously within 1 μs. This feature simplifies power management
so there is no need to turn off power supplies or clocks at the system level and
the device retains register and SRAM content while in Flash*Freeze mode.
Product Table
ProASIC3L Family
ARM Cortex-M1-Enabled
A3P250L
A3P600L
A3P1000L
A3PE3000L
M1A3P250L M1A3P600L M1A3P1000L M1A3PE3000L
System Gates
250 k
600 k
1M
3M
VersaTiles (D-Flip-Flop)
6,144
13,824
24,576
75,264
RAM kbits (1,024 bits)
36
108
144
504
4,608-Bit Blocks
8
24
32
112
FlashROM Bits
1k
1k
1k
1k
Secure (AES) ISP2
Yes
Yes
Yes
Yes
Integrated PLLs in CCCs
1
1
1
6
VersaNet Globals
18
18
18
18
Std.+/LVDS
Pro
I/O Standards
I/O Banks (+JTAG)
Std.+/LVDS Std.+/LVDS
4
4
4
8
Typical Static /
Flash*Freeze Power (mW)
at VCC=1.2 V
0.40
0.66
1.06
3.30
Typical Sleep Power (µW)
at VCCI=1.5 V
11
11
11
22
Speed Grades
Temperature Grades
Std., -1
Std., -1
Std., -1
Std., -1
C, I
C, I
C, I
C, I
147/65
Single-Ended I/O / Differential I/O Pairs1
VQ100
68/13
PQ208
151/34
154/35
154/35
FG144
97/24
97/25
97/25
FG256
157/38
177/43
177/44
FG324
221/110
FG484
235/60
300/74
FG896
341/168
620/310
Notes:
1. Advanced information subject to change.
2. AES not available for ARM-enabled ProASIC3L devices.
Low Power Benefits
The ProASIC3L devices incorporate proven Flash*Freeze
technology, which allows fast switching (within 1 µs) from an
active to a static state. No additional components are
required to switch from or to these states, thereby
eliminating the need for additional I/O or clock management
circuits. This capability makes dynamic power reduction
possible by quickly switching the device in and out of
Flash*Freeze mode during periods of inactivity. A ProASIC3L
device can operate from a single voltage (1.2 V or 1.5 V core supply) and offers
secure in-system programming (ISP) for valuable field programming upgrades.
The ProASIC3L family supports up to 3 M system gates with advanced I/O
options, user nonvolatile memory, Level 0 live at power-up (LAPU) support, and
the industry's most secured AES encryption capability.
The total power savings can add to more than 40 percent of dynamic power and
90 percent of static power compared to a traditional high performance FPGA
design.
IP and Solutions
Search for ProASIC3L IP cores.
Technology Solutions
Optimized for dynamic and total power reduction using 1.2V
core, Flash*Freeze technology while meeting most
demanding performance needs. » More
Low Cost
The world's lowest cost FPGA solution offering industryleading unit cost and lowest total system cost.
High
Performance
Enhanced, high-performance architecture up to 350 MHz
operation and best-in-class logic utilization.
Single Chip
Does not require additional configuration nonvolatile
memory in order to load the device configuration data at
every system power-up, which reduces cost and increases
security and system reliability.
Secure ISP
Supports built-in AES decryption engine and industry-leading
flash-based AES-128 key for secure remote field updates
over public networks with encrypted bitstream.
User
Nonvolatile
Memory
1,024 bits of on-chip, user accessible, nonvolatile FlashROM
that can be used in diverse system applications.
Greatly simplifies system design, making the device
available to perform critical system setup tasks and reduce
bill-of-materials costs and PCB area. » More
Utilizes a 128-bit flash-based lock and inherent flash
technology features, providing the most impenetrable
security for programmable logic designs. » More
Flash cell configuration element cannot be altered by highenergy neutrons and is therefore immune, unlike SRAMbased FPGAs. » More
Design Software
Actel's Libero Integrated Design Environment (IDE) is
a comprehensive FPGA development tool suite that offers the latest and bestin-class tools from leading EDA vendors such as Mentor Graphics, SynaptiCAD,
and Synplicity. Libero IDE offers premier physical implementation tools and
options for place-and-route, setting constraints, and analyzing timing. Libero
IDE's Power-Driven Layout automatically reduces the power consumption of
your ProASIC3L design, plus you can easily pinpoint sources of power
consumption using SmartPower. SmartPower provides a hierarchical view of the
entire design, as well as detailed views that enable you to quickly realize the
component, location, and magnitude of power sources inside the design.
Starter Kits and Programming
The ProASIC3L and M1-enabled ProASIC3L Starter Kits provide complete
evaluation solutions for examining both the low-power ProASIC3L device and
the ARM Cortex-M1 in a low-power M1-enabled ProASIC3L device. The
ProASIC3L and M1-enabled ProASIC3L development boards have on-board
voltage regulation, enabling you to set some of the I/O bank voltages
independently. ProASIC3L devices can operate down to a core voltage of 1.2 V
or 1.5 V, but require the core to be held at 1.5 V during programming. A
regulator circuit to allow control of the core voltage is provided on each board.
The core voltage may be switched manually or electronically for programming
purposes and returned to the 1.2 V setting for the lowest power consumption
during normal operation.
Device pre-programming is supported through Silicon Sculptor 3 and Silicon
Sculptor II programmers. For in-system programming (ISP), the low-cost PCbased FlashPro3 programmer may be used.
For the ProASIC3L trace and debugging, Synplicity provides logic analysis
software Identify AE and FS2 provides Logic Navigator.
Related Information
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ProASIC3 FPGAs
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