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ECE 570 Session 8 Computer Aided Engineering for Integrated Circuits IC 752-E Transient analysis – 2 Discuss the error control in SPICE 1. Truncation and round-off errors 2. “Optimal” computing of transients 3. Estimation of LTE 4. Control of integration step size in SPICE Supplemental reading: Vladimirescu, The SPICE Book, Chapters: 6, 9.4 - 9.5, 10.4 1. 1.Truncation and round-off errors Truncation error – caused by the algorithm (method). Round-off error – caused by the finite word length in the computer representation of the number. Both are important, but the round-off error will be discussed later in relation to “linear solvers”. This lecture is exclusively dedicated to the discussion of truncation errors. Notation (reminder): v ( t n ) - theoretical value of v ( t ) at t = t n vn - approximation to v ( t n ) computed numerically 2. GLOBAL ERROR (precisely Global Truncation Error -GTE) After n-steps in computing the error is en = v ( t n ) − v n and it is called GTE. This error is of interest to a user but it is not computed and not available in general. User does not have direct control over GTE. However, this error is important in applications! LOCAL TRUNCATION ERROR (LTE) Definitions etn = v ( t n ) − vn is the LTE, which can be estimated and computed, vn is a numerically computed approximation to v ( t n ) with exact starting values. LTE – is an error due to a numerical approximation in a single step calculation (error committed in one step of calculation). Global Error – contains effects of LTE in all previous steps. 3. Example/Graphical Illustration of LTE V (t ) exact V (t2 ) V2 et2 e2 calculated V (t1 ) t1 t2 tn t LTE is not what we directly want to know, but it is the only error that can be estimated and effectively controlled. 4. Discussion of LTE Consider B-E : vn+1 = vn + hn+1vn+1 or else: vn = vn−1 + hn vn Definition of LTE et = v ( t n ) − v n n where vn = v ( t n−1 ) + hn vn Note: this is the exact starting value for the step n. 5. Consider T-R: v n +1 hn+1 ( v n + v n +1 ) = vn + 2 The T-R formula can also be written (for a shifted subscript) as vn = vn−1 + hn ( vn−1 + vn ) 2 To define LTE we need to compute v n = v ( t n −1 ) + hn [ v ( t n −1 ) + v n ] 2 These are the exact values – never known! (except for a linear system) LTE can only be computed for linear systems. But importantly, it can be estimated for nonlinear systems! 6. Exercise 1: Assume the RC circuit. USE B-E method for computation. Assume: R + E + - C V - E = 5 = const v (0) = 0 h = 0.2 RC = const Compute first five steps: V1 ,V2 , ,V5 Calculate: etn , en ( you need the analytical solution for computing these errors). Compare en and etn . 7. 2. “Optimal” computing of transients Two major factors are considered in computing the transients - accuracy (errors in computing) - CPU time. Typically circuit models are with “built-in” errors, due to approximations in active device models or idealization of passive components. For this reason errors due to computing, or so-called numerical errors are tolerable if they do not exceed the effects of these built-in errors. Reduction of numerical errors occurs at the expense of increased computing effort (increased CPU time). More accurate computations are more expensive. Consequently too accurate computation is not desirable. In other words we want to compute with errors, which do not exceed “built-in” errors. In typical problems 0.1% or more often 1% numerical errors are acceptable. 8. “Optimal” computing occurs when numerical errors are just at the level of tolerance. This is called “optimal” because under those conditions the acceptable results are computed at a minimum CPU time. In order to conduct “optimal” computing we need to be able to: 1. predict numerical errors, 2. obtain error tolerances/bounds, 3. control the computing process and errors. 9. 3. Estimation of LTE Numerical analysis supplies the following estimates: 1 2 ( 2) d 2v ( 2) B-E : LTEn ≅ − hn v ( t n ); v (t ) = 2 4 dt 1 second order T-R : LTEn ≅ − hn3 v ( 3) ( t n ) ; 72 Ck LMM: LTEn ≅ ( hn )k +1 v ( k +1) ( t n ) ; k-th order ( k + 1)! where C k - is the constant of the method d kv (k ) Derivatives : v ( t ) = k are usually not available and must be dt computed numerically (approximated, estimated). Derivatives (or precisely their approximations) are computed using Divided Differences (DD). 10. Numerical mathematics supplies following formulas for divided differences: v n − v n −1 DD1 ( t n ) = ≅ v (1) ( t n ) hn DD1 ( t n ) − DD1 ( t n−1 ) 1 ( 2) DD2 ( t n ) = ≅ v ( tn ) hn + hn−1 2 DDk +1 ( t n ) = DDk ( t n ) − DDk ( t n−1 ) k i =0 hn− i v ( k +1) ( t n ) ≅ ( k + 1)! 11. Substituting proper DD to LTE estimates we get: 1 LTE n ≅ − hn2 DD2 ( t n ) 2 1 T-R : LTE n ≅ − hn3 DD3 ( t n ) 2 LTEn ≅ C k ( hn )k +1 DDk +1 ( t n ) . LMM : B-E: EXERCISE 2: For RC circuit, use B-E as in EXERCISE 1 and compute DD and LTE estimates. 12. 4. Step size control using LTE Concept: the estimates of LTE depend on step size hn . Consequently LTE can be controlled by the value of hn . Given an error bound, EBn , for LTE we state the step size control problem as follows LTE n ≤ EBn Using the LTE estimates (for T-R and LMM) we obtain: C k ( hn )k +1 DDk +1 ( t n ) ≤ EBn for T-R, (2nd order method) Note : C k = − 1 12 Ck = − 1 for B-E, (1rst order method) 2 or else we can write 1 EBn hn ≤ C k DDk +1 ( t n ) k +1 which defines the UPPER STEP BOUND, hnE . hnE 13. Comments: 1o computation of bound for the step size: hnE is expensive 2o computation of DD is error prone. Step control in multivariable circuits 1. Each variable (indicated by the superscript “i”) has a bound EBni for LTE i = 1, 2, ,I, I - is the number of variables. 2. Each variable has an estimate of LTE in the form Ck k +1 LTE ≅ ( hn ) ( k + 1) ! i n [i ] v( k +1) (tn ) or introducing the expression for DD of “i” variable we obtain LTEni ≅ C k ( hn )k +1 DDk[ +]1 ( t n ) i 14. Using the condition LTE ni ≤ EB i for every variable ( i = 1, 2, for the step-size , I ) we can write the following inequality 1 i n [i ] k +1 EB hn ≤ min i C k DD ( t n ) k +1 which defines the upper bound for step size in the form 1 i n [i ] k +1 EB hnE = min i C k DD ( t n ) k +1 . 15. 5. Control of integration step size in SPICE a) determination of error bounds EBni = ε a + RELTOL max { xn[ i ] , xn[ i−]1 } ABSTOL εa = VNTOL CHGTOL b) computation of step upper bound : hnE 1 EB i TRTOL hnE = min i Ck DDk[ i+]1 ( t n ) k +1 TRTOL – parameter (empirical) Default : TRTOL = 7 c) step size selection: at each step we need to evaluate the size of hn using the bound hnE . t 0 TSTOP 16. STEP (ERROR) CONTROL OPTIONS IN SPICE 1. LTE Based Strategy (LTBS) for error control Uses hnE - bounds of step size. The error control is usually expensive, especially when many step changes are involved. The control is economical when a few step adjustments are needed. V (t ) tn +1 tn −1 tn 3 tn+1 2 tn +1 1 tn+1 t these steps are rejected due to the accuracy requirement Illustration of a typical waveform in digital systems with the step adjustment process, where many calculations are rejected. 17. 2. Iteration Count Based Strategy (ICBS) No computing of error estimates Inexpensive Suitable for circuits with many transients Available in some versions of SPICE 18. SPICE Error Bounds (after Vladimirescu) For currents of capacitors and voltage across inductors ε x = ε a + ε r max { xn+1 , xn } xn+1 , xn - current of capacitor or voltage across inductor εa = ABSTOL − for current VNTOL − for voltages ε r = RELTOL Charge error (if the charge is used as a circuit variable) ε x = εr ⋅ max { xn+1 , xn , ε qa } ; ε r = RELTOL hn ε qa = CHGTOL , xn+1 , xn - charge (as a circuit variable). Analogous formulation for NL inductor fluxes (if applicable) may be used. Error Bound (EB) EBn+1 = max {ε x , ε x } . 19. Estimate of step size hˆn+1 = EBn+1 C k DDk +1 1 k +1 Experience showed that this formula is too conservative and as mentioned before a corrective parameter TRTOL yielding better estimate hn+1 E = hn+1 EBn+1 TRTOL = C k DDk +1 1 k +1 was introduced. Default : TRTOL = 7 (SPICE 2) The value of TRTOL can be reset using .OPTION ...., TRTOL=#…,... 20. Selection of step-size control mechanism and integration method in SPICE a) LTE Based Strategy (LTBS)-(available in all SPICE’s) b) Iteration Count Based Strategy (ICBS) – SPICE2 only Selection of the step control mechanism is done through the parameter LVLTIM available on .OPTION command. The LVLTIM is available only with the TR method. LVLTIM=1 selects : ICBS LVLTIM=2 (default) selects : LTBS Selection of integration method is done through the parameter METHOD available on .OPTION command. There are 2 methods available: Trapezoidal (T-R) method is default one. It can be explicitly selected by setting METHOD = TRAP (default). Gear’s method is selected by setting METHOD = GEAR Additional parameter selecting the method order (number of steps) is: MAXORD = 2 <3,…,6> This selection is available only with GEAR. With GEAR the LTBS step control is used exclusively. 21. Details of LTBS control of step size in SPICE hn+1 = hn hn tn −1 tn hn + 2 tn +1 tn + 2 t hn +1 h hn +1 = n 8 22. Implementation of Step Control Solve at t n+1 If (iter_num < ITL4) Compute hn+1 = f ( LTE ) if ( hn+1 < 0.9hn+1 ) then Reject t n+1 hn+1 = hn+1 ; recompute else Accept t n+1 and results hn+ 2 = min {hn+1 , 2hn , Tmax } Else reject t n+1 , hn+1 = hn / 8 if ( hn+1 ≥ hmin ) recompute else : TIME STEP TOO SMALE -- error message 23. ICBS – Strategy Based on Iteration Count Given two integers : ITL3 (default = 4), ITL4 (default = 10) I n - N-R iteration count at step t n Notation : I nmx - iteration count after convergence Strategy: I nmx < ITL3 then hn+1 = 2hn ITL3 ≤ I nmx ≤ ITL4 then hn+1 = hn I n > ITL4 then hn+1 = hn 8 Step is rejected and re-computation of values is necessary. Check of the condition: hn+1 ≥ hmin is also performed. 24.