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Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
Design of BiCMOS based low temperature coefficient
bangap reference
Deepa Talewad , Anilkumar Nandi
1 Student,
B.V.B College of Engineering and Technology, Hubli, India, [email protected]
2Professor, B.V.B College of Engineering and Technology, Hubli, India. [email protected]
ABSTRACT. BiCMOS bandgap reference which having advantage over MOS based BGR in terms
of its accuracy at its reference output and very less temperature coefficient. This paper presents
bandgap reference circuit with folded cascade operational amplifier(opamp) in order to improve the
final Vref output of bandgap reference. The temperature stability of output can be improved by using
an extra trimming circuit in voltage mode architecture of bandgap reference still operating with less
power consumption. Using only first order temperature compensation technique the proposed circuit
gives output voltage of 1.181V with 0°C to 100 °C temperature variation which corresponds to temperature coefficient of 19ppm/°C. The output reference voltage which exhibits a variations of 7mV with
supply range of 1.62V to 1.98V at typical process corners. A single stage folded cascode opamp which
is included in the proposed bandgap which improves the output voltage, power supply rejection ratio of
BGR and input common mode range, output swing and stability at opamp and BGR output. The simulation results shows that power supply rejection ratio of proposed BGR is -43db from dc to 30KHz
frequency, gain of folded opamp is 78db,Phase margin is 70 degree, input offset of opamp is 1.96µV
and closed loop gain of opamp in BGR is 118db. The total current for overall BGR is 12µA and total
power consumption is 18.4µW.The proposed bandgap reference is simulated using Mentor Graphics
pyxis tool, EldoSpice simulator in 130nm CMOS technology. The proposed BGR output will be use in
low dropout regulator circuit which is operating at 3.3 supply and gives regulated output of 1.8V.
Keywords: Voltage mode architecture, PSRR, Temperature coefficient, PTAT, CTAT voltage, trimming
INTRODUCTION
A stable high performance bandgap reference circuit plays vital role in the high performance
circuits like ADC, DAC, LDO, Charge pump circuit. A voltage reference must be highly precise and stable with respect to temperature, supply, process and load variations. High power
supply noise rejection ratio (PSRR) of LDOs which merits the noise immunity, since high
PSRR of LDOs mostly depends on PSRR of voltage reference [1]. This paper presents design
of BiCMOS based voltage reference with good PSRR and low temperature coefficient(TC)
which is most important in terms of accuracy of system [3]. A Brokaw CMOS bandgap reference presented by Yongsheng Yin [6], using current mode architecture which gives Vref of
0.5V and better PSRR but drawback of circuit is Vref output is better PSRR but drawback of
circuit is Vref output is very sensitive with respect to temperature because of sensitivity of
resistor at the output and power dissipation in terms of mill volts. This paper presents CMOS
bandgap reference with voltage mode architecture with trimming circuit in order to get low
temperature coefficient with better PSRR and also start up problem in the conventional
bandgap reference (BGR) is avoided using simple startup for proper operation of circuit. The
proposed BGR uses PNP bipolar transistor instead of NPN transistor. Since NPN bipolar transistor contributes high current gain, high matching precision, and its difficult to implement the
NPN transistor on CMOS process [6]. The proposed circuit produces the reference voltage of
1.181V, which is sufficient for given application (Low dropout regulator) operating at 3.3V
supply and gives regulated output of 1.8V. By using voltage mode architecture and bipolar
transistors, the proposed circuit produces very less TC of Vref with only first order temperature compensation and greatly reduces the circuit complexity as compared to the papers [4]
[5]. Compared to conventional BGR which uses two stage operational amplifier(opamp) the
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
proposed circuit uses single stage folded cascode opamp in order to get highly stable output at
the output of BGR with low TC since opamp input offset is very low(in terms of 1.96µV).
CONVENTIONAL BGR PRINCIPAL
The basic principal is VBE (Base to emitter) voltage of bipolar transistor which generates
complementary to absolute temperature (CTAT) voltage with negative temperature coefficient and difference between VBE of two bipolar transistor (Thermal voltage VT ) which carrying unequal current densities which exhibits proportional to absolute temperature voltage
with positive temperature coefficient (PTAT). The final Vref output is addition both PTAT
and CTAT voltage with near zero temperature coefficient is generated. The typical output of
BGR is 1.181V, which is close to bandgap voltage of silicon at room temperature.
Negative TC Voltage generation
Generally the forward voltage of pn junction diode exhibits negative temperature coefficient
(TC), and also the base to emitter voltage of bipolar transistor exhibits the similar characteristics. For bipolar device we can write as
IC = IS exp
Where
VBE
VT
(1)
𝐼
𝐼𝑆
𝑉𝐵𝐸= 𝑉𝑇 ln( 𝐶 )
and 𝑉𝑇 =
𝐾𝑇
𝑞
(2)
IS is saturation current is given by
−𝐸𝑔
𝐼𝑆 = bT(4+m) exp( 𝐾𝑇 )
(3)
b= proportionality factor and m= material constant proportional to electron mobility.
Therefore negative TC is given by
δVBE
δT
=
VBE –(4+m)VT −
Eq
q
and
T
(Assuming IC is constant)
δVBE
δT
=
VBE –(3+m)VT −
Eq
q
T
(4)
(Assuming IC is function of temperature.)
Positive TC voltage generation
If two bipolar transistors operate in unequal current densities then difference between their
base to emitter voltage directly proportional to their absolute temperature [7]. While positive
TC is given by
∆𝑉𝐵𝐸 =𝑉𝐵𝐸1- 𝑉𝐵𝐸2 =𝑉𝑇 ln(n)
(5)
𝛿 ∆𝑉𝐵𝐸
𝛿𝑇
𝐾
= 𝑞 ln(n)
(6)
Then BGR output reference is given by
VREF= IR2+VBE
=
R2(
∆𝑉𝐵𝐸
)+
𝑅1
𝑉𝐵𝐸
(7)
The second term in the above equation IR2 has positive temperature coefficient of
+0.086mV/°C, and first term VEB has negative temperature coefficient of -2mV/ °C at room
temperature. R2/R1 ratio is adjusted such that near zero temperature coefficient of Vref is
achieved theoretically [3]. The temperature coefficient of final Vref output is given by
𝛿𝑉𝑅𝐸𝐹
𝛿𝑇
=
𝑉𝐵𝐸 –(3+𝑚)𝑉𝑇 −
After putting
𝑇
𝛿𝑉𝑅𝐸𝐹
=0,
𝛿𝑇
𝐸𝑔
𝑉𝑅𝐸𝐹 = (3+m) 𝑉𝑇 + 𝑞
𝐸𝑞
𝑞
𝑅2 𝐾
+𝑅1 𝑞 ln(n)
(8)
in above equation the final BGR output is given by
(9)
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
Where Eg is bandgap of silicon at room temperature =1.12eV, VT =25mV thermal voltage, m
is constant factor= -1.5 for silicon. After putting all values Vref=1.25V at room temperature.
PROPOSED BGR PRINCIPAL
The drawback conventional architecture is the opamp output is not stable and hence BGR
output, and also start up problem in the circuit. In current mode architecture output is very
sensitive with respect to temperature and high power dissipation in the circuit which is in
terms of mill volts [1] [6].The proposed voltage mode architecture consists of startup circuit,
folded cascode opamp, and core BGR shown in figure 1. For the operation of circuit there are
two voltages VEB and VEB are generated with negative and positive TC respectively. A diode
connected PNP transistor Q3 at the output generates VEB voltage which having negative
TC(CTAT characteristics) and the pnp transistors Q1, Q2 which carries equal currents and
having their areas in ratio of 1:4
Figure 1. Proposed BGR architecture
Figure 2. Folded cascade opamp with biasing
Since both transistors Q1 and Q2 are unequal sizes which exhibits difference voltage(V EB)
across resistor(Difference between node a and b). The voltage across resistor VEB exhibits
PTAT characteristics. The resistor R1 decides current flowing in BGR legs(Both carries equal
current) and same PTAT current is mirrored in the output branch. The voltage across R2 is
PTAT voltage and VEB of Q3 exhibits CTAT voltage, the final output is addition of both voltages [5]. The value of R2 is selected such that the Vref output is having very less temperature
coefficient.
Trimming circuit
The trimming circuit is added to reduce the temperature coefficient of Vref output at different
supply and corners. A 4 bit series trimming circuit is used with resistors values are selected by
calculating fine and coarse variations of resistors at different supply and process corners as
shown in figure 1.Coarse resistor value is selected for large variation of resistor at different
supply variations and corners. RMIN0, RMIN1 and RMIN2 minimum resistors values obtained at
SS, TT and FF corners in order to get required BGR output voltage. Coarse resistors are selected as,
Rcoarse0 = RMIN1 – RMIN0
(10)
RCOARSE1 = RMIN2 - RMIN1
(11)
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
and fine resistors are selected to adjust the resistors at different process corners and supply for
minute variations in order to get proper BGR output. From the figure RMIN0=RMIN,
Rcoarse0=R21, Rcoarse1=R22, R23 and R24 are fine resistors. These values are chosen by
NMOS switches in accordingly by their turn on and turn off which is driven by digital circuit.
Startup circuit
The devices M6,M7 and M8 forms a startup circuit, M7, M8 forms inverter, which is part of
startup circuit as shown in figure 1 [1]. Initially when there is no current in core circuit, the
top two PMOS M2 and M4 are turn on, which makes input to inverter is one and output is
zero. The zero input which turn on the PMOS M6 device and initiates the current in core circuit. Once the core BGR turns on then startup will turns off and carrying very less current(pA). The devices M6 in sub threshold region, M7 in triode and M8 in saturation region
always for the proper operation of startup [6]. Figure 4 shows startup behavior of BGR output
with supply variation. The time required for BGR to produce a stable output is 200ns [1]. The
simulation is carried out by performing transient analysis when supply voltage is given as
ramp signal varying between 0V to VDD within 10ns, 100ns
IREF generation circuit
Figure 3. IREF generator circuit
Figure 4. Startup Behavior of BGR output
The current reference of 1µA for folded cascode opamp is generated from BGR PMOS current mirror as shown in figure 3.The biasing for M15 device is selected from BGR PMOS
current mirror by properly adjusting aspect ratio of M15 and same current is mirrored to nmos
M16 and connected to IREF of opamp. Now opamp will not work because startup circuit was
not included, to avoid this problem an extra PMOS M17 is biased from startup circuit and
connected to IREF generation circuit. So that once startup will initiates the current in IREF circuit, opamp will work properly. The extra RC circuit is included in reference generator to
avoid an ac signal coming from opamp cascode structure. A ac signal is coming from opamp
output because the circuit is not symmetry at its both cascode branches, since total impedance
looking from source of nmos3 to Vdd and nmos4 to Vdd are different. To avoid this problem
two RC filters are introduced in reference generator so that it will block a ac signal and allows
dc reference current.
OPERATIONAL AMPLIFIER
The proposed circuit uses single stage folded cascode operational amplifier(opamp) with high
gain and PM as shown in figure 2.The pmos input pair folded cascode opamp is chosen in
order to meet the gain, stability, speed requirements. The biasing voltages for opamp cascode
stages are generated by using current mirrors as shown in left half of figure 2 [6]. The devices
M1 and M2 are input pair of opamp, the inputs to opamp are driven by BGR a and c nodes as
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
shown in figure 1.Load capacitance of opamp is taken from adding all capacitance associated
with M2 and M3 devices. The overall opamp which carries current of 7µA and operating all
devices in saturation [11]. The gain of folded cascode opamp is given by
𝐴𝑉 =
𝑔𝑚2 𝑔𝑚4 𝑔𝑚8 𝑅1
𝑔𝑑𝑠8 𝑔𝑑𝑠10 𝑔𝑚4 𝑅1 + 𝑔𝑑𝑠4 𝑔𝑚10
[14]
SIMULATION RESULTS
Simulations have been carried out using Mentor Graphics Pyxis tool with EldoSpice simulator in 130nm CMOS technology with supply of 1.8V with 10 % variations. The operational
amplifier used in the proposed BGR is single stage folded cascade opamp, has given gain of
77.6db and phase margin of 72 degree as shown in figure 5. Figure 6 shows Vref versus supply variation waveform by performing dc analysis. When the supply is varying between 0V to
1.98V, output is getting saturated at 1.45V supply.
Figure 5. Gain and Phase plot of opamp
.
Figure 7. Vref curve before trimming
Figure 6. Vref Vs supply variations in DC
Figure 8. Vref curve after trimming
Figure 7 shows Vref versus temperature at different process corners before trimming, which
gives variations of Vref at process corners is 43mV. Figure 8 shows Vref Vs Temp curve at
different process corners after trimming circuit is used. The overall variation of Vref at different process corners(TT, SS, FF) with supply variations( 1.62V ,1.8V, 1.98V) is 4.7mV and
TC of 39.9ppm/°C.
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Parameters
[2]
[3]
[4]
[5]
[6]
Proposed
Design
CMOS
0.8
0.8
0.35
0.18
0.18
0.13
Tech(µm)
Paper No.
000
Parameter
Theoretical Simlated
Av(db)
74.8
77.6
UGB(MHz)
15.48
16
-2.47
-2.76
VDD (V)
1
-
3.3
1.8
1.8
1.8
Pole1(KHz)
VREF(V)
0.54
1.2
1.18
0.62
0.5
1.81
Pole2(MHz) -57
-52
VREF
Variation
0.3
2.8
1
1.4
0.9
1.181mV
Pole3(MHz) -74.4
-78
V
mV
mV
mV
mV
Temp.
range(ºC)
0/
40/
10/
0/
-40
+80
125
90
70
/125
TC(ppm
/ºC)
7.5
14
10.5
32.5
9
19
35
100
43
PSRR (db)
-
110
-
0/100
Table 2. Comparison of perfor
mance parameters of opamp between theoretical and simulated
Table 1. Performance comparison
of bandgap reference circuits.
The performance metric of different architectures of bandgap reference are shown in Table1
[2] [4]. From the table it can be seen that the proposed circuit got a standard Vref output of
1.181V with bipolar structure which is good reference output as compared to other papers[5]
[6]. Table 2 shows the comparison table of Folded cascode opamp performance parameters
between theoretical and simulated values. Theoretical values are obtained by small signal
analysis of folded cascode opamp using Maxima tool.
CONCLUSION
A BiCMOS voltage mode bandgap reference is designed and simulated with good PSRR and
low temperature coefficient. The proposed circuit is simulated with supply of 1.8V with 10%
variations, which produced Vref output of standard 1.181V using bipolar version and TC of
19ppm/°C.A single stage folded cascode opamp generates gain of 78db, with very less input
offset of 1.96µV because of closed loop gain of opamp in BGR is 118db. The PSRR of overall design is - 43db its good value for given application. The proposed BGR output will be use
in LDO circuit, which is operating at 3.3V supply and gives regulated output of 1.8V.
REFERENCE
Abhisek Dey and Tarun Kanti Bhattacharyya, Design of a cmos bandgap reference with low temperature coefficient and high powersupply rejection performance,VLSICS,Vol2, No3, September 2011
.
Piero Malcovati, Franco Maloberti, Carlo Fiocchi, and Marcello Pruzzi, “Curvature- Compensated
BiCMOS Bandgap with 1-V Supply Voltage”, IEEE Journal of Solid-State Circuits, 2001.
P Siew kuok Hoon,Jun Chen,Franco Maloberti ,An improved bandgap reference with high power supply regection, The University of Texas,Inc,USA,2002.
Mitrea, O., Popa, C., Manolescu, A. M., and Glesner, M , A curvaturecorrected CMOS bandgap Reference ,Adv. Radio Sci., 1, 181-184, doi:10.5194/ars-1-181-2003.
Ro-Min Weng, et al, A 1.8-V High-Precision Compensated CMOS Bandgap Reference, IEEE Conference on Electron Devices and Solid- State Circuits, 2005, pp. 271 273.
Jun Hu, Yongsheng Yin,Honghui Deng, Design of a High-performance Brokaw Band-gap Reference
,Hefei University of Technology.