Download 1. Paragraph 1

T13/E00129R0
Response to Letter Ballot Comment
for ATA/ATAPI/5
Revision 0
From: Kent Pryor
Quantum Corporation
500 McCarthy Boulevard
Milpitas, CA 95035
Phone: 408-894-4510
Email: [email protected]
Date: June 19, 2000
Subj: Response to Letter Ballot Comment for ATA/ATAPI/5
Introduction:
One comment was received into the Register of Public Review Comments on NCITS 340:200x,
Information Technology - AT Attachment with Packet Interface - 5 (ATA/ATAPI-5). The public review
period was from April 21, 2000 to June 5, 2000. Committee T13 of NCITS submitted project draft
D1321R3 for this review. This document repeats each of the five comment paragraphs with the
committee's response.
T13/E00129R0
1. Paragraph 1
1.1. Comment
The 66 MHz is very close at the cable limits. The method of expressing the timing measures really
needs to be cleaned up better to cut down on the blame game between drive manufacturers and the
computer manufacturers. As it is there is too much range for interpretation and this big leafy document
can be almost looked as a useless spec as far as arbitrating where the design needs to go.
1.2. Response
We assume that "66MHz" refers to the 66 Megabytes per second transfer rate of Ultra DMA Mode 4,
which includes a maximum signaling frequency of 16.7 MHz on any conductor. The general criticism in
the first paragraph focus on signal and timing integrity. The parts of the document which directly affect
these attributes are Tables 4, 6, and 51, the supporting timing diagrams in figures 49-58 (about 12
pages of requirements) and the informative-only Annex D (42 pages of "where the design needs to go").
Perhaps the commenter is suggesting that the standard should be separated into several documents;
this idea should be considered for future ATA/ATAPI projects. Let's continue looking for specific
technical issues.
2. Paragraph 2
2.1. Comment
Have the committee members expressed in confidence any problems in arbitration which may have
resulted already in implantation with this (maybe you can ask - but keep my poor third part name out of it
please).
2.2. Response
This interface has no arbitration operations. We will take "problems in arbitration" to refer generally to
interface signaling errors, probably detected by CRC checking on each DMA burst. We assume that
"implantation" means "implementation". So yes, some prototype testing between hosts and devices
showed errors requiring electrical design improvements using the guidelines in Annex D as well as
meeting the formal specification requirements. Altogether, this process did result in a large body of
compatible hardware actually shipped and working. And we did learn enough to add additional formal
requirements in Quantum's Ultra DMA Mode 5 proposal for ATA/ATAPI-6 announced on June 5. These
include timing requirements at both the cable connectors and at the interface integrated circuit
packages.
3. Paragraph 3
3.1. Comment
The method of time is not always consistent - separating the time as skew (is this really clear where the
limit lies in each case) and the half rails measurement threshold is almost inconsistent with the way any
other interface is specified. I feel it holds more value to specify this as well at the crossing threshold, and
keep the slew rate an independent spec.
3.2. Response
The maximum slew rate specifications in Table 4 are intended to limit cross-talk. Appendix D section 2.2
explains why the resulting voltages do not affect the timing specs. The parenthetical question about
skew cannot be answered without knowing what "this" refers to and what limit is in question. Ultra DMA's
measurement level of 1.5 volts in Table 51 and separate slew rate spec in Table 6 already seems to
meet the commenter's desire in the last sentence of the third paragraph. The single measurement
threshold may be considered less tight than the four voltage levels of single-ended SCSI (SPI-2 rev 20b,
figure 44). But SCSI has to deal with a much more varied cable plant, and is allowed higher-cost circuits
Response to Letter Ballot Comment for ATA/ATAPI/5
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T13/E00120R1
and terminators. The new proposal includes additional specifications for thresholds and hysteresis when
used at a yet higher rate. Perhaps these will be the commenter's desired "crossing thresholds". But the
current ATA/ATAPI-5 specification methods are already very similar to SPI-2 single-ended signaling for
SCSI.
4. Paragraph 4
4.1. Comment
If you look with a scope, with present technologies these devices in practice are very close in margin
from spec. Ambiguities of method could really jeopardize its practical viability, but with the speed downs,
maybe none notices. But its a bad way to throw away speed and hardware.
4.2. Response
We recognize that some "ambiguities in [design] method" are addressed only informatively by providing
detailed explanations and guidance in Annex D. Every specification can be considered incomplete and a
moving target (did you see ATA-1?). But ATA/ATAPI-5 seems adequate in the electrical area, as the
"practical viability" has now been proven in the market, at very low cost. The technical meaning of the
remaining words of this comment paragraph are unclear.
5. Paragraph 5
5.1. Comment
Have fun and don’t lose too much sleep in big committee meetings. I can learn more in a week in the lab
about this than you guys may have over two years.
5.2. Response
The T13 committee meetings are not large, typically 25 people, and guest participation is often allowed.
We don't lose sleep in the meetings, we may even gain some. Most of these electrical and timing
specifications were worked out before the T13 meetings in much smaller discussions during Quantum's
simulation, design, and test efforts with our development partners. In the process of developing and
patenting this protocol, Quantum has spent far more than a week in the lab, plus much more in analog
simulation, extrapolating those lab observations to ensure compatibility across the worst-case
combinations of ambient temperature, supply voltage, semiconductor processes, and cable properties.
We encourage more detailed feedback and more constructive criticism than this comment provides. Our
June 5 proposal for Ultra DMA Mode 5 is such an invitation.
[end of E00129R0.DOC]
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Response to Letter Ballot Comment for ATA/ATAPI/5