Download Adaptive Voltage Regulation and Equal Current Distribution of

The 30th Annual Conference of the IEEE Industrial Electronics Society, November 2 - 6, 2004, Busan, Korea
Adaptive Voltage Regulation and Equal Current Distribution of
Parallel-Buck DC-DC Converters Using Backstepping
Sliding Mode Control
Shui-Chun Lin and Ching-Chih Tsai, Senior Member, IEEE,
Department of Electrical Engineering, National Chung Hsing University
250, Kuo-Kuang Road, Taichung 40227, Taiwan
[email protected]
Abstract－This paper develops a novel methodology
for voltage regulation and equal current distribution
of parallel-buck DC-DC converters. Such converters
are modeled as linear averaged state-space system
models with adjustable loads. Two measurements,
such as output voltage and inductor current, are used
to accomplish the design of an adaptive backstepping
sliding mode controller for the Parallel-buck DC-DC
converters. Based on the singular perturbation
method, a reduced order model is derived in order to
show that the effect of equivalent series resistance
(ESR) of the capacitor can be ignored and the parallel
converters can be well approximated by the reduced
order model. With the reduced order model, an
adaptive sliding mode control utilizing backstepping
approach is proposed to control the parallel-buck
DC-DC converters. This proposed control method has
been verified by computer simulations, and has also
been proven capable of giving satisfactory voltage
regulation performance under input voltage
variations and load changes.
Keywords: Adaptive control, backstepping, parallel
DC-DC converter, pulse width modulation (PWM),
voltage regulation, sliding mode control.
I.INTRODUCTION
aralleled DC-DC converters have been shown to have
several advantages over stand-alone converters with
identical capacities. The merits of parallel DC-DC
converters include increased power processing capability,
improved reliability, enhanced availability, long term
maintainability and etc. In particular, in applications to
higher power demands, the use of parallel DC-DC
converters is able to share the same load with significant
reduction of component stress and output voltage ripple.
Generally speaking, the parallel-buck DC-DC converters
are not identical and thus unbalanced currents are drawn
from their outputs. The facts are caused by many factors,
such as component tolerances, nonidentity conductors
from the converters to the current distribution, and others.
The equal current distributions among converters are
very important for the reliability of the system. Without a
proper current sharing control design, the converters may
become unstable and their life-times may be shortened or
the converters’ performance may be degraded.
Many control strategies have been used to achieve
equal current sharing for parallel operation of the
converters. Rajagopalan et al. [1] carried out a
master-slave method, and Kim et al. [2] performed a
droop method. The master-slave method is a kind of
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2004 IEEE
active control scheme. With the typical master-slave
method, it is necessary to intercommunicate between the
master and slave modules, and their interconnections are
complicated. The major deficiencies of the droop
approach are poor voltage regulation and poor current
sharing characteristics.
In order to accomplish the equal current distribution
and the regulated output voltage, many different
switching control design approaches have been proposed
for parallel operations of the converters [3-9]. All these
approaches have tried to reach this goal with a minimum
of technical complexity in order to keep the optimal
performance optimization. More recently, the
implementation of advanced control algorithm utilizing
standalone digital signal Processor (DSP) concepts in
switching power supply systems seem to be of growing
interest. DSP control offers several advantages for
control structures and the control redesign can be
changed by modifying only the software, thereby
providing possibility of the use of adaptive control and
even complicated control strategies. This paper is
concerned with the control problem of parallel DC-DC
converters with a DSP control chip. The backstepping
sliding mode control and adaptive control policies will
be used to develop high-performance regulation laws for
the parallel converters.
The singular perturbations design methodology has
been extensively used for a large class of nonlinear
systems that can be decomposed into slow dynamics and
fast dynamics. Those control theories and techniques
using singular perturbations method have been widely
explored in [14, 15, 18]. In this paper we are interested in
how the singular perturbations method can be applied to
show that the effect of equivalent series resistance (ESR)
of the capacitor C in a buck DC-DC converter can be
ignored, and to derive a order reduced slow model for
the circuit in order to develop an adaptive and efficient
control policy for achieving the required performance.
Adaptive backstepping is a systematic and recursive
design methodology for nonlinear feedback control. This
type of method has been well studied and documented in
[13, 16, 17]. This approach is based upon a systematic
procedure for the design of feedback control strategies
suited for nonlinear systems with exhibiting uncertainties,
and guarantees global regulation and tracking for the
nonlinear
systems
transformable
into
the
parametric–strict feedback forms. As the authors’ best
understanding, this design approach has not yet been
applied to regulate the parallel-buck DC-DC converters.
The objective of this paper is to develop reduced
slow state-space models of the converters using singular
perturbation method based on output voltage and
inductor current measurements, and to design adaptive
backstepping sliding-mode controllers for N paralleled
buck DC-DC converters with the required specifications.
To make the design feasible, computational simulation is
used to verify its performance, and the Lyapunov second
theorem is used to analyze the stability of the designed
control system.
The remainder of this paper is organized as follows.
Section II establishes the circuit’s reduction using
singular perturbation method. Section III is devoted to
deriving a reduced slow model of the circuit. In Section
IV, an adaptive backstepping sliding-mode approach is
adopted for synthesizing a controller to regulate the
converters’ output voltage. Computer simulations are
conducted in Sections V to show the effectiveness of the
proposed control method. Finally, the conclusions of the
paper are stated in Section VI.
II. SINGULAR PERTURBATION ANALYSIS
Consider PWM-based N paralleled buck converters
with adjustable loads. Fig.1 depicts a basic configuration
of N paralleled DC-DC buck converters, each of which
consists of a power MOSFET transistor as a switch, a
fast recovery diode and RLC components. Throughout
this paper, the parallel-buck converters are assumed to
operate in continuous conduction mode (CCM) [11]. To
simplify the notations, we define that iL i be the current
passing through the inductor Li , i C i be the current in the
capacitor ci , io
be the converter output current.
Moreover, v i denotes the DC input source voltage, v o is
the converter output voltage, ri is the equivalent series
resistance of inductor Li , rc is the equivalent series
i
resistance of the capacitor ci . In order to provide an
analytical model for predicting the responses of the
converter with respect to load changes, input voltage
variations and uncertainties caused from circuit elements,
we model the adjustable load current io as a fixed load
current iM and a variable current iN . Note that the current
iN remains constant except at the time instants to
change voltage setpoints. In Fig.1, the transistor operates
at a fixed frequency with a period T with a duty-ratio d .
The inductor current is assumed to be continuous, and
the inductance and capacitance components are lossless
and the output capacitor ripple voltage is considered to
be negligible. The relationship between steady-state
output voltage and duty-ratio is obtained from equating
the positive and negative inductor volt-seconds within a
switching cycle. In what follows study the two-time
scale properties of the standard model and give
approximate models based on the decomposition of the
models into slow and fast models. In doing so, we
consider N parallel-buck converters with a fixed load
current, iM and an adjustable current, i N , shown in
Fig.1. Notice that the resistance R in Fig.1 is fixed. The
application of linear circuit modeling method [10-13]
with aforementioned conditions leads to the
i L1
r1
Power MOS
vi
L1
iC 1
rc 1
Diode
C1
vc1
iL 2
r2
Power MOS
io
L2
rc 2
Diode
vi
C2
iC 2
iM
iN
vo
R
vc 2
iLn
rn
Power MOS
Ln
Diode
vi
rcn
Cn
iCn
vcn
Fig.1 A schematics of N parallel-buck DC-DC converters
following equations:
di
Li Li + rii Li = vi di − vo
dt
diCi
dv
d
iCi = Ci ( vo − iCi rCi ) = Ci o − Ci rCi
dt
dt
dt
Let ε i = Ci rC be a time constant. Since 0 < ε i << 1
(1)
(2)
i
then (2) becomes
εi
diCi
dt
+ iCi = Ci
dv o
,
dt
(3)
i = 1, 2, ...... n
By decomposing the model (3) into slow iCis (reduced)
and fast iCif (boundary) modes. i.e., iCi = iCif + iCis , we
obtain the fast mode satisfying
diC
ε i if + iCi f = 0
dt
and the slow state described by
dv
iCi = ic is = Ci o
dt
By a simple calculation, we obtain
iC i f = Ae
−
(4)
(5)
t
(6)
εi
which leads to that ic f → 0 as t > 5ε .Consequently,
for t > 5ε , it follows that
i
iCi = ici f (t ) + ic i s (t) ≅ ici s (t) = Ci
dvo
dt
(7)
(7) reveals that, after a very short transient time, the
effect of equivalent series resistance (ESR) of the
capacitor rC can be ignored; (2) can be well approximated
by the slow state (7).
III. REDUCED SLOW MODEL
The general circuit topology for parallel operation
of switching buck DC-DC converter is shown in Fig.1.
This total output current equal to the sum of the inductor
currents of each converter module could be expressed by
the following equation:
iL1 + iL2 + ... + iLi = iC1 + iC 2 + .... + iC i +
vo
+ iN (8)
R
and each inductor current satisfies the averaged model
Li
diLi
+ ri iLi = vi di − vo , where i = 1, 2,.....n
(9)
dt
With the overall reduced slow model (7), (8) can be
rewritten as
n
∑
i =1
n
iLi =
∑
Ci
i =1
=C
dvo vo
+ + iN
dt
R
n
dvo vo
+ + iN , C = ∑ Ci
dt
R
i =1
(10)
which leads to
dvo 1 n
v
i
= ∑ iL − o − N
C
dt
C i =1
RC
(11)
i
approaches zero as t tends to infinity. The asymptotical
stability property of ve can be shown by selecting a
Lyapunov function as below
t
1
1
V1 = Cve2 +
(16)
(k I ve (τ )dτ + iN ) 2
0
2
2k I
The time derivative of V1 along its trajectory
is V = −(k + 1/ R )v 2 . Since V is negative definite, we
∫
1
p
1
e
have ve → 0 as t → ∞ .
Remark 1
The parameters k p and k I can be designed such that (15)
has a desired characteristic function.
IV. ADAPTIVE BACKSTEPPING SLIDING MODE
CONTROL DESIGN
This section aims to develop an adaptive control
strategy for overcoming the problem with unknown
circuit parameters and load variations. In the sequel an
adaptive sliding mode controller with output voltage and
inductance current measurements will be proposed to
regulate the circuit’s output voltage and to have equal
current distribution for the parallel-buck DC-DC
converter. In doing so, we rewrite (9) for each converter
as
− β i iLi − γ i vo + di
, i = 1, 2,...n
(12)
iLi =
αi
where
αi =
Li
r
1
, β i = i , γ i = , and
vii
vii
vii
α i , βi , γ i ,
are assumed to be unknown parameters. The control goal
of the converter is to find a controller with adjustable
parameters and a set of parameter adaptation laws such
that the output voltage vo tracks the desired constant
reference voltage v ref . To achieve the goal, we define the
tracking
error
as ve = vo − vref
.
This
implies
that vo = ve + vref and vo = ve . Hence, (11) and (12) can
be rewritten as
1 n
1
ve = (∑ iLi − vo − iN )
(13)
C i =1
R
− β i iLi − γ i vo + di
(14)
iL i =
αi
The detailed design procedure of the proposed adaptive
backstepping sliding mode controller for the converter is
stated in the sequel.
Step1:
To facilitate the design of controller, let i Li be
considered as a virtual control variable such that the state
variable v e is asymptotically stable. Thus, by designing
t
1 vref
− k p ve − k I ∫ ve (τ )dτ ) , k I > 0, k P > 0
(
0
n R
we obtain the following dynamics of the error v e
iLi = φ (ve ) =
t
dve
v
(15)
= − e − k p ve − k I ∫ ve (τ )dτ − iN
0
dt
R
The subsequent method is used to show that ve
C
Step2:
This step aims at finding a controller suited for
adaptive strategy using backstepping and sliding mode
approach. The following sliding surface si = iLi − φ (ve )
is selected to attain the controller design. Differentiating
the sliding surface function yields
1
si = iLi − φ(ve ) = iLi − ( − k p ve − k I ve )
n
1
1
= iLi + k p ve + k I ve
n
n
− β i i Li − γ i vo + d i 1
1
(17)
=
+ k p ve + k I ve
n
n
αi
The switching control d i is designed in the following
form
1
1
di = γ i vo + βi iLi − α i ( k p ve + k I ve ) − k1i si − ve − k2i sgn (si ) (18)
n
n
such that
si =
−ve − k1i si − k2i sgn (si )
αi
(19)
, k1 ≥ 0, k2 > 0
Notice that the control (18) can be reduced to a type of
sliding mode control if the parameter k1i is zero. In order
to prove the asymptotical stability of the overall system,
we need to rewrite (15) as below
n
t
dv
v
(20)
C e = ∑ si − e − k p ve − k I ∫ ve (τ )dτ − iN
0
dt
R
i =1
and propose the following Lyapunov function candidate
V2 =
t
1 2
1
1 n
(k I ∫ ve (τ )dτ + iN ) 2 + ∑ α i si2 , α i > 0
Cve +
0
2
2k I
2 i =1
Taking the time derivative of V2 along its trajectory
n
t
gives V2 = veCve + ve ( k I ve (τ )dτ + iN ) + ∑ siα i si
∫
0
i =1
From (19) and (20), it follows that
n
n
n
i =1
i =1
i =1
2
V2 = −(k p + 1/ R)ve2 + ve ∑ si − ve ∑ si − ∑ (k1i si + k2i si )
n
= −(k p + 1/ R)ve2 − ∑ (k1i si + k2i si ) < 0
2
(21)
i =1
which implies that V2 is negative semidefinite. With
Barbalat’s lemma, we imply that ve → 0 and
si → 0 , i = 1, 2,..., n. as t → ∞ .
Step 3:
Find a set of parameters adaptation laws such
that s → 0 and v e → 0 as t → ∞ .We propose the
following adaptive control law
(22)
1
1
d i = γˆi vo + βˆi iLi − αˆ i ( k p ve + k I ve ) − k1i si − ve − k2 i sgn ( si )
n
n
si = iLi − [
vref
t
− k I ∫ ve (τ )dτ − k p ve ]
(23)
0
R
where αˆ i , βˆi , γˆi , are the estimates of the parameters
α i , β i , and γ i . Substituting the control (22) into (17),
one obtains
~
1
1
− β i iL i − γ~i vo + α~i ( k p ve + k I ve ) − ve − k1i si − k 2 i sgn ( si )
(24)
n
n
si =
Table1. 3parallel-buck converters parameters.
parameter
value
parameter
value
r1
r2
r3
L1
L2
0.19 Ω 0.2 Ω 0.21 Ω 1.1mH 1mH
R
C
kI
kp
k1i
10 Ω
10 µ F
100
0.001
0.5
L3
vi
0.9mH
20V
k2i
f
0.000001 20KHz
adaptive control (22), (23) with the set of parameter
adaptation laws (27),are globally uniformly bounded,
thereby
implying
that
all
the
variables,
ˆ
ˆ
ˆ
α i , β i , γ i , si , iLi , vo , ve , are globally uniformly bounded
for t ≥ 0. Furthermore, ve → 0, si → 0 as t →∞ .
αi
Next, we find a Lyapunov function and use it to derive
parameter adaptation laws
t
1
1
( k I ∫ v e (τ )d τ + i N ) 2 +
0
2kI
2
2
2
2
n
α
β
γ i
+∑( i + i +
)
2 λ 2i
2 λ 3i
i = 1 2 λ 1i
Va =
n
∑α s
i =1
2
i i
+
1
C v e2
(25)
2
where
λ1 > 0, λ2 > 0, λ3 > 0, α~i = α i − αˆ i , β~i = β i − βˆ i ,
γ~i = γ i − γˆi and α~ i = −αˆ i , β~i = − βˆi , γ~i = −γˆi .
Taking the time derivative of V a and using (24) yield
i
i
i
Va = −(1/R + k p )ve2 + ∑ [α i si si − (α~i /λ1i )αˆ i ]
n
i =1
~
− ∑ [( β i /λ2i ) βˆi + (γ~i i / λ3i )γˆi ]
n
t =1
and
~
2
ai si si = −βi iLi si − γ~i vo si + α~i (k p ve + k I ve )si − ve s − k1i si − k2i si
Thus, we obtain
n
αˆ
Va = −(k p + 1/ R)ve2 − ∑ [k1i si2 + k2i si + α i ((k p ve + k I ve )si − i )]
λ1i
i =1
n
βˆ
t =1
λ2
+ ∑ [ β i ( − iLi si −
i
) + γi ( − vo si −
i
γˆ
λ3
)]
(26)
i
Hence, we propose the following parameter adaptation
laws
αˆi = λ1i (k p ve + k I ve ) si
λ1i > 0
βˆi = −λ2i iLi si
λ2i > 0
γˆi = −λ3i vo si
(27)
λ3i > 0
Remark 2 The estimates αˆ i , βˆi and γˆi usually do not
converge to their true values, except that the reference
voltage meets the persistent excitation conditions,
V. COMPUTER SIMULATIONS
In what follows a Simulink program was developed
to verify the effectiveness of the proposed control
strategy. This simulation takes the parameters given in
Table 1. For the following simulation, the reference
output voltage was set at 5 Volts and the input voltage at
20 Volts. To simulate the input voltage variations and
load changes, the input DC voltage was increased by
50% at the time interval [1,2] and [6,7], shown in Figure
2, respectively, and the load was changed by 33% ( iN
from 3A to 4A) at the time interval [3,4], shown in
Figure 3, respectively. Figs. 4, 5 and 6 illustrate the
changes of the inductors of the three converters for the
input voltage changes and load variations. We observe in
Fig. 7 that the three converters have the same current
loading distribution, and the total inductance currents of
the circuit are equal to the sum of three individual
inductance currents. Figs. 8, 9 and 10 depict the control
duty ratios ( d1 , d 2 , d 3 ) for the converters in order to
maintain the output voltage equal to the desired setpoint
voltage. The output voltage responses of the DC-DC
buck converter demonstrate excellent regulation
performance even subject to sudden changes in input
voltage and load. From Fig.11, the results indicate that
small amount of voltage variations appear in the startup
phase and these exponentially converge to zero when the
load is abruptly changed.
n
such that V = −(k + 1/ R)v 2 − (k s 2 + k s ) ≤ 0 and Va
∑ 1i 2 i
a
p
e
i =1
is negative semidefinite. Again, Barbalat’s lemma
implies that all the signal s, ve si αˆ i , βˆi and γˆi , are
bounded and ve → 0 and si → 0 , for t → ∞ .
This completes the proof of which the system is globally
asymptotically stable. The following theorem
summarizes the result.
Theorem 1
Assume that the reference voltage v ref is constant, the
parameters k p , k I , k1i , and k2i , i = 1,2,..., n , are positive
gains. Then all the trajectories of the closed-loop error
system composed of the system (13) (14) and the
VI. EXPERIMENTAL AND DISCUSSION
An experimental setup was constructed in Fig.12 in
order to verify the proposed control method for the
PWM buck DC-DC converter. The TMS320C542 DSP
has been optimized for digital control system
applications and has all the architectural features
necessary for high-speed signal processing. The
TMS320F542 DSP architecture was also used to
implement the proposed control laws (22) and (23) with
the parameter adaptation laws (27) using standard C
programming techniques and related cross C compiler.
Fig.13 shows the transient response of the output voltage
Fig.2 waveform of the Input voltage
vi
was increased by 50% at the
time interval [1, 2] and [6, 7], respectively.
Fig.3 waveform of the adjustable current load iN was changed by
33% (from 3A to 4A) at time interval [3, 4].
Fig.4 Inductor current iL1 of the Parallel DC-DC buck converters in
Fig.7 Load (Total) current iL of the parallel DC-DC buck converters in
Fig.1
Fig.8 Duty ratio d1 of the parallel DC-DC buck converters in Fig.1
Fig.9 Duty ratio d 2 of the parallel DC-DC buck converters in Fig.1
Fig.1
Fig.5 Inductor current iL2 of the parallel DC-DC buck converters in
Fig.10 Duty ratio d3 of the parallel DC-DC buck converters
Fig.1
in Fig.1
Fig.6 Inductor current iL3 of the parallel DC-DC buck converters in
Fig.1
Fig.11 Output voltage response of the parallel DC-DC buck converters
in Fig.1
iL 1
r1
Power MOSFET
NSC91-2622-E-005-008-CC3.
io
L1
iC1
rc1
REFERENCES
Diode
vi
C1
vc1
iL 2
r2
io
L2
Power MOSFET
iM
iC2
rc2
R
Diode
vi
C2
Digital signal
processor
(DSP)
TMS320C542
vo
vc2
Current
transducers
(Hall element)
TLP250
PWM
iN
ADS7805
vo
iL 2
iL 1
Current
transducers
(Hall element)
Fig.12 Control architecture of the proposed control method for the
experimental parallel DC-DC buck converters
1 >
2 >
1) Ch 1:
2) Ch 2:
5 Volt 500 ns
2 Volt 500 ns
Fig.13 Waveform of the output voltage set at 4 volts and the input
voltage changed 5 volts.
of the two parallel-buck DC-DC converters under load
changes. The result in Fig. 13 indicates that the proposed
method is capable of giving robust voltage regulation
against load changes.
VII. CONCLUSIONS
This paper has proposed a novel adaptive
backstepping sliding mode control to achieve voltage
regulation and equal current distribution for parallel
-buck DC-DC converters under input DC voltage
variations and load changes. The controller design is
accomplished based on the circuit’s averaged reduced
order model in which the fast mode of the capacitor
current is ignored. The resulting controller without
adaptation behaves like an integral sliding mode
controller, and does not have any numerical difficulties
and stiffness caused by the fast mode of the capacitor
current. The adaptive capability of the controller has a
powerful strength to automatically tune its control
parameters for buck DC-DC converters with unknown
circuit parameters. Moreover, simulation and
experimental results have shown that the proposed
control method is proven capable of giving satisfactory
voltage regulation performance under input voltage
variations and load changes.
ACKNOWLEDGMENT
This study was supported by the National
Science Council of the Republic of China under Grant
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