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THE OAK RIDGE AUTOMATIC COMPUTER By J. C. Chu Argonne National Laboratory A total of seventy-seven individual orders is provided. In engineering design, there are two principles worth mentioning. As to circuitry and components, we believe that each type of circuit and circuit component has merits as well as shortcomings. Each such element should be used according to individual circumstances. For this reason one will find in the ORACLE DC as well as AC coupling circuits, synchronized as well as asynchronized circuits, logical as well as analog gating circuits, crystals as well as vacuum tubes, triodes as well as pentodes, and receiving as well as transmitting tubes. Both speed and reliability are essential. Features that make for reliability are rigorous logical design that minimizes the number of components required, allowance in every circuit design of ample tolerances on components, and strict adherence to the principle that, under no circumstances, is speed to be obtained at the expense of lowered standards of reliability. No internal checking of any kind is employed throughout. The three-dimensional chassis layout of the JOHNIAC is used in the arithmetic and control unit; plug-in subassemblies are used in the memory unit. Figure 1 summarizes the general characteristics of the ORACLE. It shows that the number of digits· assigned to order is nine and the number assigned to address is eleven. A complete command, therefore, is composed of twenty digits. A word is composed of forty digits,t so a word is made of two commands. Also, in Figure 1, it is shown that the memory system of the ORACLE can be operated in either of two modes, namely Mode 1024 or Mode 2048. This will be explained further in the latter part of this paper. It should also be noted that a total of five main voltages is used. Modified teletype equipment is used as the input and output unit with a read-in speed of 24 characters per second and punch-out speed of 15 characters per second. Multiple channel magnetic tape with a drive using accumulation of the tape in baskets is planned as the auxiliary memory unit. The remaining part of this paper contains a brief review of the logical design of the ORACLE and a few illustrative engineering circuits. Figure 2 is a diagram of the ORACLE's logical symbols. In the logical diagrams, no attempt is made to achieve precise conformity with the engineering diagrams. Signal polarity, type of gating circuit and drivers are not presented in the logical diagram. The signal on each line is either a "I" or a "0." It is a "1" when the line is activated. The active state is marked along the line. Figure 3 is the arithmetic and control logical diagram. The dotted lines are the information lines and the solid lines are the control lines. The A and Q registers have five tubes per stage. These are marked as "A" and "Q" on the diagram. Asymmetrical toggles are used. These have a maximum shifting speed of approximately 4 sec. per shift. There are five tubes per stage in the S-register. Symmetrical toggles are used here. The plusser or adder, which is indicated as "P" on the diagram, has eighty tubes per stage. It is of the logical adder type with special arrangements for speeding up the carry propagation. The time for carry propagation and collapse is about 4 /-Lseconds. The static programmer is, in effect, a partially decoded matrix table, It has about one hundred tubes. The set up speed is approximately 5 /-Lseconds. The dynamic programmer which generates the pulse routine to program the shift registers contains sixty tubes. The shift counter is a 6-stage binary scaler of the cathode trigger • It would be more appropriate to use the word "bit" instead of the word "digit", t See the paper of C. L. Perry on the logical design of the computer in this publication. THE ORACLE The ORACLE (Oak Ridge Automatic Computer Logical Engine) is a general purpose digital computer, designed and constructed at the Argonne National Laboratory for the Oak Ridge National Laboratory. Production of the major electronic units has been carried out by Technitrol Engineering Company of Philadelphia, Pennsylvania. The construction started in November, 1951. In logical design, it belongs to the parallel asynchronous type. The number system is binary with fixed binary point. The orders which can be executed by the machine can be classified as of the following types: Arithmetic Memory and arithmetic unit transfer Control transfer Memory and auxiliary memory transfer. Copyright © 1952, Association for Computing Machinery. Reprinted with permission from the Proceedings of the Association for Computing Machinery. Conference held in Toronto, Ontario, September 8-10, 1952. 57 From the collection of the Computer History Museum (www.computerhistory.org) 58 National Computer Conference, 1985 type. RC differentiating coupling networks between stages are used. The total carry propagation lasts about 0.1 to 0.2 IJ.seconds. The purpose of the dispatch counter is to dispatch the address specified by the order to the memory, keep account of the progress of the execution of the orders and keep track of memory regeneration. The dispatch counter is composed of the dispatch counter, control counter and regenerator counter which are marked as DC, CC and RC respectively, and consists of nine tubes per stage with a total of eleven stages. The eleventh stage is used only when the memory is operating in the 2048 mode. The half adders used here between stages are of logical and amplitude combination type. In a counter of this type, the set-up time is essentially the gating time. Because the counting rate is relatively slow, the idle time of the counter is used for carry propagation. The MOSC--memory order sequence control-is the interplay unit between the memory control and the arithmetic control. It serves to convey information between the two units. It has about eight tubes. As stated before, no typical circuits are set as standards in the ORACLE. The engineering design of some individual units may be of interest. To limit the length of this paper, only the shift register and its drivers and the general principle of the ORACLE memory system will be discussed. The shift register contains an upper and lower bank, each with forty toggles. The upper and lower toggles illustrated in Figure 4 are typical of the toggles in the register. The four vacuum tubes located between the toggles are the drivers and the 30K, 40K resistors constitute the gating circuits to transfer the information between the upper and lower banks. T", Tn T d , and TJ are, respectively, the transfer-up gates, transfer-right gate, transfer-down gate and transfer-left gate. There are two voltage levels that accompany each gating signal. The voltage level at which the gate is activated is indicated by an arrowhead. The transfer-in gating circuit is similar to the transfer-up circuit; it is not shown on this diagram. Clearing the toggles is done by lowering the plate voltage of the left-hand tube, thus lowering the grid of the right-hand tube to cause it to cut off, and the left-hand tube to become conducting. The transfer is done by raising the common cathode of the toggle to cause the left tube to cut off. When the cathode voltage is again lowered, the voltage of the right grid is higher than that of the left grid. The right tube now is then conducting and the left one is cut off. The wave form of the clear and transfer pulses is shown in the same diagram. The minimum clearing time is about 1 IJ.sec. and the transfer time is 1.2 IJ.sec. Clear and transfer start at the same time but transfer should outlast clear by at least 0.2 IJ.sec. The toggle has a safe margin of stability for variations of the components of twice that specified by the manufacturer and changes of tube characteristics of 50% resulting from aging. Figure 5 is a plot of plate current (Ip) vs. plate to cathode voltage (Ipk) with constant cathode current (Ik) as a parameter. The load line is plotted according to the equation Ip RL + e pk = Ebb and "0" is the operating point of the asymmetrical toggle. From the load line, it is seen that when the left-hand side tube of the toggle is conducting, it draws a plate current of about 4.8 milliamperes with a grid current of 2.7 milliamperes. The plate swing of this tube is from about 12 volts to about 85 volts. Since the plate swing is at a relatively low DC level, it is possible to use a low voltage bleeder ratio so that the grid of the right-hand side tube sees 88% of this plate swing. Figure 6 shows the clear and transfer driver circuits for the asymmetrical toggles. In order to minimize fluctuation of the drivers' voltage, self-regulating drivers are used. For both the clear and transfer drivers, only those voltage levels which are important for the reliability of the toggle are regulated. These drivers are designed to be consistent with the requirements for feedback stability. They have a rise and fall time approximately 0.2 IJ.sec. with 1% overshoot. The regulation for full load to no load is about 1%. In the transfer driver circuit, tube 5687 is the driver switching tube. When it is conducting, the regulating amplifier is cut off and the driver output is at -100 volts. If the switch tube 5687 is cut off, then the regulating tube 12AT7 is allowed to function. The top (-13.5) of the transfer pulse is, accordingly, regulated. One circuit of interest is the unit gain electronic voltage divider. It is composed of two 12AT7's in cascade. The lower tube, with a 24K resistor in its cathode, is a constant current tube because the plate current through this tube is entirely dictated by its cathode voltage and cathode resistor. Consequently, whatever voltage swing within the linear characteristics of the tubes occurs at the cathode of the top tube, it will be seen at the plate of the lower tube. The two 22K resistors in series give the required voltage levels shift. Figure 7 is the ORACLE memory. There are two operating modes available in the ORACLE memory system. In either case, dot-dash display is used. The dot is used to regenerate a zero, and dot-dash is used to regenerate a one. Mode 1 is the 1024-word mode in which time multiplex is used between a pair of Williams tubes to determine the stored information for each bit. In this arrangement, when either tube reads a "I" signal, a "I" is replenished to both. This method overcomes the most common type of screen blemish which would prevent storage of a "I" (dot-dash). Mode 2 is the 2048-word mode in which each tube stores 1024 bits. The first tube is regenerated in the first half of a major cycle and the second tube in the second half of the major cycle. As can be seen from the block diagram, no extra equipment is added to have Mode 1 available in the ORACLE memory system. It has been verified experimentally that when the ORACLE memory is in the 1024 mode, there is no noticeable effect on the repetitive consulting number (or read-around ratio). The 3JP1 tube is selected for the memory; it is expected to give a repetitive consulting number around 500. This number is obtainable because it is possible to use a higher accelerating potential to obtain a better focus; there being no trouble resulting from the common screen blemishes. Another feature of the ORACLE memory is the ABS· used to stabilize the beam current of the memory tube. Since the "I" signal (signal due to dot-dash configuration) depends on the beam current, a single address (zero location) is reserved for the storage of the "I" signal. The ABS clock can be set from approximately a single memory major cycle frequency to many cycles. It requires a maximum of three memory minor cycles to effect an ABS cycle. One minor cycle is required for synchronization, to complete the memory cycle which has already begun, and to prevent further order execution. When the MOSC and the Williams tube pulse routine generator are locked in this manner, the dispatch counter is automatically cleared to zero and no transfer from RG or DC is possible. Zero address is, therefore, most conveniently chosen for ABS storage. Since the "1" signal stored in the zero address location at the previous ABS cycle may be influenced by the interim storage display, a second memory cycle is used to write a fresh "I" signal at the zero address location and the third minor cycle is used to read the "I" signal. The feedback loop is completed through the amplifier to the ABS integrating circuit which controls the cathode bias of the memory tube. The effectiveness of the ABS system has been verified by experimentally changing the amplifier gain and the memory tube heater voltages while the memory is artificially programmed for continuous repetitive consulting. For ± 10% variation of heater voltage and reasonable variation of amplifier gain, there was no effect on the RC number when the ABS was on. Figures 8 and 9 show the physical construction of the basic memory plug-in unit. On top of the base unit are the amplifier and the discriminator.· A total of twenty-three vacuum tubes is used to store 2048 bits of information. * Automatic Beam-Current Stabilization. From the collection of the Computer History Museum (www.computerhistory.org) The Oak Ridge Automatic Computer A further discussion of the ORACLE memory system is presented in another paper entitled "The Selection of Tubes for the Wiiliams Memory" by J. C. Chu and R. J. Klein in this publication. The present status of the ORACLE is as follows: Its arithmetic and control unit have been constructed and passed the specified acceptance tests. A model of the memory has been constructed and tested thoroughly for effectiveness. The ORACLE is due for operation the early part of 1953. ACKNOWLEDGMENT The author wishes to acknowledge the encouragement given by Dr. Louis A. Turner, Director of Physics Division, Argonne National Laboratory, in carrying out this project and for his assistance in the preparation of this manuscript. J. C. Chu OAK RIDGE COMPUTER CHARACTERISTICS: MACHINE TypE ............................................. PARALLEL 40 REGISTER CAPACiTy ........................................ . ALLOWED ADDER CARRY TIME ............................ . 5 6 ALLOWED TIME PER SHIFT. ~ ........................... .. MULTI PLICATION TIME (eir = 0) ........................ .. 240 . MULTIPLICATION TIME (ear = 1-2 -39 ) .................. .. 440 DIVISION TIME ............................................ . 440 40 NUMBER OF DIGITS ASSIGNED TO NUMBER ............. . NUMBER OF DIGITS ASSIGNED TO ORDER........... ..... 9 NUMBER OF DIGITS ASSIGNED TO ADDRESS......... ..... fL·s. fL·s. Jl.s. fL··· Jl.s. MEMORY MINOR CYCLE OR MAXIMUM ACCESS TIME..... I I 20 MEMORY MAJOR CYCLE MODE 1024 ................................. . 20.48m.s. MODE 2048 .................................. 40.96 m.s. fL.s. NUMBER OF VACUUM TUBES ............................. 3000 Figure l-Characteristics of the Oak Ridge Computer o o A-G-C fa A-r-SC ~ .- o 0 A-?-C A~-C A--~~O 59 • A Ne~t1cn B LOGICAL SYMBOLS Figure 2-Logical symbols From the collection of the Computer History Museum (www.computerhistory.org) 60 National Computer Conference, 1985 L,.J ,..,. M 10 SU ~ ,MOSCI $ 'MOSCI SV ct=r : C I e , I -----., I I L_____ ~ I ~I l ADDItUS : ~ .. - - - - - - - . - - - - - - - I ~: MOSe I ~: Cli SHIn " (S 10) I eLult.gg'.- y~ ,. I I l :I~II : :l -: OU All I I a,: I .. : ~---~ I I I I I I 0 I I I ...t-------"1----- :: I O'.T ~~ ..o-J) I 1010., . I I I ----- A"III I I MOSC ; ! AL _a.f( I osc .. I I I ,.----~ IIIOK AU "'004Lr' a,-oP: '- ____ J I I ---I III AUX II AU... CW-"1----~ I-'T' ~I O-ISPI ~1 -o L!,.J I L ___ , I ' II I TO III 1_______________ n ! )" .-,1, A _: yr- _________ T _ _ _ _ _ _ _ _ _ I .-'-1- III to SL AUlCIU"VIl ,.- - : "ROM ADD TO DC (IilOSel " ARITHMETIC UNIT AND CONTROL I ~ ~ • I • I MOSe TO DEfLECTION NOMENCLATURE SU Sl AU AI QU QI P Mosc SP AG SR Storage register, upper bank Storage register, lower bank Arithmetic register, upper bank Arithmetic register, lower bank Quotient register, upper bank Quotient register, lower bank Plusser or adder Memory order sequence control Static programmer Arithmetic gate Shift recognition Multiplication or division order Memory Magnetic tape or teletype tape Address 1T M T ADD Figure 3---Arithmetic unit and control +110 I I I II -13 -100 -4 I +50~ I I' + 150 18K 36K :~ I FROM 2 ft • 11'-II I UPPER FROM 2"_1 UPPER 30K 40K T" :I~~+ -135 -tOO 135 T,t--100 Tdt=:~~ Cld 40K 40K 135 It+-100 T .150 18K +110 36K ~ 1 SHIFT REGISTER L 40K 240K -300 Figure 4-Shift register From the collection of the Computer History Museum (www.computerhistory.org) The Oak Ridge Automatic Computer Tube Type 6J6 14 13 Ebb 12 II 10 9 8 Ip 7 7 ipR L+ 'pk- Ebb 5 4 - 4 3 Figure 5-Load lines for the asymmetrical toggle ,-1.75 " -500 500 ll-- +"1"'1' I '.h, "i'jfr;, !ti:~~,~1 jt-"+-__L:::~4-----'---+----" c~ :I~~ + -c:-:i I ~oor-'J I I I I I 1. ~964 J3 39M -3~0 t - - PU~S[ I ( T I~ 3K - - ~687}',,-+---'=-~+r T r I~O I1175Kr ...r K - 300 FOR"[R _ _ :-6d7 I -300 . I I_ _ _ _ _ DRIV[RS - - - - - I CLEAR AND TRANSFER DRIVER Figure 6-Clear and transfer driver From the collection of the Computer History Museum (www.computerhistory.org) 61 62 National Computer Conference, 1985 To orlt .. mehc unU to,. COo<' DOl, 5, Jl'--__________fL R _ _ _ _ _ _ _ _ _ __ _~~ _________________ ~'t ~k__ _ _ _ _ _ __ _ _ 52 - - - - 1 1 - - __________ T, _~~~_ _ _ _ _ _ __ 0... r---sl~ _ _ _ _ ___ --------~~~----------------~~~---------------~~~----- PULSE ROUTINE TIMING 1 From dl.'Ch COUn'., WILLIAM'S MEMORY SYSTEM Figure 7-0RACLE memory system Figure 8--A complete plug-in unit From the collection of the Computer History Museum (www.computerhistory.org) The Oak Ridge Automatic Computer Figure 9-Plug-in subassemblies of the memory unit From the collection of the Computer History Museum (www.computerhistory.org) 63 From the collection of the Computer History Museum (www.computerhistory.org) ARTIFICIAL INTELLIGENCE EWING L. LUSK, Track Chair Argonne National Laboratory Argonne, Illinois From the collection of the Computer History Museum (www.computerhistory.org) From the collection of the Computer History Museum (www.computerhistory.org)