Download MAPS with pixel level sparsified readout

MAPS with pixel level sparsified readout: from
standard CMOS to vertical integration
L. Gaionia,c, A. Manazzaa, M. Manghisonib,c,
L. Rattia,c, V. Reb,c, G. Traversib,c
aUniversità
bUniversità
degli Studi di Pavia
degli Studi di Bergamo
cINFN
Pavia
Outline

Motivation

CMOS Monolithic Active Pixel Sensors (MAPS) for tracking in
future high energy physics experiments

Deep n-well (DNW) MAPS features

DNW MAPS in planar technology

DNW MAPS in 3D technology

o
Analog and digital front-end
o
Design consideration
o
Readout architecture
o
Detection efficiency
Conclusion
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Motivation
 Future experiments at next generation colliders like ILC and Super B-Factory
require fast, highly granular, low mass detectors
 CMOS MAPS features:
o
minimal readout electronics  small pitch, high spatial resolution
o
sensing element shares the same substrate with the readout electronics
o
substrate thickness can be reduced to a few tens of microns
o
fast readout may be a problem
 Because of the large amount of data produced in the readout of large
matrices, an innovative solution of MAPS, based on triple well structures, was
proposed  Deep N-well MAPS (DNW MAPS) allow designers to implement
more complex, fast readout circuits
o
capabilities for pixel level sparsification and time stamping
o
fully CMOS architecture
o
relatively small area for the digital front-end (FE)
o
detection efficiency maybe degraded
 Vertical integration may lead to the full compliance with the experiment
specifications  3D DNW MAPS
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
CMOS MAPS
 Have been proposed as suitable candidates for charged particle trackers at
the next generation colliders
 Several features make them appealing for such applications:
o
sensor and readout electronics share the same substrate  low material budget
o
low power consumption and fabrication costs

Minority carriers released along the
track move by thermal diffusion in the
undepleted epitaxial layer

N-well/P-epitaxial diode acts as
collecting element

Sensor capacitance (CD) used to
convert the collected charge to a
voltage signal  small electrode

Simple in-pixel readout architecture 
sequential readout

See next talk (C. HU-GUO) for state of
the art of CMOS MAPS: MIMOSA
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Deep N-well MAPS

Deep N-well provided
by triple-well CMOS
processes is used to
shield nMOSFETs from
substrate noise

This feature was
exploited in the
realization of a new
kind of CMOS pixels 
DNW MAPS devices
 The DNW acts as collecting element for the charge released in the substrate
 A readout chain for capacitive detectors is used for Q-V conversion  gain
decoupled from electrode capacitance
 NMOS transistor of the analog section hosted in the deep N-well
 Sensor can be extended to cover a large area of the pixel cell  PMOS device
can be included in the front-end design
 Fully CMOS design  high functional density
 Fill factor = DNW/total n-well area
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
DNW MAPS: analog front-end
 Shaperless version of an optimum readout chain for capacitive detectors
 The analog processor includes a charge sensitive amplifier and a threshold
discriminator  binary readout
 SDR0 prototype designed in a 130 nm technology (25 μm pitch)
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
SDR0, a DNW MAPS for the ILC vertex
 Digital front-end enables
single hit-storage and 5-bit
time stamping, and includes
sparsification blocks (token
passing scheme)
the ILC beam structure:
o
Detection phase –
corresponding to bunch train
period
o
Readout phase –
corresponding to intertrain
period
•Token passing core
•Discriminator
•Hit-latch
DNW sensor
Time stamp
•Nand gate
register
•Bus control FF
25 mm
 Sensor operation is based on
Sparsification
logic
•Preamplifier
25 mm
0.95 ms
x2820
bunch train interval
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
0.2 s
337 ns
Digital readout
intertrain interval
L. Gaioni, “3D DNW MAPS ”
SDR0: features and experimental results
o
W/L input device: 22/0.25
o
Power consumption: 5 μW
o
Equivalent noise charge: 50 e- @ CD = 100 fF
o
Threshold dispersion: 50 e- (main contributions from
preamplifier input device and NMOS and PMOS pair in
the discriminator)
o
Charge sensitivity: 650 mV/fC
o
Power Down option for power saving
Matrix response to infrared laser
Digital readout is working fine
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
DNW MAPS: the APSEL series
 ASPEL series: first generation DNW
MAPS with on-pixel data
sparsification and time stamping,
continuous readout, tested in a
beam for the first time in September
2008
o
o
o
resolution < 18 mm (50 mm x 50 mm
pixels)
efficiency plateau close to 90%
sensors, readout chips, DAQ systems
and AM boards are working fine
 Two major flaws affect the overall performance of the DNW MAPS:
o
detection efficiency may be inadequate: fully CMOS electronics requires a
non negligible amount of n-well area for the integration of PMOS devices
o
single-hit detection
 Extensive R&D on 2D DNW MAPS ongoing (layout optimization)
 3D integration processes, the technology leap
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
3D Integrated Circuit
 In wafer-level, 3D processes, multiple layers of planar devices are stacked
and interconnected using through silicon vias (TSV)
 Key technologies needed for 3D:
WB/BB pad
alignment and Mechanical/electrical bonding
between layers
o
wafer thinning (below 50 mm)
o
Realization of electrically isolated connections
through the silicon substrate (TSV formation)
TSV
 Advantages
o
Reduced chip size
o
Reduced parasitics
o
Reduced power
o
Fabrication process optimized by tier function
1st wafer
Inter-tier
bond pads
 Tezzaron Semiconductor technology can be used
to vertically integrate two layers specifically
processed by Chartered Semiconductor (130 nm
CMOS, 1 poly, 6 metal layers, 2 top metals, dual
gate, N- and PMOS available with different Vth)
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
2nd wafer
o
L. Gaioni, “3D DNW MAPS ”
Tezzaron/Chartered run
 In the last few months several Italian teams (from INFN Bologna,
Pavia, Perugia, Pisa and Roma III and Universities of Bergamo, Pavia,
Perugia and Pisa), together with Fermilab and a number of French
(In2P3), Polish and German groups, have been working within the
3DIC Consortium on a MPW run in the Tezzaron/Chartered 3D IC
fabrication process
 The 3D IC Consortium:
o
includes FNAL and several Italian and French Institutions (also Bonn and
AGH Universities, see http://3dic.fnal.gov) aiming to work together on a
MPW run using the Tezzaron 3D IC fabrication process
o
the collaborating institutions are willing to share information on design
tools and design rule implementation, cell libraries, circuit blocks (besides
costs)
o
as far as the Italian contribution is concerned, this first submission, funded
in the frame of the P-ILC experiment, will include MAPS sensors mainly for
applications to the ILC, but also some APSEL structures
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
DNW MAPS: from 2D to 3D
 Tier 1 includes collecting electrode (deep N-well/P-substrate junction), analog
front-end and discriminator
 Tier 2 includes digital front-end (2 latches for hit storage, pixel-level digital
blocks for sparsification, 2 time stamp registers, kill mask) and digital back-end
(X and Y registers, time stamp line drivers, serializer)
 Separation of analog and digital sections  lower cross-talk
 A 3D DNW MAPS for the ILC vtx  the SDR1 chip
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
SDR1: analog front-end and discriminator
 Limited use of PMOS devices in the sensor layer
shaperless FE (SFE)
discriminator
AVDD
DVDD
Inter-tier
bond pads
Ifbk
Vt
DGND
CF
AGND
TIER 1 (BOTTOM)
TIER 2 (TOP)
 Preamplifier PMOS devices are kept in the analog layer (TIER 1), whereas
large area PMOS from discriminator are integrated in the digital layer (TIER 2)
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Analog FE: features and simulation results
o
W/L input device: 20/0.18
o
Power consumption: 5 μW
o
Equivalent noise charge: 35 e- @ CD = 200 fF
o
Threshold dispersion: 36 e- (main contributions from preamplifier input
device and NMOS and PMOS pair in the discriminator)
o
Charge sensitivity: 800 mV/fC
o
Power Down option for power saving
IFB = 1 nA
350
IFB = 1.4 nA
I
75
FB
300
= 1.8 nA
IFB = 2.2 nA
SFE peak amplitude [mV]
Preamplifier output [mV]
100
IFB = 2.6 nA
50
Injected charge
800 e25
250
200
150
100
INL=2%
50
0
0
0
4
8
12
Time [ms]
16
20
0
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
400
800
1200 1600 2000 2400 2800
Input charge [electrons]
L. Gaioni, “3D DNW MAPS ”
Geometrical features of the DNW electrode
 Placing most of the PMOS on the digital layer may reduce the area covered
by competitive electrodes  better efficiency
 The DNW covers about 35% of the cell area in the SDR0 chip, more than 50%
in its 3D release
25 mm
20 mm
DNW (collecting
electrode)
NW
SDR1 cell
(bottom tier)
SDR0 cell
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Sensor detection efficiency and cluster size
 Monte Carlo simulations on matrices of 3x3 DNW MAPS featuring the layout of
the SDR0 and SDR1 sensors (10000 experiments, 80 μm thick substrate)
10
SDR0
100
Average cluster size
Sensor detection efficiency [%]
8
80
60
40
SDR1
6
4
2
SDR0
SDR1
20
0
0
200
400
600
800
0
-
Discriminator threshold [e]
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
200
400
600
800
-
Discriminator threshold [e]
L. Gaioni, “3D DNW MAPS ”
Digital front-end
 Increased functional density with respect to SDR0 chip
 Each pixel is able to keep information about two hits with the relevant 5-bit
time stamps
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Digital front-end
 During the bunch train period, the SR FF (FFSRK) is set when the pixel is hit the
first time and the relevant time stamp register gets frozen
 Upon a second hit, the D FF (FFDR) is set and the relevant time stamp register
gets frozen
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Token passing readout architecture
Suggested by FNAL IC design group,
first implemented in the VIP chip
ReadOutCLK
MUX
8
FirstTokenIn
8
tki
DataOut
5
X=1
TSBUF
X=2
TSBUF
X=256
TSBUF
gX=GetX
gX
tki gX
TS
tko gY TS
tko gY
tki
gX
tki gX
TS
tko gY TS
tko gY
tki
gX
tki gX
TS
tko gY TS
tko gY
Y=1
gY=GetY
TS=TStampOut
tki=TokenIn
tko=TokenOut
tki
gX
tki gX
TS
tko gY TS
tko gY
tki
gX
tki gX
TS
tko gY TS
tko gY
tki
gX
tki gX
TS
tko gY TS
tko gY
Y=2
tki
gX
tki gX
TS
tko gY TS
tko gY
tki
gX
tki gX
TS
tko gY TS
tko gY
tki
gX
tki gX
TS
Time
stamp
counter
tko gY TS
tko gY
Y=240
LastTokenOut
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Cell layout
Inter-tier
connections
Inter-tier
connections
DNW sensor
Analog section and
discriminator NMOS
N-well
Digital section and
discriminator PMOS
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Conclusion
 Vertical integration processes are very promising for the fabrication
of MAPS for the next generation colliders
 3D DNW MAPS have the following advantages compared with the 2D
devices:
o
better collection efficiency due to the reduced area covered by
competitive n-wells in the analog tier
o
reduction of cross-talk between analog/sensor and digital blocks
o
improved functional density
 Experimental characterization of the fisrt 3D prototypes is foreseen in
November
 Next step: 3D front-end chip vertically integrated to a high resistivity
fully-depleted sensor
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Backup
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
DNW MAPS and vertical integration
 Vertical integration between two layers of 130nm CMOS chips

The first layer may include a DNW MAPS device with analog readout, with digital
readout circuits in the second layer
 Overcome limitations typically associated with “conventional” and DNW
CMOS MAPS:
o
Reduced pixel pitch
o
100 % fill factor (few or no PMOS in the sensor layer)
o
Better S/N vs power dissipation performance (smaller sensor capacitance)
o
Reduction of digital-to-analog interferences
o
Increased pixel functionalities (removal of layout constraints allow for an improved
readout architecture, analog information,….)
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”
Digital FE detection efficiency
 Detection efficieny turns
out to be increased
thanks to the increased
functional density in the
digital FE
102
single-hit detection (SDR0)
double-hit detection (SDR1)
taking into account the
average cluster size
(1.13 for SDR0, 2.35 for
SDR1) at a discriminator
threshold of 300 e-
 Detection efficiency in
the SDR1 DFE is larger
than 99% for a hit
occupancy of
0.15/particles/BCO/mm
2
Digital FE detection efficiency [%]
 Curves obtained by
Qt=300 e
-
100
98
96
94
0
0.03
0.06
0.09
0.12
0.15
0.18
2
Occupancy [particle/BCO/mm]
VERTEX 2009 (18th workshop), 13-18 September 2009, VELUWE, the Netherlands
L. Gaioni, “3D DNW MAPS ”