Download Sense amplifiers are used to translate this small voltage signal to a

Class- 5 & 6
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Overall memory chip organization
Static memory circuits using the six-transistor
cell
Dynamic memory circuits
Sense amplifier circuits used to read data from
memory cells
Learn about row and address decoders
Read Only Memory (ROM)
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Random Access Memory (RAM) refers to memory in
a digital system that has both read and write
capabilities
Static RAM (SRAM) is able to store its information
as long as power is applied, and it does not lose
the data during a read cycle
Dynamic RAM (DRAM) uses a capacitor to
temporarily store data which must be refreshed
periodically to prevent information loss, and the
data is lost in most DRAMs during the read cycle
SRAM takes approximately four times the silicon
area of DRAM
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Note that the basic building block for this
memory is a 128Kb cell
The figure shows the
block structure of a
256-Mb memory
There are sets of
column and row
decoders that are used
for memory array
selection
The column decoder
splits the memory into
upper and lower halves
The row decoder and
wordline drivers bisect
each 32-Mb subarray
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The memory block
diagram contains
2M+N storage
locations
When a bit has been
selected, the set of
sense amplifiers are
used to read/write to
the memory location
Horizontal rows are
referred to as
wordlines, whereas
the vertical lines are
called bitlines
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Inverters configured as shown in the above
figure form the basic static storage
building block
These cross-coupled inverters are often
referred to as a latch
The circuit uses positive feedback
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With the addition of two control transistors it
is possible to create the 6-T cell which stores
both the true and complemented values of
the data
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Initial state of the 6-T cell storing
a “0” with the bitlines’ initial
conditions assumed to VDD/2
Conditions after the WL
transistors have been
turned on
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Final read state condition of
the 6-T cell
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Waveforms of the 6-T cell read
operation: Wordline capacitive
coupling effect
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Reading a 6-T cell that is storing a “1”
follows the same concept as before, except
that the sources and drains of the WL
transistors are switched
Note that the delay is approximately 20ns
for this particular cell
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It can be seen that not much happens while writing a “0”
into a cell that already stores a “0”
Microelectronic Circuit Design, 4E
McGraw-Hill
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While writing a “0” to a cell that is storing a “1”, the
bitlines must be able to overpower the output drive of
the latch inverters to force it to store the new condition
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The 1-T cell uses a capacitor for its storage element (data
is represented as either a presence or absence of a charge)
Due to leakage currents of MA, the data will eventually be
corrupted, hence it needs to be refreshed
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Storing a “0”
Storing a “1”
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Since the 6-T SRAM provides a large signal current
drive to the sense amplifier, it generally has shorter
access time as compared to a DRAM
The 4-T DRAM cell is an alternative that increases
access time, and automatically refreshes itself
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Sense amplifiers are used to detect the small
currents that flow through the access
transistors or the small voltage differences
that occur during charge sharing
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Sense amplifiers are one of the most critical
circuits in the periphery of CMOS memories
Their performance strongly affects both
memory access time, and overall memory
power dissipation.
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As with other ICs today, CMOS memories are
required
to increase speed, improve capacity and
maintain low power dissipation.
These objectives are somewhat conflicting
when it comes to memory sense-amp design.
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With increased memory capacity usually
comes increased bit-line parasitic
capacitance.
This increased bit-line capacitance in turn
slows down voltage sensing and makes bitline voltage swings energy expensive
resulting in slower more energy hungry
memories
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Due to their great importance in memory
performance sense amplifiers have became a
very large class of circuits
Their main function is to sense or detect
stored data from a read selected memory cell.
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The memory cell being read produces a
current "IDATA" that
removes some of the charge(dQ) stored on
the pre-charged bitlines.
Since the bit-lines are very long, and are
shared by
other similar cells, the parasitic resistance
"RBL" and
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capacitance "CBL" are large. Thus, the
resulting bit-line voltage swing (dVBL) caused
by the removal of "dQ" from the bitline is very
small dVBL=dQ/CBL
Sense amplifiers are used to translate this
small voltage signal to a full logic signal that
can be further used by digital logic.
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The need for increased memory capacity,
higher speed, and
lower power consumption has defined a new
operating environment for future sense
amplifiers
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Decreasing memory-cell area to integrate
more memory on a
single chip reduces the current IDATA that is
driving the now heavily loaded bit-line. This
coupled with increased CBL causes an even
smaller voltage swing on the bit-line.
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Decreased supply voltage results in smaller
noise margins
which in turn affect sense amplifier reliability
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fundamental approaches towards building
edge-triggered registers: the master-slave
concept and
the glitch technique
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technique that uses a
sense amplifier structure to
implement an edge-triggered
register
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 Voltage
Sense Amplifiers
 Current-Sensing
amplifiers
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SRAM sense amplifiers based on voltage
sensing are
widely used and established. However, this
principle
becomes slow for low supply voltages and
large
memories, since the cell current
discharges the bit lines until a
considerable voltage swing is reached
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. Current sensing that uses the cell current
directly as a signal keeps the bit line
voltages nearly constant and
results in fast read operation. This
requires a sense amplifier with low input
resistance for good impedance matching.
The most simple circuit to provide a low
input resistance is the common gate stage
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structure for current sensing has been
mentioned.
The new concept uses the common gate
transistor also as a multiplexer. For this
reason the gate voltage is controlled by the
select signal SEL of the
bit line multiplexer (MUX).
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A main advantage of current sensing
principles
compared to voltage sensing is their superior
behavior
for low voltage operation where the driving
cell current
becomes very small.
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Replacement a current-sensing amplifier has
been introduced, and its ability to overcome
problems associated with voltage sensing
may further examined.
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MPC is the
precharge
transistor whose
main purpose is to
force the latch to
operate at the
unstable point
previously
mentioned
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The same sense
amplifier used in
the 6-T cell can
be used for the
1-T cell in
manner shown in
the figure
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Obviously it is desired to have a fast access
in many DRAM applications.
By driving the wordline to a higher voltage
(referred to as a boosted wordline), say 5V
instead of 3V, it is possible to increase the
amount of current supplied to the storage
capacitors
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The sense amplifier can definitely be a major source of power
dissipation, but by using a clocking scheme, it is possible to
reduce the power dissipated, Dummy Cell (DC), Precharge
(PC), Latch clock (LC)
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The following figures are examples of commonly
used decoders for row and column address decoding
NMOS NOR Decoder
NMOS NAND Decoder
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Complete 3-bit NAND
decoder
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ROM is often needed in digital systems such
as:
◦ Holding the instruction set for a microprocessor
◦ Firmware
◦ Calculator plug-in modules
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The basic structure of
the NMOS static ROM is
shown in the figure
The existence of an
NMOS transistor means
a “0” is stored at that
address otherwise a “1”
is stored
Power dissipation is
large
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The domino
CMOS ROM is
one technique
used to lower
the amount of
power
dissipation
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Another ROM
option is the
NAND array
ROM which
can be
directly used
with a NAND
decoder
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The main problem with these previous ROMs is
that they must be designed at the mask level,
meaning that it is not a versatile product.
To solve this problem, the programmable ROM
(PROM) was introduced
The standard PROM cannot be erased, so the
erasable ROM (EPROM), and later, electrically
erasable ROM (EEPROM) were introduced
High density flash memories allow for electrical
erasure and reprogramming of memory cells
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The reset-set (RS) flip-flop can be easily
realized by using either two cross-coupled NOR
or NAND gates
The RSFF has the following truth tables
NOR RSFF
NAND RSFF
R
S
Q
Q
R
S Q
Q
0
0
Q
Q
0
0
Q
Q
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
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Simplified RS flip-flop
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A very important circuit of digital systems is the
D-Latch which is used for a D Flip-Flop
Whenever clock C goes high in the D-Latch, the
data on D is passed through to Q
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By using series
D-Latches that
latch the data
on opposite
clock phases, a
master-slave D
flip-flop can be
realized
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The End