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Beyond CMOS computing 2. Overview of Beyond CMOS Devices Dmitri Nikonov Thanks to Ian Young [email protected] 1 Nikonov 2. Beyond CMOS Outline General principles of logic devices Nomenclature of beyond CMOS devices How to achieve lower switching energy? 2 Nikonov 2. Beyond CMOS Why Are We Looking Beyond CMOS Computation Efficiency needs max. performance at lowest supply (Vdd) Switching Energy a CVdd2 At Vdd ≤ Vth , performance suffers significantly Lowest Vth is limited by leakage Computation efficiency of CMOS limited by 60 mV/dec Id/Vgs sub-threshold Slope CMOS Circuit Delay (ps) • • • • 300 For ITRS LG=20nm At 1nW Standby Power 250 200 150 100 50 0 0.0 0.3 0.6 0.9 Supply Voltage (V) 3 Nikonov 2. Beyond CMOS Nanoelectronic Research Initiative 2007-present, few $M, 5 semiconductor co., federal and state governments Notre Dame Penn State Purdue UT-Dallas SUNY-Albany Purdue MIT Harvard GIT NCSU Columbia U. Virginia (co-funds all centers) UC Los Angeles UC Berkeley UC Irvine UC Riverside UC Santa Barbara Portland State U. Nebraska-Lincoln U. Wisconsin-Madison 4 UT-Austin Rice UT-Dallas Texas A&M U. Maryland NCSU Nikonov 2. Beyond CMOS Brown Columbia Illinois-UC MIT/U.Virginia Nebraska-Lincoln Northwestern Penn State Princeton / UT-Austin Purdue Stanford U. Alabama UC Berkeley Virginia Nanoelectronics Center (ViNC) University of Virginia Old Dominion University College of William & Mary Computational Variables Class Variables Example Charge Q, I, V CMOS, TFET Electric Dipole P (FeFET) Magnetic Dipole M, Ispin ASL, SWD, NML Orbital State Bose condensate BisFET e- Charge 5 E-Dipole Magnetic -Dipole Nikonov 2. Beyond CMOS Orbital State Computational Variables and Transduction Output of a device needs to be the same computational variable (and same range) as input. Otherwise a transducer is needed. A. Transistor-like devices: (CMOS HP, CMOS LP, III-V FET, HJFET, gnrFET, spinFET) also GpnJ, BisFET B. STT/DW, STOlogic, STTriad Current-driven = Spin Torque Switching C. SMG, SWD, NML Voltage-driven = Magneto-Electric Switching also ASLD (current driven) 6 Nikonov 2. Beyond CMOS Requirements to Logic Non-linear characteristics (related to noise margin and the signal-to-noise ratio) Power amplification (gain>1) Concatenation (output of one device can drive another) Feedback prevention (output does not affect input) Tenets of Logic Complete set of Boolean operators (NOT, AND, OR, or equivalent) Physical measures Size (i.e. scalability) Switching time Switching energy (i.e. power dissipation) Room temperature or higher operation Low sensitivity to parameters (e.g. fabrication variations) Operational reliability CMOS architectural compatibility (interface, connection scheme) Techno logical require ments CMOS process compatibility (fabricated on the same wafer) Comprehending intrinsic and extrinsic parasitic and their interface to interconnect 7 Nikonov 2. Beyond CMOS Beyond CMOS Devices 1. Electronic 2. Spintronic Tunneling FET spin-torque e SpinFET spin-current All Spin Logic e Spin Torque Oscillator Graphene pn Junction Domain Wall Logic Spintronic Majority BisFET Spin Torque Triad 3. Orbitronic 8 Nano Magnet Logic Spin Wave Device Nikonov 2. Beyond CMOS Devices Off the Table Electronic Spintronic SET/binary decision diagram RAMA Resonant Injection Enhanced FET conductor contacts Domain wall ring Hbi as substrate current Electron structure modulation FET Phononic Excitonic FET Orbitronic 9 MTJ+STT Nikonov 2. Beyond CMOS Graphene thermal transistor Design Rules and Layout Estimation Scalable CMOS design rules in terms of l = maximum mask misalignment Rules and this layout remain the same between generations Contacted gate pitch = 8 l Also contacted gate pitch = 4F Minimum pitch of electrodes, 4F, determine the devices density (not the size of intrinsic devices) 10 Nikonov 2. Beyond CMOS CMOS FET (+) The incumbent logic device. (-) Higher active power than other devices. 11 Nikonov 2. Beyond CMOS Tunneling FET HomJTFET HetJTFET gnrTFET (+) Higher subthreshold slope => smaller supply voltage. (-) Smaller on-current than MOSFET. 12 Nikonov 2. Beyond CMOS Spin FET Magnetic source and drain Spin polarized carriers might not have vacant states Parallel magnetizations = smaller R Anti-parallel = larger R (+) Switch magnetization for better off-current, reconfigurability. (-) For benchmarked circuits, the spin functionality not used. 13 Nikonov 2. Beyond CMOS Bipolar pseudoSpintronic = BiSFET Electrons and holes Excitons Exciton condensate Collective tunneling through an oxide must be much stronger Charge imbalance destroys it (+) Claims of low voltage operation. (-) No room temperature Bose Einstein condensate observed. 14 Nikonov 2. Beyond CMOS Graphene p-n Junction Graphene electrostatically doped by p or n carriers Electrons reflect in interface dep. On angle Routs electrons by total internal reflection Mux configuration (+) Promises to switch with small voltage. (-) Practical implementation of reflection struggles. 15 Nikonov 2. Beyond CMOS All Spin Logic spin-torque spin-current e e Spin polarized electrons injected from nanomagnets Spin polarized current by diffusion It switches nanomagnets by spin torque (+) Good unidirectionality predicted. (-) Problem of spin relaxation = short interconnect. 16 Nikonov 2. Beyond CMOS Domain Wall Logic Currents summed and injected through side electrodes Domain wall moves and changes magnetoresistance under central electrode (+) Good scheme for cascading. (-) Magnetoresistance small for current switching. 17 Nikonov 2. Beyond CMOS Spin Majority Gate Similar to spin torque memory Currents through nanopillars aim to switch magnetization in the bottom (“free”) layer Majority wins! (+) Higher subthreshold slope => smaller supply voltage. (-) Smaller on-current than MOSFET. 18 Nikonov 2. Beyond CMOS Spin Torque Triad Spin torques in A and B switch magnetization in “Out” Change magnetoresistance (+) Binary elements, more familiar design. (-) Many elements in a circuit. 19 Nikonov 2. Beyond CMOS Spin Torque Oscillators Spin torque causes magnetization to precess in a periodic orbit. Several oscillators synchronize determine the frequency of the output (+) Frequency modulation robust. (-) Harder to read off oscillating signal. 20 Nikonov 2. Beyond CMOS Spin Wave Devices Ac current causes input magnetization oscillate Magnetization oscillation propagates as a spin wave Pulses of spin waves switch output magnets (+) Uses amplitude and phase, ingenious design of circuits. (-) Need precise phasing of signals. 21 Nikonov 2. Beyond CMOS Nano-Magnet Logic Magnetic fields set nanomagnets in an unstable state Dipole interactions between them flip magnetization Magnetization read off by magnetoresistance (+) Relatively fast switching from unstable state. (-) Dipole interactions between magnets sensitive to shape. 22 Nikonov 2. Beyond CMOS Barriers, Collectives, Thermodynamics source gate drain Energy +V e- -V e- Generic Electronic Switch /2 0 θ Generic Spintronic Switch Barrier 20 kT (from Ion/Ioff) 60 kT (non-volatile) Voltage 0.5 – 1 V 10-100 mV Particles Ne = 200 electrons Ns = 10000 spins Switching Energy Limit 4000kT = Ne*20kT 60 kT Phenomenon Non collective Collective E eVN ~ 4000 kT (1) Leakage determined by barrier I on I off 23 eV exp( ) kT (3) 1 E 0 B N s H k ~ 60 kT 2 (2) Leakage not related to barrier Nikonov 2. Beyond CMOS Power Delivery • Limited by Cu conductivity. • I/device=0.1mA • 1000 devices on network. • Size 6um*6um • Drop 2mV in device itself. [Vias not shown] • Contribution of wires NOT negligible • Estimated voltage power and ground networks: Minimum 10mV supply needed. 24 Nikonov 2. Beyond CMOS Beyond CMOS Devices 1. Electronic 2. Spintronic Tunneling FET spin-torque e SpinFET spin-current All Spin Logic e Spin Torque Oscillator Graphene pn Junction Domain Wall Logic Spintronic Majority BisFET Spin Torque Triad 3. Orbitronic 25 Nano Magnet Logic Spin Wave Device Nikonov 2. Beyond CMOS Summary Beyond CMOS devices are based on various computational variables. Need to perform transduction. 13 beyond CMOS devices covered in this study. More proposals appearing. Spintronics not relying on lower in the energy barrier, can be operated at ~10mV. All references and details at in D. E. Nikonov and I. A. Young, Proceedings of IEEE, 2013. 26 Nikonov 2. Beyond CMOS