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Gate Array Solutions
Gate Array solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Multiple actuator controller . . . . . . . . . . . . . . . . . . . . . . 4
NA7105x compliant PC peripheral integration . . . . . . . 5
Medical imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CPU/MCU interface extension . . . . . . . . . . . . . . . . . . . . 7
Graphics controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EMI noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Gate Array ASIC solution benefits . . . . . . . . . . . . . . . . . . . .10
CMOS-N5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CMOS-9HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
EA-9HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
CMOS-10HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CMOS-12M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Packaging solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Design service and support . . . . . . . . . . . . . . . . . . . . . . . . .18
2
Gate Array solutions
Gate Array ASICs are a well-established technology for
implementing customer specific logic functions in a simple,
fast and in particular a very cost-effective manner. They can be
used for many purposes in all kind of applications.
In Gate Array ASICs the customer specific functions are
implemented via the metallization layers. In contrast to field
programmable gate arrays (FPGAs), where the customer logic
functions are stored in SRAM memories for the sake of reprogrammability, Gate Array ASICs show various advantages,
especially when there is no need for re-programmability and
volumes exceed a certain value. This brochure will show you
in detail where the specific advantages of Gate Array ASICs in
comparison with FPGAs are.
Also, as an integrated device manufacturer (IDM), NEC
Electronics is governing all competence and know-how of
its Gate Array ASIC process technologies. This does not only
explain the excellence of the products but also explains, why
NEC Electronics is in the position to maintain production
for many years. The life time of Gate Array ASIC process
technologies at NEC Electronics typically exceeds 15 years.
This brochure provides examples and suggestions to show
how easily and effectively Gate Array ASICs can be used to
offer solutions in various application fields. It also describes
in detail when and why the conversion of field programmable
gate arrays (FPGAs) into Gate Arrays makes sense, not only for
commercial, but also for technical reasons.
In contrast to Cell-based IC (CB-IC) ASICs, where the
customer specific functions are already implemented starting
from the transistor level, Gate Array ASICs are faster and
easier to design and feature significantly lower non-recurring
engineering (NRE) cost.
So, in the context of Gate Array ASICs, cost-efficiency has
many faces:
•
Low non-recuring engineering cost (NRE)
•
Low unit cost
•
Low development cost due to fast and simple
design-flows
NEC Electronics has been the world-wide leader in Gate
Array ASICs for more than a decade meanwhile. This success
is based upon a deep understanding of technology and most
importantly of customer requirements.
Gate Array ASIC product overview
Product
Gate length
(drawn)
[µm]
Core supply
voltage
[V]
Interface
voltages
[V]
Metal
layers
[number]
Max.
gate count
[raw ASIC gates]
Embedded memory
CMOS-N5
0.5
5 / 3.3 / 3.0
5 / 3.3 / 3.0
2
123k
–
CMOS-9HD
0.35
3.3
5 / 3.3
3/4
2.5M
–
EA-9HD
0.35
3.3
5 / 3.3
3/4
2.5M
Flexible, CB-IC type
CMOS-10HD
0.25
2.5 / 1.8
3.3 / 2.5 / 1.8
4/5
2.6M
–
CMOS-12M
0.15
1.5
3.3 / 2.5 / 1.8
5/6
4.4M
max. 2.7 Mbit
(More details on the individual benefits of each technology are described later.)
3
Application example: Multiple actuator controller
Challenge
Controlling multiple external drivers
Solution proposal diagram
4
Solution advantages
Through its true 5 V interfacing capabilities and its very low unit and NRE cost,
CMOS-N5 Gate Array technology is the ideal solution to support solutions, where
multiple devices, each with rather low individual complexity, are required.
Solution specific
key features
•
Full 5 V driving capabilities
•
Very low NRE and unit cost
•
Low-complexity with fast and easy design capabilities
Application example: NA7105x compliant PC peripherals + logic
Challenge
Integration of single or multiple NA7105x compliant peripheral blocks together
with customer specific logic in a single device.
Block diagram
Solution
CMOS-N5 Gate Array technology
µPD6589A master / 80-pin TQFP package
Further solution proposal
Available number of peripheral cores
2 pieces
3 pieces
4 pieces
µPD71051 µPD65881
µPD65941
48-pin TQFP
µPD65894
µPD65942
64-pin TQFP
µPD65894
µPD65942
64-pin TQFP
µPD65894
µPD65942
80-pin TQFP
µPD71054 µPD65892
µPD65941
48-pin TQFP
µPD65883
µPD65942
64-pin TQFP
µPD65883
µPD65942
64-pin TQFP
µPD65883
µPD65942
64-pin TQFP
µPD71055 µPD65880
48-pin TQFP
µPD65892
80-pin TQFP
µPD65882
100-pin TQFP
µPD65894
144-pin LQFP
µPD71059 µPD65881
µPD65941
48-pin TQFP
µPD65882
µPD65941
48-pin TQFP
µPD65894
µPD65941
64-pin TQFP
µPD65894
µPD65941
80-pin TQFP
1 piece
NA71051 <=> 8251: Serial control unit
NA71054 <=> 8254: Programmable timer unit
NA71055 <=> 8255: Parallel interface unit
NA71059 <=> 8259: Interrupt control unit
5
Application example: Medical imaging
Challenge
High-speed data handling with low-power consumption
Solution proposal diagram
6
Solution advantages
CMOS-10HD Gate Array technology is ideally suited for high-performance, lowpower applications with high-bandwidth data processing.
Solution specific
key features
•
High-speed Gate Array technology
•
2.5 V or optionally 1.8 V supply voltage
•
LVDS and other high-speed buffers available
Application example: CPU/MCU interface extension
Challenge
Individual and flexible extension in accordance with exact customer requirements.
Solution proposal diagram
Solution advantages
EA-9HD/CMOS-9HD offers a wide range of masters in order to allow integration of
solutions with small to large complexity.
Solution specific
key features
•
3.3 V core supply voltage
•
Special I/F buffer (eg. USB) availability
•
EMI noise reduction features
•
Standard interface IP macros
•
PCI buffers
7
Application example: Graphics controller
Challenge
High-performance graphics controller with integrated DDR SDRAM memory
interface
Solution proposal diagram
8
Solution advantages
CMOS-12M offers a wide range of masters in order to allow integration of solutions
with large complexity. The pre-diffused high-density SRAM memory fits all
upcoming memory requirements. CMOS-12M is a deep sub-micron technology
featuring 1.5 V supply voltage and a very low power consumption at high-speed.
Solution specific
key features
•
Low power consumption
•
High-speed technology
•
Special I/F buffer (eg. SSTL, LVDS) availability
•
Embedded SRAM
•
Wide range of packaging solutions
Special feature:
EMI noise reduction
Challenge
Reduction of electro-magnetic interference (EMI) noise induced by the circuit in
susceptible applications and environments.
Application 1:
Capacitance cells
Capacitance cells can be allocated to any space in the internal core area.
Noise is reduced because capacitance cells absorb clock noise.
Key benefit:
EMI noise reduction without
compromising die area efficiency.
Application 2:
SSCG clock generator
A ±5% modulation for source clock signal is applied.
EMI peak is flattened because of the spreading of the clock noise.
Spread-spectrum clock generation
Key benefit:
Generic EMI noise reduction
Application 3:
Power line isolation
Power line isolation between core and I/O.
Key benefit:
Noise from internal circuits is
isolated from I/O signals.
9
Gate Array ASIC solution benefits
Gate Array ASIC solutions from NEC Electronics by nature have
some very strong advantages over other solutions such as SRAMbased field-programmable gate arrays (FPGAs).
✓
Wide range operating ambient
temperature / Ta
All Gate Array solutions offered by NEC
Electronics feature a full ambient temperature
range from -40 up to +85°C. Depending on
individual packaging/mounting solutions, junction
temperature (Tj) of +125°C is possible.
✓
Single supply voltage
NEC Electronics’ Gate Array solutions only require
a single supply voltage with an accuracy of just +/10% for proper operation.
✓
High performance
Due to the fact that Gate Array solutions use hardwired connections for the logic implementation they
are inherently faster than other solutions like FPGAs.
✓
Low power consumption
Gate arrays show a much smaller* power
consumption in comparison to FPGAs for two
reasons: Firstly, the hard-wired logic results in
much smaller leakage currents and secondly, the
rush current during the power-on phase is also
significantly lower.
* up to one order of magnitude
✓
10
Small number of I/Os
For the same application, gate array ASICs need
significantly less I/O pins than other solutions.
Firstly, no programming pins are required and
secondly – due to lower power consumption – less
power & ground pins are needed. The reduction
of I/O package pins usually comes along with the
reduction of package size.
✓
Fast start-up time
As Gate Array ASICs are hard-wired and do not
need to be re-programmed after powering up, they
are started-up much faster than FPGAs. Gate arrays
typically need less than 1 msec for starting-up.
✓
Low failure rate
Gate array ASICs show a very low failure rate of
typically less than 3 FIT. Again, due to their SRAMbased architecture, FPGAs feature much worse
values here. So-called soft errors (SER), which the
latest generation FPGAs are extremely susceptible to,
are unknown to Gate Array ASICs.
✓
High design data security
(Copy protection)
The circuit data with the customer proprietary
design details are protected by hard-wired
connections within the Gate Array chip. Compared
to FPGAs, there is no bit stream necessary from the
outside for re-programming at every start-up.
✓
Direct 5 Volts interface
With NEC Electronics Gate Arrays ASICs direct
5V connections are possible without any additional
external components (e.g. resistors).
✓
Wide choice of packaging
solutions
NEC Electronics’ Gate Array ASICs are available
with a very wide choice of different packaging
solutions, ranging from high-end Advanced BGA
(ABGA) packages to very small outline, low pin-count
Tape Fine-Pitch BGA (TFPBGA), SSOP or QFN
packages.
11
CMOS-N5
Extremely short development and production turn-around
times make CMOS-N5 a very quick and easy solution, perfectly
fitting for small, very low-cost companion ASICs.
Special Features
Besides, this CMOS-N5 is a true 5 V technology.
Available packages
•
0.5 µm drawn gate length
•
QFP, LQFP, TQFP,
•
5 V or 3.3 V +/- 10% supply voltage libraries
•
FPBGA, TFPBGA
•
Ambient operating temperature from - 40 to +85°C
(industrial)
•
SSOP
•
QFN
Specification
Process
0.5 µm CMOS process
Number of usable gates
1,500 to 92,500 gates
Supply voltage range
2.7 ... 5.5 V
Internal gate
0.21 ns (supply voltage: 5.0 V, F/O=1, typical wire length)
0.28 ns (supply voltage: 3.3 V, F/O=1, typical wire length)
Power gate
0.16 ns (supply voltage: 5.0 V, F/O=1, typical wire length)
0.22 ns (supply voltage: 3.3 V, F/O=1, typical wire length)
Input buffer
0.23 ns (supply voltage: 5.0 V, F/O=1, typical wire length)
0.31 ns (supply voltage: 3.3 V, F/O=1, typical wire length)
Output buffer
1.30 ns (supply voltage: 5.0 V, IOL=9 mA, CL=15 pF)
2.02 ns (supply voltage: 3.3 V, IOL=9 mA, CL=15 pF)
Delay time
Typical operating frequency
(depends on the circuit configuration)
12
5 V operation: 80 MHz
3.3 V operation: 50 MHz
3.0 V operation: 30 MHz
Output drive capacity
IOL = 3, 6, 9, 12, 18, 24 mA
Operating ambient temperature
TA = -40 to +85°C (Tjunction up to +125°C)
I/O buffer
CMOS level, TTL level (no output), oscillation block (MHz band)
Memory macro
Asynchronous high-density single-/dual-port RAM
Mega macros
- Programmable DMA controller
- Serial control unit
- Programmable timer counter
- Parallel interface unit
- Interrupt control unit
- UARTs
Test related
SCAN, BSCAN
Other macros
CTS
CMOS-9HD
CMOS-9HD features a well proven mid-performance process
that allows for flexible implementation of high complexity
designs making use of 3 or optionally 4 metal layers. System
performances beyond 100MHz can easily be achieved.
Special Features
Available packages
•
0.35 µm drawn gate length
•
QFP, LQFP, TQFP,
•
3.3 V supply voltage libraries
•
FPBGA, TFPBGA
•
Ambient operating temperature from - 40 to +85°C
(industrial)
•
TBGA, PBGA, ABGA
•
QFN
•
High speed I/O‘s: GTL, GTL+, HSTL, SSTL, pECL, PCI
Specification
Process
0.35 µm CMOS process
Number of usable gates
9,700 to 1,500,000 gates
Supply voltage range
3.0 ... 3.6 V
Delay time
Internal gate
131 ps (F/O=1, typical wire length)
Power gate
107 ps (F/O=1, typical wire length)
Input buffer
229 ps (F/O=2, typical wire length)
Output buffer
1.396 ps (IOL=9 mA, CL=15 pF)
Typical operating frequency
100 MHz
Output drive capacity
IOL = 1, 2, 3, 6, 9, 12, 18, 24 mA
Operating ambient temperature
TA = -40 to +85°C (Tjunction up to +125°C)
I/O buffer
3.3 type, 5 V tolerant, PCI, GTL+, oscillation block (MHz band)
Memory macro
- Synchronous high-speed dual-port compiled RAM
- Asynchronous high-speed single-/dual-port compiled RAM
- Asynchronous high-density single-/dual-port RAM, ROM
Mega macros
- Serial control unit
- Programmable timer counter
- Interrupt control unit
- UART
Test related
SCAN, BSCAN
Other macros
CTS, DPLL (for phase control, for multiplication)
(depends on the circuit configuration)
- V30
- 8051 compatible CPU
- CAN
13
EA-9HD
EA-9HD is an advanced embedded array 0.35 µm CMOS
process with 3 or optionally 4 metal layers. EA-9HD is based
on a high-density, high-speed channel-less sea-of-gates (SOG)
architecture that enables embedded high-density cell-based
SRAM blocks. EMI noise is reduced by filling up the empty
area of an internal circuit with special capacity cells and/or by
separating the power supply line of the internal circuit and the
I/O part.
Special Features
Available packages
•
3.3 V supply voltage
•
QFP, LQFP, TQFP,
•
5V full-swing I/Os
•
FPBGA, TFPBGA
•
SSCG(spread spectrum clock generator) macro to
suppress EMI noise
•
TBGA, PBGA, ABGA
•
QFN
Specification
Process
0.35 µm CMOS process
Number of usable gates
9,700 to 1,500,000 gates
Supply voltage range
3.0 ... 3.6 V
Delay time
Internal gate
131 ps (F/O=1, typical wire length)
Power gate
107 ps (F/O=1, typical wire length)
Input buffer
229 ps (F/O=2, typical wire length)
Output buffer
1.396 ps (IOL=9 mA, CL=15 pF)
Typical operating frequency
100 MHz
Output drive capacity
IOL = 1, 2, 3, 6, 9, 12, 18, 24 mA
Operating ambient temperature
TA = -40 to +85°C (Tjunction up to +125°C)
I/O buffer
3.3 type, 5 V full-swing, PCI, GTL+, oscillation block (MHz band, KHz band)
Memory macro
- Synchronous high-speed dual-port compiled RAM
- Synchronous high-density single-/dual-port compiled RAM, ROM
Mega macros
- Serial control unit
- Programmable timer counter
- Interrupt control unit
- UART
- POR (power-on-reset)
Test related
SCAN, BSCAN
Other macros
CTS, DPLL (for phase control, for multiplication),
APLL (for phase control, for multiplication), SSCG PLL
(depends on the circuit configuration)
14
- V30
- 8051 compatible CPU
- CAN
CMOS-10HD
CMOS-10HD features a high-density 0.25 µm CMOS
process with a channel-less sea-of-gates (SOG) structure.
3 or 4 metal layers are available. CMOS-10HD also offers two
multi supply voltage options: 3.3 V (interface) / 2.5 V (internal)
or 3.3 V (interface) / 1.8 V (internal). The 1.8 V supply voltage
option is ideally suited to applications requiring low-power
consumption.
Special Features
Available packages
•
•
•
•
•
•
•
•
0.25 µm drawn gate length
2.5 V and 1.8 V supply voltage libraries available
Ambient operating temperature from - 40 to +85°C
(industrial)
High speed I/Os: LVDS, SSTL2/3, PECL, PCI, GTL+
QFP, LQFP, TQFP,
FPBGA, TFPBGA
TBGA, PBGA, ABGA
QFN
Specification
Process
0.25 µm CMOS process
Number of usable gates
38,000 to 1,563,000 gates
Supply voltage
range
Single power supply
1.65 ... 2.0 V, 2.25 ... 2.75 V
Dual power supply
Internal: 1.65 ... 2.0 V, 2.25 ... 2.75 V
I/O:
1.65 ... 3.6 V
Internal gate
163 ps (internal power supply = 1.8 V, F/O = 1, typical wire length)
113 ps (internal power supply = 2.5 V, F/O = 1, typical wire length)
Power gate
139 ps (internal power supply = 1.8 V, F/O = 1, typical wire length)
91 ps (internal power supply = 2.5 V, F/O = 1, typical wire length)
Input buffer
243 ps (internal power supply = 1.8 V, 1.8 V input buffer, F/O = 1, typical wire length)
173 ps (internal power supply = 2.5 V, 2.5 V input buffer, F/O = 1, typical wire length)
Output buffer
1246 ps (internal power supply = 1.8 V, 1.8 V output buffer, IOL = 12 mA, CL = 15 pF)
776 ps (internal power supply = 2.5 V, 2.5 V output buffer, IOL = 12 mA, CL = 15 pF)
Delay time
Typical operating frequency
(depends on the circuit configuration)
Internal power supply 2.5 V: 133 MHz
Internal power supply 1.8 V: 66 MHz
Output drive capacity
IOL = 1, 2, 3, 6, 9, 12, 18, 24 mA
Operating ambient temperature
TA = -40 to +85°C (Tjunction up to +125°C)
I/O buffer
1.8 V type, 2.5 V type, 3.3 V type, LVDS, SSTL2/3, PECL, PCI, GTL+
Memory macro
Synchronous high-speed single-port or dual-port compiled RAM
Mega macros
- Programmable DMA controller
- Serial control unit
- Programmable timer counter
- Parallel interface unit
- Interrupt control unit
- UART
- PCI
Test related
SCAN, BSCAN
Other macros
CTS, DPLL (for phase control, for multiplication)
- V30
- 8051 compatible CPU
15
CMOS-12M
CMOS-12M represents the link between Gate Array
technologies and deep-submicron ASICs. It is based on a
150 nm node length CMOS process with channel-less seaof-gates (SOG) structure, making use of 5 or 6 metal layers
for optimum routing. One key feature of CMOS-12M is the
availability of embedded high-density dual-ported SRAM
memory blocks.
Special Features
Available packages
•
150 nm node length, 1.5 V supply voltage
•
QFP, LQFP,
•
Sea-of-gates architecture with embedded high-density
SRAM memory blocks
•
FPBGA, TFPBGA
•
PBGA, ABGA
•
Ambient operating temperature from - 40 to +85°C
(industrial)
•
Low unit cost and low NRE
Specification
Process
150 nm node length CMOS process
Number of usable gates
125,000 to 2,000,000 gates
Package
100/144 LQFP, 208 QFP(FP), 108/160/208 FPBGA,
256/324/449/676 PBGA, 352/500/576/672/756 ABGA
Supply voltage range
Internal: 1.5 ± 0.15 V
External: 1.35 ... 3.6 V
Power consumption
19.6 nW/MHz/gate (Operation rate = 0.35)
Delay time
62 ps (2-input NAND, F/O=1, typical wire length)
Typical operating frequency
200 MHz
Output drive capacity
IOL = 3, 6, 9, 12 mA
Operating ambient temperature
TA = -40 to +85°C (Tjunction up to +125°C)
I/O interface
3.3 V CMOS, LVTTL, LVPECL, 2.5 V CMOS, 2.5 V LVDS,
SSTL2, SSTL3, 2.5 V LVPECL, 3.3 V PCI, HSTL, GTL+
Memory macro
Synchronous 1-port or 2-port compiled RAM, Embedded RAM
Mega macros
- UART
- PCI controller
- DDR controller
Embedded macros
- SRAM: Synchronous dual-port compiled RAM
- APLL: Phase-shift type, SSCG type
- DLL: For high-speed SDRAM interface
Embedded test related
SCAN, BSCAN, BIST
(depends on the circuit configuration)
16
Packaging solutions for Gate Array ASICs
A wide variety of different packaging solutions is available
for NEC Electronics’ Gate Array ASIC technologies.
NEC Electronics focusses particularly on very small-outline
packages with low pin counts. All solutions are
available in RoHS-compliant versions.
QFP (Quad Flat Pack)
•
Well-established, general purpose package
•
44 to 376 pins
•
0.4 mm to 1 mm pin pitch
•
1 or 2.7 mm package height
[T]FPBGA ([Tape] Fine Pitch Ball Grid Array)
• Small footprint, low-height and low-weight chip-size package
• 61 to 400 balls
• Versions from 0.5 mm up to 1 mm ball pitch available
• Ultra low-profile versions with 0.65 mm height (TFPBGA)
available
TBGA (Tape-automated bonding Ball Grid Array)
•
Improved thermal characteristics
•
256 to 768 balls
•
1 or 1.27 mm ball pitch
PBGA (Plastic Ball Grid Array)
•
High-ball count, low-cost BGA package
•
225 to 672 balls
•
1.27 mm ball pitch
QFN (Quad Flat No leads)
•
Very small outline, similar to TFPBGA
•
Larger lead pitch, better suited for low-cost PCBs
SSOP (Small Single Outline Package)
•
20/30-pin option available
•
Standardized package solution
17
Solution design-in support
As an integral part of its Gate Array ASIC solutions,
NEC Electronics also offers to support its customers at the
requested design entry point. Thus, customers who are not
familiar with the Gate Array ASIC design flow specifics will be
also able to have their design turned into silicon in a smooth
way within very short time.
NEC Electronics uses primarily the RTL
handover interface for doing FPGA conversions.
RTL handover benefits:
C
Start of design
Development of FPGA incl. testbench (customer)
Delivery of VHDL-database, pinout, constraints to NEC
C
N
Conversion of database, SCAN insertion, ATPG (NEC)
10
days
Layout (NEC)
N
1
day
C
N
1
day
N
17
days
Samples delivery
The design source files are optimized directly on
NEC Electronics libraries
•
This is a very efficient way of conversion
resulting in reduced chip cost
•
This method requires VHDL or Verilog
synthezisable source files
•
Memories are mapped one by one as specified
in the netlist
•
This method can be handled regardless of the
design entry method used
C
N
Joint approval of layout data, delivery of marking data
•
The diagram shows the different steps through
the smooth and successful implementation of a Gate
Array ASIC. The numbers at the right hand side
describe the number of working days required on the
basis of a CMOS-N5 design example.
C: Customer
N: NEC Electronics
Key benefits
18
•
Complete design and layout are done in Europe
•
Customers receive personal design support throughout the entire design
•
Long lasting experience and reliable support based upon several hundred customer designs already completed
Gate Array Solutions by NEC Electronics
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel:
0211-65 030
Fax:
0211-65 03 1327
Offices in Europe:
www.eu.necel.com/europe
Distributors in Europe:
www.eu.necel.com/distributors
NEC Electronics Corporation
Kawasaki, Japan
Tel:
044-435-5111
Fax:
044-435-1667
Offices world-wide:
www.eu.necel.com/global
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel:
408-588-6000
800-366-9782
Fax:
408-588-6130
800-729-9288
Internet:
www.eu.necel.com/asic
E-mail:
[email protected]
© Published by
NEC Electronics (Europe) GmbH
Printed in Germany, August 2006
Document No. A18020EE1V0PF00
All product, brand, or trade names used in this pamphlet
are the trademarks or registered trademarks of their
respective owners.
Product specifications are subject to change without notice.
To ensure that you have the latest product data, please
contact your local NEC Electronics sales office.
www.eu.necel.com