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Lepix:
monolithic detectors for particle tracking in standard
very deep submicron CMOS technologies.
A. RIVETTI
I.N.F.N. sezione di Torino, via P. Giuria 1
Torino, 10125, Italy
W. SNOEYS, M. CASELLE, K. KLOUKINAS
CERN CH-1211, Geneva 23, Switzerland
A. DOROKHOV
Institut de Recherches Subatomiques
23 rue du Loes - BP28- F6703, Strasbourg, France
P. CHALMET, H. MUGNIER, J. ROUSSET
MIND-MicroTechnologies-Bât. Le Mont Blanc
74160, Archamps, France
A. Rivetti
Villa Olmo, 7/10/2009
Outline
 Motivations
 Sensor design
 Front-end electronics
 Prototyping strategy and R&D timeline.
 Conclusions.
A. Rivetti
Villa Olmo, 7/10/2009
High resolution silicon detectors: state of the art
• Hybrid pixels: detectors and electronics fabricated on
different substrates.
• Charge collection by drift, good radiation hardness.
• Pixel size: 50 mm x 50 mm to 50 mm x 400 mm.
• Complex front-end electronics, high read-out speed.
•Typical power density: 250 mW/cm2.
• MAPS: detector and electronics on the same substrate.
• Only commercial CMOS technologies.
• Pixel size: 20 mm x 20 mm or lower.
• Slower read-out speed.
• Charge collected by diffusion, more sensitive to bulk
damage.
• Power density for fast options: 100 mW/cm2.
• Silicon strips: detector and front-end electronics on
different substrates.
• Suitable to cover large areas at low particle densities.
• Power density: 20mW/cm2.
A. Rivetti
Villa Olmo, 7/10/2009
Lepix goal
Exploiting the features of very deep submicron CMOS processes to combine most of
the advantages of the previous technologies:
 Good radiation hardness (charge collection by drift).
 High speed: parallel signal processing for every pixel.
 Low power consumption: target 20 mW/cm2.
 Monolithic integration.
 Use of CMOS technologies with high production rate (20 m2 per day…)
Lepix is a collaboration between CERN, IReS in Strasbourg and INFN.
Interest also from Imperial College
Within INFN it is a project funded by the R&D scientific committee.
A. Rivetti
Villa Olmo, 7/10/2009
Standard CMOS on lightly doped substrates
 First feedback from the foundry that standard deep submicron CMOS processes
can be reliably implemented with wafer of higher resistivity (> 100 W · cm).
Sensitive node
Sensitive
node
Sensitive node
Sensitive
node
Aggre ssor
Aggre
ssor node
no de
Analog ground
Analog
ground
Analog ground
Analog
ground
Digital ground
Digital
ground
Substrate contact
Substrate
contact
Junction
Junction
capacitance
capacitance
Digital ground
Digital
ground
Substrate contact
Substrate
contact
Substrate contact
Substrate
contact
Junction
Junction
capacitance
capacitance
Epi-layer
Epi-layer
Highly doped
Highly
dopedsubstrate
su b strate
a)
Aggre ssor
Aggre
ssor node
no de
Lightly doped
Lightly
dopedsubstrate
su b strate
b)
 Higher substrate resistivity enhances the separation between different circuit blocks
(better insulation between digital and analogue).
 A resistivity of 200 W · cm should allow a uniform depletion layer of 30 mm – 40 mm with a
reverse bias voltage of 100 V.
 Collection by drift + moderate resistivity: good radiation hardness (adequate for LHC
upgrades).
A. Rivetti
Villa Olmo, 7/10/2009
First sensor concepts
Pmos input device.
Bias circuit
nwell collection diode
 Charge to voltage conversion on the sensor
capacitance
 For 30 mm depletion and 10fF capacitance:
38 mV for 1 mip.
Processing
electronics
 Only one PMOS transistor in the pixel.
 Each pixel is permanently connected to its front-end electronics located at the
border of the matrix.
 Each pixel has one or two dedicated lines: need of ultra fine pitch lithography =>
90 nm CMOS.
A. Rivetti
Villa Olmo, 7/10/2009
Issues in sensor design
 Challenge is in obtaining a uniform depletion layer.
 Optimal geometry and segmentation of the read-out electrode.
 Effective charge resetting scheme.
 Pattern density rules in very deep submicron technologies are very restrictive.
 Insulation of the low-voltage transistors from the high voltage substrate.
Sensor is designed in close contact with the foundry!
A. Rivetti
Villa Olmo, 7/10/2009
Sensor segmentation (1)
 Signal is proportional to:
Q  collected charge
C electrode capacitanc e
m=1/2 in weak inversion
 Noise is proportional to: 1  1m
gm I
 Signal to noise ratio is proportional to:
m=1/4 in strong inversion
Q m
CI
m≤1/2
 If C and I are reduced by the same factor SNR improves.
 The game pays till charge sharing and inter-pixel capacitance come into
play
 Strategy: have (reasonably) small pixels at the very front-end and group
them afterwards according to the required space resolution.
A. Rivetti
Villa Olmo, 7/10/2009
Sensor segmentation (2)
 For a full parallel read-out sensor size is also limited by the pitch of the
metal lines.
 The technology allows for at least five very dense metal layers, possible to
have full reticle chips with LHC-grade pixels.
Pmos input device.
 One or two metal lines are needed for every
pixel
 Metal routing and sensor layout must obey the
pattern density rules.
nwell collection diode
Pmos input device.
 In practice, to minimize the electrode
capacitance and maximize the signal the electrode
size will be much smaller than the pixel pitch.
nwell collection diode
A. Rivetti
Villa Olmo, 7/10/2009
Options for resetting the input transistor
Bias circuit
Bias circuit
Vref
Vref
Bias circuit
Vref
Vctrl
Processing
electronics
 Continuous reset with diodes
A. Rivetti
Processing
electronics
 Continuous reset with transistor
Processing
electronics
 Pulsed reset
Villa Olmo, 7/10/2009
Sensor simulations
Pixel used in this simulation was 50 mm x 50 mm.
With the highest resistivity substrate available 80 mm depletion with 100 V
A. Rivetti
Villa Olmo, 7/10/2009
Sensor read-out: source follower configuration
 The current signal is converted
to a voltage step by integration on
the input parasitic capacitance (~
10 fF).
bias
VTH
 The voltage step is sensed at the
source and fed to a preamplifiershaper-discriminator chain .
 Stack of only two transistors.
 Margin to operate the sensor at low power supply (0.6 V).
 Enough headroom for leakage induced DC variations.
 Only one external line per pixel.
 The rise time of the signal, but not its final amplitude sensitive to the parasitic
capacitance of the line.
A. Rivetti
Villa Olmo, 7/10/2009
Voltage-mode read-out simulations
 Power constrained to 1 mW per
channel, (sensor, amplifier
discriminator).
 10 mW/cm2 for 100 mm x 100
mm pixels
 10 fF input capacitance and
1200 electrons signal assumed.
 Line capacitance 2 pF.
 Peak about 60 mV.
 ENC 40 electrons
A. Rivetti
Villa Olmo, 7/10/2009
Possible analogue measurement with ToT
Time over threshold
 ENC 40 electrons rms.
 SNR of 15 for 600
electron signal.
Time walk
 Response delay of 50
ns for 600 electrons.
Minimum signal to have response within 25 ns is about 2500 electrons.
Time over threshold can be explored to recover the timing. Trade-off
between digital and analogue power consumption
A. Rivetti
Villa Olmo, 7/10/2009
Current-mode read-out
 The current signal is converted to a voltage step by
integration on the input parasitic capacitance (~ 10 fF).
bias
 The voltage signal is converted back to a current by
the in-pixel transistor.
 Stack of up to six transistors, possible because of weak
inversion operation.
 Two lines per pixel.
 Current read-out allows for very compact current
comparator and a more compact front-end cell.
bias
A. Rivetti
ITH
Both line capacitances play an important
role in the shaping of the signal.
Villa Olmo, 7/10/2009
Current-mode readout simulations
Time over threshold
Time walk
 With current mode 25 ns timing is achieved for 600 electrons and 2 mW
of power
Time over threshold works also for the current mode approach.
A. Rivetti
Villa Olmo, 7/10/2009
Jitter performance
A. Rivetti
Villa Olmo, 7/10/2009
Matrix readout
 Signals are sent in analog form
towards the periphery of the
matrix.
 The clock is distributed only in
the periphery.
 All NMOS device must be in
triple well to insulate them from
the “hot” substrate. Custom
digital library is needed.
 Particular care to manage SEE
given the small feature size of
the technology.
A. Rivetti
Villa Olmo, 7/10/2009
Matrix readout issues
 Analog power basically determined by SNR required. Easily predicted once
the analog blocks are defined.
 Digital power dependent on the switching activity, so it can be quite different
even for the same architecture working under different occupancy conditions.
 Area and power must be minimized Data storage is a critical item. Only
storage of valid hits.
 High pixel granularity is dictated by the optimization of the analog power.
Grouping of pixels after the very front-end if space resolution and occupancy
requirements allow it.
 If the detector has to contribute to trigger primitives also data transmission
becomes a very critical issue.
 The power of a standard high-speed LVDS transmitter is already a few milliwatts, with a few links the digital power consumption will exceed the analog one.
A. Rivetti
Villa Olmo, 7/10/2009
Prototyping plans
 A first submission is in preparation before the end of the year.
 Several matrices with different sensor optimization will be implemented.
 Sensors will be read-out with a maps-like architecture.
 A few simplified front-ends with preamp-shaper and current readout will be
also implemented
 The design will be already use higher resistivity wafers.
 A prototype with more elaborated front.-end and first digital readout
schemes will be developed within next year.
A. Rivetti
Villa Olmo, 7/10/2009
Conclusions
 A cooperative research effort being established between CERN, INFN and
IReS to investigate new type of monolithic sensors.
 Technique: commercial very deep submicron CMOS implemented on lightly
doped substrates.
 Sensors simulation are very encouraging.
 A first submission to the foundry scheduled very soon.
 First experimental results expected early in 2010.
A. Rivetti
Villa Olmo, 7/10/2009