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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on October 19, 2002 by Dimitrios Katsis ([email protected])
Borivoje Nikolić
1.
Homework #7 Solutions
EECS 141
Logical Effort of Transmission Gates
2.5V
0.0V
in
out
2.5V
CL
Figure 1
Calculate the logical effort of the circuit shown in Figure 1 assuming that W p=2Wn=2L=2Lmin and that the equivalent
resistances of the PMOS and NMOS are equal to R.
If Reqp and Reqn the PMOS and NMOS equivalent resistances respectively, the equivalent resistance
of the circuit during pull-up and pull-down is respectively
ReqLH  Reqp  ( Reqp // Reqn )
ReqHL  Reqn  ( Reqp // Reqn )
Since Reqp  Reqn  R the above equations give
Req  ReqLH  ReqHL  3R / 2
For the equivalent resistance to be equal to that of the minimum sized inverter (R), the input
transistors should be made 3/2 times larger, increasing thus the input capacitance by 3/2 (compared to
the minimum sized inverter). Hence, the logical effort of the circuit is
g  3/ 2
Note: If we would like to have more accurate results, we could take into account that the PMOS
transistor is better in pulling up and the NMOS in pulling down by increasing the NMOS and PMOS
equivalent resistance by a factor of 2 during a rising and falling transition respectively. In this case:
Reqp // Reqn  R //( 2 R)  2 R / 3
Hence, in this case g  5 / 3 .
1
2.
Happy fun dynamic logic
Dynamic logic is fun! Hopefully you’ll still think so after this problem….
a)
Implement the following function in dynamic logic: F = ((A+B)C)’
Shown below in Figure 1
Figure 1: part a
Figure 2: part b
b) Cascade the output of the circuit into a second stage to implement F=[((A+B)C)’+D]’
Shown above in Figure 2
c)
Will the circuit in part b work correctly? Why or why not? If not, give an example of when the circuit works
incorrectly.
No, it will not work correctly. As we stated in lecture and discussion, precharg-evaluate blocks do
not cascade well because of erroneous discharge. An example is whenever it is in precharge, the
second stage output state will be indeterminate because the NMOS [with input ((A+B)C)’] is on
and the PMOS is on at the same time, fighting for control of the output. Uh oh!
d) The logic function in part b annoys your friendly TA (annoyed TA’s give hard problem sets!). Please help me out. I
don’t like having too many inversions (the ’) in a logic function. Write the equivalent function with only one ’ in it.
Hint: If you don’t understand what I mean, I don’t like multiple levels of inversion like (A’+B)’ if it is possible to
avoid. Think, what does (A’+B)’ equal?
(A’+B)’ = AB’, therefore [((A+B)C)’+D]’ = (A+B)CD’
e)
Draw a domino implementation of the circuit in part b/d.
Shown below in Figure 3
2
CLK
ABC+DAB
D
C
CLK
AB
A
B
CLK
Figure 3: part e
f)
Figure 4: part f
This part has nothing to do with the previous parts except it is also a dynamic circuit. Draw a multiple output domino
circuit with two outputs: AB and BAC+DAB.
Shown in Figure 4 above.
3.
Not so much fun dynamic logic
a)
Assuming that all inputs of the circuit shown in Figure 1 below are initially 0 during the precharge phase and that all
internal nodes are at 0V, calculate the voltage drop on Vo, if A changes to 1 (VDD=2.5V) during the evaluate phase. It
is given that Vtn0=0.5V, 2φF=0.6V and γ=0.4V0.5.
Hint: Don’t forget the body effect.
Assuming that ΔVout  Vtn , the capacitor C1 is charged to a voltage VS , which is the maximum
voltage for which M1 conducts. VS is calculated using the equation that is valid at the edge of
conduction and cut-off:
VGS  Vtn
 VGS  Vtn0  γ

2φF  VSB  2φF

Since the bulk of the NMOS transistors is connected to ground, the previous equation can be
rewritten as:
VG  VS  Vtn0  γ

2φF  VS  2φF
 VG  VS  Vtn0  γ 2φF  γ

 VG  VS  Vtn0  γ 2φF

2


2φF  VS

 γ 2 2φF  VS 
 VS2  4.78VS  5.234  0
3
4.78V  1.38V
 1.7V
2
(We accept only the lower solution of the quadratic equation, since after reaching this voltage the
transistor doesn’t conduct and can’t thus reach the higher value).
Hence, charge conservation yields:
C LVDD  C LVo  C1VS
 VS 
 C L ΔVo  C1VS
 ΔVo  C1VS / C L  0.44V
Since VG  VS  Vtn , Vtn  0.8V .
Hence, our assumption about ΔVo  Vtn  0.8V was correct.
b) Now calculate the voltage drop on Vo if both A and B change to 1 (under the above conditions).
Similarly to (a), capacitors C1 and C2 will be charged to a final voltage of 1.7V.
Hence, charge conservation gives:
C L ΔVo  C1VS  C2VS  ΔVo  0.88V  Vtn
Hence, our assumption that ΔVout  Vtn doesn’t hold anymore and ΔVo is calculated as follows:
ΔVo  VDD
Cs
, where C s  C1  C 2 .
Cs  CL
Hence,
ΔVo  2.5V
c)
20
 0.83V
20  40
What is the maximum number of transistors that can be connected in series to M1 and M2 (including M1 and M2,
excluding M0) if the output should not fall below 0.9V during the evaluate phase? Assume that each one of the new
transistors has the same intrinsic capacitance (to ground) as M1 and M2 (C=10fF).
The final value of Vo  0.9V corresponds to ΔVo  1.6V  Vtn . Hence, the following equation is
valid:
Cs
(1)
ΔVo  VDD
Cs  CL
where C s the total intrinsic capacitance to be charged.
The worst case is when all of the connected transistors conduct and thus C s  NC (where N the
number of the transistors). In this case (1) gives:
ΔVo ( NC  C L )  VDD NC
 NC(VDD  ΔVo )  ΔVo C L
1.6V  40 fF
N
 7.1 , hence N = 7.
0.9V  10 fF
4
2.5V
CLK
Vo
A
M1
B
M2
0
M0
CL=40fF
C1=10fF
C2=10fF
CLK
Figure 1
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