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Low power combinational circuit based on pseudo NMOS logic Rajeev Kumar1, Assit .Prof. UCST, Dehradun [email protected] AbstractDifferent logic families have been proposed from several years to improve the performance of the high speed circuits. Mostly used logic family is CMOS which requires equal number of nMOS and pMOS transistor but in some application it may be required to reduce the area. Pseudo nMOS logic is one of the alternative for that .In this paper, NOR-XOR, NAND-XOR and other combinational circuit using pseudo NMOS logic is proposed. The performance of the circuits is measured in terms of power consumption, delay and power delay product and the results are compared with existing standard pseudo nMOS logic circuit for different logic functions. All the circuits are simulated using TSpice on 180nm CMOS technology. Keywords Dynamic circuit, NOR, NAND, XOR, XNOR pseudo NMOS, Power consumption, Delay. I. Introduction The rapid integration of VLSI circuit is due to the increased use of portable wireless systems with low power budget and microprocessors with higher speed. To achieve high speed and lower power consumption transistor technology and power supply must be scaled down simultaneously. In one hand, the ever increasing market segment of portable electronic devices demands the availability of low-power building blocks that enable the implementation of longlasting battery-operated systems [1]. On the other hand, the general trend of increasing operating frequencies and circuit complexity, in order to cope with the through put needed in modern highperformance processing applications, requires the design of very high-speed circuits. At the circuit design level, considerable potential for power savings exists by means of proper choice of a logic style for implementing combinational circuits. This is because all the important Vimal Kant Pandey2, Assit .Prof. DIT, University, Dehradun [email protected] parameters governing power dissipation, transition activity, and short-circuit currents are strongly influenced by the chosen logic style [2]. Depending on the application, the kind of circuit to be implemented, and the design technique used, different performance aspects become important, disallowing the formulation of universal rules for optimal logic styles. CMOS logic is providing the almost all requirements of designing high speed and low power circuits. One of the essential features of the CMOS logic circuits is that it employs equal number of nMOS and pMOS transistors. In addition, to balance the rise and fall times of the logic circuit, the size of the pMOS transistor generally needs to be larger than that of nMOS transistor. In some applications, it may be required to reduce the area of logic circuits in order to fit into specific area budget. There are many ways to solve this problem. The most widely used approach is pseudo nMOS logic. In this paper, different combinational logic circuits such as NANDNOR, XOR etc are designed and simulated. This paper has been segmented into three sections. Section I have introduction part while in section II basics of pseudo nMOS logic and previous work is discussed. Section III and IV presents simulation results and conclusion respectively. II. Pseudo-NMOS Logic Pseudo-NMOS logic is an example of ratio-ed logic which uses a grounded pMOS load and an nMOS pull-down network that realizes the logic function [2]. Figure 1 shows a basic pseudo CMOS inverter circuit. In this pMOS is connected to Gnd in place of a load [3] and each input is connected to gate of only one transistor [4]. Sreenivasa Rao, Ijjada et al [5] design a combinational logic using pseudo nMOS logic shown in figure 5. It consists of two inputs A and B and four outputs which give AND, NAND, XOR and XNOR logic functions having low transistor count and high speed compared to the other logic styles. The main advantage of this logic is, it uses only N+1 transistor verses 2N transistors for static CMOS. This reduces the gate complexity substantially at the cost of static power consumption. Transistor sizing is critical to maintain sufficient noise margins. In this logic the high output voltage for any gate is Vdd but the low output voltage is not ‘0’ volt. This results in decreased noise margin. Thus, the main drawback of this logic is very high static power consumption as there exists a direct path between Vdd and ground through the PMOS transistor. In order to make low output voltage as small as possible, the pMOS device should be sized much smaller than the nMOS pull-down devices. Also, to increase the speed particularly when driving many other gates the pMOS transistor size has to be made larger. Therefore there is always a tradeoff between the parameters noise margin, static power dissipation and propagation delay. Figure.3 Proposed Pseudo NMOS Logic (NAND, XNOR) Figure.4 Proposed Pseudo NMOS Logic (NAND, XNOR) In figure 6 and 7 to other circuits are proposed which gives output NOR, OR, XOR & XNOR and NOR, AND, AND, OR, XOR & XNOR respectively. Each of the proposed circuits consists of only two inputs A and B and more than two outputs depending on the design. The main design objectives for these circuits are low power consumption and higher speed at low supply voltage. Figure 1. Pseudo NMOS inverter III Proposed Circuit The proposed circuit of NOR-XOR and NANDXNOR gates in Pseudo-nMOS logic is shown in figure 2 & 3. Another NAND-XNOR circuit shown in figure 4 having lesser number of transistor as compared to circuit proposed in figure 2. Figure.2 Proposed Pseudo NMOS Logic (NOR, XOR) Figure 5. Pseudo nMOS Logic [5] Table2: Rise, fall time, Propagation delay, power consumption and power delay product for XNOR gate Fig.2 Fig3 Fig.4 Fig.5 Fig.6 Figure 6. Proposed Pseudo nMOS Logic (NOR, OR, XNOR, XOR) Rise time* 60 60 60 40 60 Falling Propagatio Power time * n delay* consumption # 9.6 34.80 1.5 9.6 34.80 .048 9.8 34.90 .097 29 34.50 .69 9.3 34.65 .28 Units- *=ns,&=ns*ns,#=pw PDP & 52.2 1.67 3.38 23.80 9.7 Comparison of rise, fall time, propagation delay, power consumption and power delay product for different proposed circuits for XOR and XNOR are shown form figure 8 to figure 17. Figure.8 Comparison of Rising Time delay for XOR gate Figure.7 Proposed Pseudo nMOS Logic (NAND, AND, NOR, OR, XNOR, XOR) IV. Simulation Result Simulation of all the designs presented in the paper is done on TSpice using 180nm technology. Performances of all presented designs are measured in terms of rise, fall time, propagation delay and power consumption. Table 1 and table 2 show the rise time, fall time, propagation delay, power consumption and PDP for XOR and XNOR gates respectively. Table1: Rise, fall time, Propagation delay, power consumption and power delay product for XOR gate Fig. 1 Fig4 Fig. 5 Fig. 6 Rise time* 40 40 60 .26 Falling time * 29 Propagatio n delay* 34.50 Power consumption # 10.28 PDP& 354.66 29 9.7 34.50 34.85 1.5 .69 51.75 23.80 .33 .29 .28 .081 Units- *=ns,&=ns * ns,#=pw Figure.9 Comparison of Falling Time delay for XOR gate Figure.10 Comparison of Propagation Delay for XOR gate Figure. 11 Comparison of Power Consumption for XOR gate Figure.12 Figure.15 Comparison of Propagation Delay for XNOR gate Comparison of PDP for XOR gate Figure. 16 Comparison of Power Consumption for XNOR gate Figure.13 Comparison of Rising Time delay for XNOR gate Figure.17 Comparison Figure.14 Comparison of Falling Time delay for XNOR gate of PDP for XNOR gate Conclusion In this paper, different combinational logic circuits are proposed using pseudo nMOS logic. Performances of all the circuits are calculated by simulating the designs in TSpice environment using 180nm technology. The simulation result shows that the proposed circuits consumes less power and have higher speed. References [1] Reto Zimmermann and Wolfgang Fichtner, “Low-Power Logic Styles: CMOS Versus PassTransistor Logic” IEEE Journal of Solid-State Circuit, vol. 32, No. 7, July1997 [2] Yngvar Berg, Omid Mirmotahari, “High Speed and Ultra Low-voltage CMOS NAND and NOR domino gates” World Academy of Science, Engineering and Technology 68 2012. [3] A. P. Chandrakashan and R. W. Brodersen, Low Power Digital CMOS Design, Kluwer, Norwell, MA, 1995 [4] Adel S. Sedra, Kenneth C. Smith, Microelectronic circuits, 5th edition, Oxford University Press,2003 [5] Sreenivasa Rao.Ijjada, Ayyanna.G , G.Sekhar Reddy, Dr.V. Malleswara Rao,“ Performance of Different CMOS Logic Styles for Low Power and High Speed” International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No. 2, June 2011. [6] Rabaey J,”Digital Integrated Circuits-A Design Perspective”, Prentice Hall, 1996. [7] A. Chandrakashan, R.Brodersen, “Low Power Digital CMOS circuits”, Kiuwer Academic publishers, 1995. [8] A Textbook “Neil H.E Weste and David Harris “CMOS VLSI Design. A circuits and systems Perspective [9] S. Dutta, S. Nag, K. Roy, “ASAP: A Transistor Sizing tool for speed, area, and power optimization of static CMOS circuits”, IEEE International Symposium on Circuits and Systems, pp. 61-64, June, 1994. [10] V.Oklobdzija, R.Montoya,” Design performance Trade off in CMOS-Domino Logic”, IEEE journal of Solid-state Circuit, vol21,pp.304309, 1986. [11] Low-Power CMOS Digital DesignAnantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, Fellow, IEEE 0018-9200/92$03.00 0 1992 IEEE [12] R.Krambeck, C Lee, H Law, High-Speed Compact Circuit with CMOS”, IEEE Journal of Solidstate Circuits, Vol 17, pp.614-619, 1982.