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Turkish Journal of Electrical Engineering & Computer Sciences http://journals.tubitak.gov.tr/elektrik/ Research Article Turk J Elec Eng & Comp Sci (2013) 21: 1972 – 1982 c TÜBİTAK ⃝ doi:10.3906/elk-1201-114 A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder Oktay AYTAR,1 Ali TANGEL,2,∗Kudret ŞAHİN2 Department of Electrical and Electronics Engineering, Abant İzzet Baysal University, Gölköy Campus, Bolu, Turkey 2 Department of Electronics and Communication Engineering, Kocaeli University, İzmit, Kocaeli, Turkey 1 Received: 30.01.2012 • Accepted: 14.06.2012 • Published Online: 24.10.2013 • Printed: 18.11.2013 Abstract: This paper presents a 5-bit flash analog-to-digital converter design using the 0.18- µ m Taiwan Semiconductor Manufacturing Company’s CMOS technology library. The designed system consists of 2 main blocks, a comparator array, and a digital decoder. The digital decoder contains a latch, 1-of-N decoder, and fat-tree encoder units. The 1-of-N decoder is implemented using 2 × 1 multiplexers. As a result, the active die area and the power consumption are reduced, in addition to an increase in the sampling frequency. The power supply voltage range for the overall system is ± 0.9 V. For testing purposes, a ramp signal of between –0.45 V and 0.7 V is applied to the converter input. The sampling frequency is 5 Gs/s. The simulation results include a maximum power consumption of 28 mW, integral nonlinearity values of between –0.65 least significant bits (LSB) and + 0.01 LSB, differential nonlinearity values of between –0.3 LSB and + 0.13 LSB, and an active die area of 0.1 mm 2 . Key words: Flash ADC, CMOS VLSI, high-speed data converters 1. Introduction Analog-to-digital converters (ADCs) are the most important core units to convert analog information to corresponding digital forms. This means that they can be considered as bridges between the real word and the digital world. ADCs are commonly used in the application areas of mobile phones, cameras, digital TVs, wireless sensor networks, transmitter and receiver circuits, and the conversion processes of the signals for baseband applications [1–4]. Flash ADC is known as the fastest type of ADC among designers. It has the most important role, especially for magnetic read channel applications, optical data recording, digital communication systems requiring a high data processing rate, and optical communication systems [5–8]. The fully parallel (fullflash) ADC architecture is depicted in Figure 1. In this scheme, the comparison processes, with all quantization levels, correspond to an instant analog input voltage level and are done simultaneously during only 1 cycle of the sampling clock signal. The 1st phase of the sampling clock is for sampling and the 2nd phase is for converting and obtaining output binary data [6]. This property makes the flash ADC the fastest one among the others. The most effective role for ADC performance is played by analog blocks. The design constraints related to the conversion speed are mostly defined by the performances of these blocks, especially by the comparators used in flash designs. The 2 well-known disadvantages for flash ADCs are their low resolution and higher power consumption due to a larger chip area when compared to other types of ADC architectures. ∗ Correspondence: 1972 [email protected] AYTAR et al./Turk J Elec Eng & Comp Sci R R + + + - Thermometer to Binary Decoder Block R Vinput Thermometer Code Block Vref,p N-Bits R Vref,n Figure 1. Flash ADC general architecture. There are several flash ADC designs proposed in the literature. However, the 5-bit ADC, which is advertised in this study, is different than the others in terms of the subblocks employed in it. It can be considered as a case study, which employs different design schemes and methods advertised in the literature to be able to obtain a higher performance full-flash ADC. Finally, a fast and highly linear 5-bit flash ADC design implementation is achieved in the 0.18-µ m CMOS technology using the Cadence IC design platform. This paper is a revised version of the authors’ earlier work [9]. The rest of the paper presents all of the design steps and related simulation results. The conclusion section compares the proposed ADC performance with similar designs from the literature. 2. The 5-bit CMOS flash ADC design steps The block diagram of the proposed flash ADC is shown in Figure 2. It consists of a comparator block, latch block, 2 × 1 MUX-based 1-of-N decoder block, and fat-tree–based encoder block. Analog Input Comparator Block Latch Block 2x1 Mux – Based 1-of-N Decoder Block Fat-Tree Encoder Block N-Bits Outputs Figure 2. The proposed flash ADC architecture. 2.1. The comparator structure In the designed ADC system, the comparator schematic shown in Figure 3 is chosen [10]. The transistor aspect ratios and critical DC bias voltages used in the comparator circuit are also given in Figure 3 and Table 1, respectively. In this circuit, M2 and M3 are the N-type metal-oxide-semiconductor (NMOS) input differential pairs driven by the tail current transistor M4. The differential pair is loaded by diode-connected P-type metaloxide-semiconductor (PMOS) transistors (M5–M6) and cross-coupled PMOS transistors (M0–M1), which serve as a positive feedback loop. The purpose of this feedback loop is to boost the differential voltage gain obtained by M2–M3 and to balance the output resistance. M9 and M10 form a current mirror and its reference current is provided by M5 and M7 together. The comparator’s first-stage output is additionally amplified by a commonsource PMOS amplifier (M8). The very last stage of the comparator is a basic CMOS inverter circuit (M11–M12). The DC analysis result of the complete comparator is shown in Figure 4, where it can be seen that a nice voltage comparison with almost zero input offset is obtained. 1973 AYTAR et al./Turk J Elec Eng & Comp Sci Vdd M5 M1 M0 M6 M8 M7 Vin M3 M2 M11 Vref output M12 M4 Vbias M10 M9 -Vdd Figure 3. The comparator schematic [10]. Table 1. Transistor aspect ratios of the comparator schematic. M0 M1 M2 M3 M4 M5 M12 Vbias Vref W/L (µm) 6/0.2 6/0.2 3/0.2 3/0.2 2/0.2 6/0.2 2/0.2 0.1 V 0.9 V W/L (µm) 6/0.2 6/0.2 6/0.2 2/0.2 2/0.2 6/0.2 M6 M7 M8 M9 M10 M11 2.2. The latch circuit The preferred dynamic latch circuit is depicted in Figure 5. The latch circuit either transfers the input logic level to the output (during which the clock signal is kept at logic ‘1’) or keeps the last output logic level (during which the clock signal is kept at logic ‘0’), depending on the controlling clock signal. DC Response 1000 750.0 out input 500.0 V (mV) Vdd M1 clk Wp M1 = M2 = 250.0 0 0.2 μ m Lp -500.0 -750.0 -1000 250.0 500.0 750.0 1000 -1000 -750.0 -500.0 -250.0 0 V(in) (E-3) Figure 4. The DC analysis result of the comparator. 6μ m M2 ref -250.0 1974 = in out out M3 M3 = M4 = M4 Wn Ln = 2μ m 0.2 μ m -Vdd Figure 5. The dynamic latch circuit. AYTAR et al./Turk J Elec Eng & Comp Sci In other words, clock ‘0’ means a conversion phase and clock ‘1’ means a sampling phase. The control between the analog and digital parts of the ADC is obtained in this way [1]. In fact, it is not possible to convert an analog input level to its digital value instantly. A very small time period is necessary for the digital part to complete its job. Therefore, a dynamic latch circuit usage is inevitable for a flash ADC design. This time is called the ‘conversion time’, in general, and it is shortest in full-flash ADCs but is very long for the serial type of ADCs. 2.3. The 1-of-N decoder block This decoder block converts the so-called thermometer code (TC) obtained from the outputs of the dynamic latch array to 1-of-N code. In fact, the TC is a good solution for low-resolution and high-speed converters, but the error rate increases while the resolution and speed increases [11]. The multiplexer-based decoder was also proposed in the literature [11]. The 1-of-N decoder structure used in the design is shown in Figure 6. in out 0 0 0 LATCH out 1 clk in out 0 0 LATCH in1 out 1 in2 out 0 in1 0 LATCH out 1 in2 MUX clk in 1 in1 out 0 in2 out 1 in1 out 0 in2 out 1 in1 out 0 in2 MUX 1 out 1 S clk 1 1 S LATCH in out MUX clk 1 MUX out LATCH in out 0 S clk in out 0 S out 1 LATCH 1 MUX S clk in S out 1 in1 out 0 in2 out LATCH MUX 1 clk Figure 6. The conceptual circuit of the 1-of-N decoder block (3-bit case only). 1975 AYTAR et al./Turk J Elec Eng & Comp Sci Figure 7 shows the transmission gate-based multiplexer circuit used in the decoder. In the decoder, 2 × 1 multiplexers are used. The multiplexer inputs are tied to their corresponding latch outputs, where both the normal and inverted forms of the TC segments are available at the same time. Normal latch output terminals are connected to the 1st inputs of the multiplexers, while the inverted outputs are connected to the 2nd inputs. For a specific decoder row, the output of the upper row latch block is also tied to the lower row multiplexer’s select input, as seen in Figure 6. As a result, the TC is converted to 1-of-N code. M1 A M2 out Select M1 B M2 Vdd M1 Select M2 M1 = M2 = Wp Lp Wn Ln = = 6 μm 0.2 μm 2 μm 0.2 μm Figure 7. The 2 × 1 multiplexer circuit. 2.4. Fat-tree encoder structure As is known, the TC is obtained from analog comparator array outputs in flash ADC designs. Programmable logic array–read-only memory, exclusive OR encoder, or Wallace-tree encoder structures are generally used to convert TC to binary code [12,13]. The ADC designs advertised in [12–14] suggest the usage of the fat-tree encoder structure instead, which results in a higher sampling rate and lower power consumption due to a reduction in the number of logic gates required for the digital part of ADCs. Therefore, a fat-tree encoder structure is preferred in our case study, as well, which can be seen in Figures 8a, 8b, and 8c. The OR blocks in our encoder are designed using static CMOS technology. Note that in Figure 8c, the inputs labeled as I0 to I31 are the outputs obtained from the 1-of-N decoder block to be applied to the fat-tree encoder inputs. The inputs in Figures 8a and 8b are connected to the corresponding input/output nodes in Figure 8c. As a result, 5 bits of binary output data from bit0 to bit4 are obtained. 3. Simulation results The Cadence IC5141 design platform and North Carolina State University’s design kit with a 0.18-µ m CMOS library are used during the design and simulations. A ramp-shaped analog input signal of between –0.45 V and 1976 AYTAR et al./Turk J Elec Eng & Comp Sci 0.7 V, at a 10 MHz frequency, is applied to the ADC input for transient analysis. The clock frequency applied to the latch block is 5 Gs/s. Figure 9 shows the DC analysis results and Figure 10 shows the corresponding linearity plots [differential nonlinearity (DNL) and integral nonlinearity (INL)]. To be able to obtain the linearity plots, the DC results are transferred to a MATLAB platform, as used in [15]. a15 a14 a13 b7 b6 a12 b5 b4 a11 a10 b3 b2 a9 a8 bit0 a7 a6 bit1 b1 b0 c3 c2 a5 a4 bit2 c1 c0 a3 a2 d1 d0 a1 a0 bit3 (b) I1 I0 a0 b0 I3 I2 I5 I4 a1 b1 a2 a3 I7 I6 a4 I9 I8 I11 I10 I13 I12 a5 b2 c1 b3 a6 a7 I15 I14 I25 a12 I24 a11 I23 I22 a10 I21 I20 a9 I19 I18 a8 I17 I16 b5 b6 a13 I27 I26 I29 I28 b4 c2 c3 b7 a14 a15 I31 I30 c0 d0 d1 bit4 (a) (c) Figure 8. Fat-tree encoder schematic for the 5-bit case. Figures 11 and 12 show the transient analysis results including DNL and INL plots for a 10-MHz input signal under digital clock frequency of 5 Gs/s. According to the transient simulation results, the worst-case INL is –0.65 least significant bits (LSB) and the worst-case DNL is –0.3 LSB. Moreover, a 5 Gs/s clock is kept constant but the input frequency is changed. The corresponding DNL and INL plots with respect to the input frequency are also examined. In Figures 13 and 14, only the worst-case 1977 AYTAR et al./Turk J Elec Eng & Comp Sci V (mV) linearity error values are plotted for specific frequency values. Additionally, the average current values drawn by the partial system blocks are tabulated in Table 2. As was expected, the largest current is drawn by the comparator block (a total of 31 comparators), which is about 10 mA. Table 3 shows the transistor count of the designed system blocks. Figure 15 shows the reconstructed output signal for an analog ramp input signal without filtering. DC Response 1000 in V (mV) -1000 1000 bit0 V (mV) -1000 1000 bit1 V (mV) -1000 1000 bit2 V (mV) -1000 1000 bit3 V (mV) -1000 1000 bit4 -1000 -1000 -750.0 -500.0 -250.0 0 250.0 dc(mV) (E-3) 500.0 750.0 Figure 9. The 5-bit DC simulation results. DNL [in LSB] INL [in LSB] DNL and INL of 5-bit converter (from histogram testing) 0.1 0.05 0 -0.05 -0.1 0.1 0.05 0 -0.05 -0.1 avg = -2.2e-017, std.dev = 0.014, range = 0.035 5 10 15 bin 20 25 30 25 30 avg = 0.0035, std.dev = 0.012, range = 0.048 5 10 15 bin 20 Figure 10. DNL and INL plots based on the DC simulations. Table 2. The average current values of the partial system blocks. Block name Comparator array Latch array plus 1-of-N decoder Fat-tree encoder block 1978 Current values 9.927 mA 5.291 mA 430.6 µA 1000 AYTAR et al./Turk J Elec Eng & Comp Sci V (mV) V (mV) V (mV) V (mV) V (mV) V (mV) DC Response 1000 in -1000 1000 bit0 -1000 1000 bit1 -1000 1000 bit2 -1000 1000 bit3 -1000 1000 bit4 -1000 -1000 -750.0 -500.0 -250.0 0 250.0 dc(mV) (E-3) 500.0 750.0 1000 INL [in LSB] DNL [in LSB] Figure 11. Binary output data waveforms for fin = 10 MHz ramp input signal. 0.4 0.2 0 -0.2 -0.4 DNL and INL of 5-bit converter (from histogram testing) 0 -0.2 -0.4 -0.6 -0.8 avg = 0, std. dev = 0.095, range = 0.44 5 10 15 bin 20 25 30 25 30 avg = 0.35, std. dev = 0.21, range = 0.66 5 10 15 bin 20 Figure 12. DNL and INL plots for the fin = 10 MHz/fclk = 5 Gs/s. 8 The worst case INL values [LSB] The worst case DNL values [LSB] 2.5 2 1.5 1 0.5 0 6 10 7 10 Analog input frequency [Hz] 8 10 Figure 13. Worst-case DNL errors with respect to the input frequency. 7 6 5 4 3 2 1 0 106 107 Analog input frequency [Hz] 108 Figure 14. Worst-case INL errors with respect to the input frequency. 1979 AYTAR et al./Turk J Elec Eng & Comp Sci 1000 Transient response ideal_dac_out V (mV) 750.0 500.0 250.0 0 -250.0 -500.0 1000 analog_input V (mV) 750.0 500.0 250.0 0 -250.0 -500.0 0 25.0 75.0 50.0 Time (ns) 100 Figure 15. Reconstructed output signal for an analog ramp input signal. Table 3. Transistor count of the designed system blocks. Block name Comparator array Latch array 2 × 1 Mux array Fat-tree encoder Transistor count 403 208 180 336 4. Conclusion In conclusion, a 5-bit 5 Gs/s full-flash ADC was successfully designed in 0.18-µ m CMOS technology using Cadence tools. According to the simulation results, the proposed ADC is highly linear with a worst-case DNL of 0.3 LSB and INL of 0.65 LSB, and it also has a low power consumption value of 28 mW. The performance summary and comparison with similar works in the literature were listed in Table 4. Based on the simulation Table 4. The comparison table. References Technology (CMOS) Resolution Power supply voltage Power (mW) Analog input range Sampling frequency (Gs/s) Max INL (LSB) Max DNL (LSB) Calibration Active chip area (mm2 ) 1980 Proposed 0.18 µm 5-bit ±0.9 V 28 –0.45 V to 0.7 V 5 –0.65 –0.3 No 0.1 [4] 0.13 µm 5-bit 1.2 V 120 0.8 Vpp 3.2 1.13 1.12 Yes 0.18 [16] 0.18 µm 4-bit 1.8 V 4.80 – 0.7 0.27 0.19 Yes – [17] 65 nm 5-bit 1.3 V and 1 V 28.1 0.8 Vpp 5.5 0.33 –0.3 Yes 0.035 [18] 0.18 µm 5-bit 1.8 36 1 Vpp 1.056 0.56 0.32 No – AYTAR et al./Turk J Elec Eng & Comp Sci results, the 2 × 1 Mux-based decoder structure improves the performance in terms of the speed and power consumption. Moreover, it is also thought that the proposed ADC architecture is attractive for designers from a design complexity point of view. The layout photo of the complete converter is shown in Figure 16. As a future work, the performance of the proposed 1-of-N decoder structure will be compared to alternative types of 1-of-N decoder performances. In addition, further improvements are planned in the encoder architecture. Figure 16. The layout photo of the complete converter. 1981 AYTAR et al./Turk J Elec Eng & Comp Sci Acknowledgment This study was financially supported by the Kocaeli University Scientific Research Division under Project Number BAP-2009/40 (Microelectronic Laboratory). References [1] O. Aytar, “Katlamalı ve aradeğerlemeli analog-sayısal dönüstürücülerin VLSI tasarımında eşik evirmeli nicemleyici tekniği’nin kullanımı ve performansı”, PhD, Kocaeli University, İzmit, Turkey, 2009. [2] C.C. Chen, Y.L. Chung, C.I. Chiu, “6-b 1.6GS/s flash ADC with distributed track-and-hold pre-comparators in a 0.18 µ m CMOS”, International Symposium on Signals, Circuits and Systems, pp. 1–4, 2009. [3] L. Wu, F. Huang, Y. Gao, Y. Wang, J. Cheng, “42 mW 2 GS/s 4-bit flash ADC in 0.18 µ m CMOS”, International Conference on Wireless Communications & Signal Processing, pp. 1–5, 2009. [4] Y.Z. Lin, C.W. Lin, S.J. Chang, “5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, pp. 509–513, 2010. [5] S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18 µ m CMOS”, IEEE International Symposium on Circuits and Systems, pp. 6138–6141, 2005. [6] S. Park, Y. Palaskas, M.P. Flynn, “A 4-GS/s 4-bit flash ADC in 0.18 µ m CMOS”, IEEE Journal of Solid State Circuits, Vol. 42, pp. 1865–1872, 2007. [7] K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, M. Segami, “A 7 bit 800 Msps 120 mW folding and interpolation ADC using a mixed-averaging scheme”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 138–139, 2006. [8] C. Chen, J. Ren, “An 8-bit 200 M samples/s folding and interpolation ADC in 0.25 mm 2 ”, Analog Integrated Circuits and Signal Processing, Vol. 47, pp. 203–206, 2006. [9] K. Şahin, O. Aytar, A. Tangel, “5 Bit 2.5 Gs/s paralel (Flash) analog sayısal dönüştürücü tasarımı”, ElektrikElektronik Bilgisayar Sempozyumu, pp. 125–130, 2011. [10] W.S. Chu, K.W. Current, “A CMOS voltage comparator with rail-to-rail input-range”, Analog Integrated Circuits and Signal Processing, Vol. 19, pp. 145–149, 1999. [11] E. Sail, M. Vesterbacka, “A multiplexer based decoder for flash analog-to-digital converters”, IEEE Region 10 Conference , pp. 250–253, 2004. [12] D. Lee, D. Yoo, K. Choi, J. Ghaznavi, “Fat tree encoder design for ultra-high speed flash A/D converters”, The 45th Midwest Symposium on Circuits and Systems, pp. 87–90, 2002. [13] V. Hiremath, S. Ren, “An ultra-high speed encoder for 5GSPS flash ADC”, IEEE International Instrumentation and Measurement Technology Conference, pp. 136–141, 2010. [14] Z. Liu, S. Jia, Y. Wang, Z. Ji, X. Zhang, “Efficient encoding scheme for folding ADC”, 9th International Conference on Solid-State and Integrated-Circuit Technology, pp. 1988–1991, 2008. [15] University of California Berkeley, EECS Instructional and http://inst.eecs.berkeley.edu/ ∼ n247/matlab files/inldnl.m, accessed 6 December 2011. Electronics Support, [16] G. Torfs, Z. Li, J. Bauwelinck, X. Yin, G. van der Plas, J. Vandewege, “Low-power 4-bit flash analogue to digital converter for ranging applications”, Electronics Letters, Vol. 47, pp. 20–22, 2011. [17] W.H. Ma, J.C. Kao, M. Papaefthymiou, “A 5.5 GS/s 28 mW 5-bit flash ADC with resonant clock distribution”, Proceedings of the 37th European Solid-State Circuits Conference, pp. 155–158, 2011. [18] J.X. Ma, S.W. Sin, S.P. U, R.P Martins, “A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications”, International Symposium on Circuits and Systems, pp. 4305–4308, 2006. 1982