Download Indirect Compensation Technique for Low-Voltage

Indirect Compensation Technique for Low-Voltage
CMOS Op-amps
Vishal Saxena
R. Jacob Baker
E.C.E. Dept., University of Texas at Austin
Austin, TX, USA
[email protected]
E.C.E. Dept., Boise State University
Boise, ID, USA
[email protected]
Abstract—Two and three-stage indirect-compensated op-amps
employing split-length composite devices are presented. By
incorporating split-length devices the right-half plane zero
which hampers op-amp performance can be eliminated. Chip
test results indicate significant enhancements in op-amp speed
while reducing power consumption and layout area. Moreover,
these techniques can be used to compensate three-stage op-amps
operating at low supply voltage (VDD).
I.
INTRODUCTION
Two-stage op-amps have been the amplifier topologies of
choice in analog system design due to their simple frequency
compensation and relaxed stability criterions. The two-stage
op-amps have traditionally been compensated using the Miller
(or Direct) compensation technique [1][2]. Miller
compensation achieves dominant pole compensation by pole
splitting due to capacitance multiplication effect. However, the
compensation capacitance (Cc) connected between the outputs
of the first and second gain stages, leads to a right-half plane
(RHP) zero. The RHP zero, located at z1=gm2/CC in the s-plane,
pulls down the phase margin of the op-amp and requires a
larger capacitance to compensate the op-amp. This in turn
results in a reduced unity gain frequency of the op-amp given
by fun=gm1/2πCc [1].
The RHP zero can be eliminated by blocking the feedforward compensation current, while allowing the feedback
component of the compensation current to attain pole splitting.
This can be achieved by several methods including a zero
nulling resistor (RZ) or a voltage buffer in series with the
compensation capacitor in the feedback path [1][4]. A
common-gate stage can also be employed to block the feedforward component of the compensation current while
achieving pole-splitting [3]. Such techniques where the
compensation current is indirectly fed-back are categorized as
indirect compensation. This paper presents a brief description
of indirect feedback compensation and presents the use of
split-length devices for op-amp compensation while operating
at low-VDD.
II.
INDIRECT FEEDBACK COMPENSATION OF OP-AMPS
The class of amplifier compensation in which the
compensation current is fed back indirectly from the output to
the internal high impedance node is defined as Indirect
Feedback Frequency Compensation or simply, indirect
compensation [1], [5]. Here, the compensation capacitor is
connected to an internal low impedance node in the first stage,
which allows indirect feedback of the compensation current
from the output node to the internal high-impedance node i.e.
the output of the first stage. The dominant pole location for the
indirect compensated op-amp is same as in Miller
compensation. However, instead of a RHP zero we now have
a LHP zero located at z1=gmc/(CC+CA), where gmc is the
transconductance of the common-gate device and CA is the
capacitance attached to the low-impedance node A. The nondominant pole location is given by p2=-gm2CC/(C1CL). Also
there exists a third parasitic pole arising due to the loading of
the low impedance node-A [4].
VDD
VDD
VDD
VDD
M4T
M3T
A
Vbias2
M3B
VDD
Vbias1
ic
M4B
VDD
M4
VDD
M3
M4
M7
1
M7
220/2
110/2
1
vm
M1
M1T
vp
M2
CC
1.5pF
M6TL
M6BL
Vbias3
M6TR
M8T
M6BR
M8B
vout
2
M2T
A
vm
M1B
10/10
M2B
Vbias3
50/2
Vbias4
(a) Cascoded current mirror load
1.5pF
30/2
M8T
30/2
M5B
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
vp
vout
2
ic
50/2
M5T
Vbias4
CC
M8B
100/2
100/2
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
(b) Cascoded Diff-pair
Figure 1. Indirect compensated two-stage op-amps using cascode common
gate device. The compensation capacitor, Cc, in each of the op-amps is
connected to the the low impedance node A [1][4].
We can discern that when using indirect compensation, the
second pole, p2, is pushed further away from the dominant
pole, p1, by a factor of approximately CC/C1. Hence, pole
splitting can be achieved with a lower value of the
compensation capacitor CC and/or with a lower value of gm2.
This results in a significantly higher unity-gain frequency
attainable by the op-amp. Also the LHP zero adds to the phase
in the vicinity of the unity gain frequency, fun, and improves
the phase margin [1][2]. Figure 1 shows two-stage op-amp
topologies where indirect compensation is achieved by using
the “embedded’ common-gate device in the cascode structure
[4].
III.
INDIRECT COMPENSATION USING SPLIT-LENGTH
COMPOSITE TRANSISTORS
Indirect-compensated two-stage op-amps can be designed
by employing the internal low impedance nodes available in a
cascode topology to feedback the compensation current [1].
However, with continual scaling of supply voltage (VDD)
cascoding may no longer be an option in the sub-100nm
CMOS processes [6]. A suitable technique for low VDD design
which employs a split-length composite transistor for indirect
compensation, proposed in [1]&[5], is analyzed in this section.
Figure 2 illustrates splitting of an NMOS or a PMOS to
create a low impedance node-A. For a composite NMOS, the
lower device, M1B, operates either in cut-off or triode region
but never in saturation. Since a triode device offers a low
channel resistance and also that node-A is connected to the
source of M1T, the node-A is a low impedance node. Similar
argument holds for the PMOS composite device [1].
In order to simplify the small signal analysis of this opamp topology, few assumptions have been made. The
transconductance of each of the split PMOS devices is
denoted as gmp. The resistance, RA, can be approximated to be
equal to the channel resistance of the trioded PMOS, which is
close to 1/gmp. Also, here if the current mirror load is designed
with the same gm as the diff-pair, we have g mp = 2 g m1 . The
simplified small-signal model for SLCL op-amp is shown in
figure 4 [7].
1
gmp
gm1vs
2
−
1
gmp
g m1
v
gmp s
Figure 4. Small signal model for analysis of the two-stage op-amp
employing split length load devices [7].
On applying nodal analysis on the small signal model
shown in figure 4, we obtain a dc gain of − gm1 R1 gm2 R2 and a
unity gain frequency equal to
gm1
2π (2CC )
The dominant pole is given as
f un =
p1 ≈ −
(1)
1
(2)
2 g m2 R2 R1CC
The LHP zero is located at
Figure 2. Illustration of the split-length composite NMOS and PMOS
devices [1].
A. Split length current mirror load (SLCL)
Figure 3 exhibits a two-stage op-amp with a split-length
current mirror load (SLCL) topology. The compensation
capacitor is connected to the internal low impedance node-A
to achieve indirect compensation.
z1 ≈ −
a
4 g mp
3 CC + C A
4 2 g m1
f = − 3aC
C
+ CA
f≈
8 2
3
ω un
(3)
The non-dominant poles are approximated by
p2 ≈ −
g m 2 CC
2C1C L
(4)
d
i
p3 ≈ − 2 g mp C2 || CC + 1 R1 || rop C1
(5)
Figure 5. Simulated frequency response of the indirect compensated opamp
with split-length current mirror load (SLCL). Here fun=20MHz and PM=80°.
Figure 3. A two-stage op-amp with indirect feedback compensation using
split-length load composite devices [1][5].
SPICE simulated frequency response for this op-amp is shown
in figure 5. This op-amp exhibits a unity gain frequency of
20MHz, a phase margin of 75° and a transient settling of 60ns.
B. Split length differential pair (SLDP)
Figure 6 shows the proposed two-stage op-amp topology
where a split-length diff-pair (SLDP) is used for indirect
compensation. This topology exhibits better power supply
rejection ratio (PSRR) since the node used for compensation
(node A) is isolated from the supply rails and lesser supply
noise is leaked to the output.
margin of the op-amp. However, in the case of SLDP we do
not have such convenience and it might be hard to obtain
desirable phase margins with the SLDP topology. But the
SLDP indirect compensation topology is of great utility when
designing multi-stage indirect compensated op-amps
described in [6].
IV.
INDIRECT COMPENSATION OF THREE STAGE OP-AMPS
The SLCL and SLDP indirect compensation techniques
shown in the last section form the basis for low-voltage opamp compensation. However, one may argue that the op-amp
gain is sacrificed by avoiding cascoding. But, since cascoding
may no longer be viable due to supply voltage (VDD) scaling
and relatively fixed threshold voltages (VTH). Thus the
paradigm of cascoding needs to be traded with cascading of
low-voltage stages to design high-gain op-amps in nanoCMOS. Also since the intrinsic gain of the transistors (gmro)
has been dropping with continued scaling, use of at least three
stages is inevitable for op-amp design in nano-CMOS.
Figure 6. An indirect compensated two-stage op-amp employing splitlength diff-pair.
Small signal analysis of this topology again yields the
same non-dominant poles and zero locations as in the splitlength current mirror load case. However, the unity gain
frequency is now estimated by
f un =
2 g m1
(6)
2πCC
Thus the LHP zero can now be expressed as
z1 ≈ −
a
4 g mn
3 CC + C A
4 2 g m1
f = − 3aC
C
+ CA
f≈
2 2
3
ω un
(7)
which implies that the LHP zero is located at a lower
frequency than the unity gain frequency. This has the effect of
flattening the gain magnitude response which may degrade the
phase margin of the op-amp. The SPICE simulated frequency
response for this op-amp is shown in figure 7. This op-amp
exhibits a unity gain frequency of 35MHz, a phase margin of
62° and a transient settling of 75ns [7].
Figure 8. A low-VDD class-AB three-stage op-amp employing reversed
nested indirect compensation (RNIC).
Figure 8 presents a three-stage op-amp operating at a
supply voltage of 2.5V, designed by cascading three low-VDD
gain stages. A PMOS diff-amp is used in the second stage to
precisely set the bias level for the third common-source stage
and also for providing higher CMRR. The third stage is biased
in a class-AB fashion such that the gates of M10 and M11
move together and one of the devices is shut-off while driving
the load. Note the way in which the compensation currents are
indirectly fed-back to node-1 from nodes 2 and 3.
Figure 7. Simulated frequency response of the indirect compensated opamp
with split-length diff-pair (SLDP). Here fun=35MHz and PM=60°.
In the case of SLCL indirect compensation, we have the
flexibility of varying gmp independent of gm1 in order to
control the location of the LHP zero and hence the phase
Figure 9. Simulated frequency response of the indirect compensated threestage opamp (RNIC). Here fun=20MHz and PM=76°.
This compensation scheme leads to two LHP zeros besides
a dominant pole and two non-dominant poles. The two LHP
zeros counter the two non-dominant poles and help improve
the phase margin. The low impedance internal nodes fbl and
fbr also lead to two parasitic poles at higher frequencies,
which are close to the fT limited poles (or mirror poles) and
can be ignored. Detailed analysis for this three-stage topology
is provided in [6]. Thus incorporation of indirectcompensation in three-stage op-amps leads to lower power,
simple and manufacturable topologies as shown in figure 8.
V.
CHIP TEST RESULTS AND PERFORMANCE COMPARISON
The test chip, designed using AMI’s C5N (0.5µm) process,
includes Miller compensated op-amps with and without the
zero nulling resistor and the SLCL, SLDP & RNIC indirect
compensated op-amp topologies (see figure 10).
operating at 50% of the supply voltage and occupying the
same layout area as the corresponding two-stage op-amps.
TABLE I. PERFORMANCE COMPARISON OF THE OPAMPS FOR CL=30PF.
Op-amp
Topology
ADC
(dB)
fun
(MHz)
CC
(pF)
PM
ts
(ns)
Power
(mW)
Miller
Miller
with RZ
SLCL
(this work)
SLDP
(this work)
RNIC
(this work)
57
57
2.5
2.7
10
10
74°
85°
270
250
1.2
1.2
Layout
area
(mm2)
0.031
0.034
66
20
2
80°
60
0.7
0.015
60
35
2
60°
75
0.7
0.015
89
20
1.5,
1.5
76°
60
1.4
0.017
VI.
CONCLUSION
Indirect feedback compensation technique applied to twostage and three-stage op-amps using split-length transistors
has been presented. The chip test results demonstrate that the
indirect feedback compensation employing split-length
devices leads significantly faster, lower power op-amps with
smaller layout footprint when compared to the traditional
Miller compensation. These indirect compensated topologies
are suitable for op-amp design in nano-CMOS processes.
ACKNOWLEDGMENT
The authors are grateful to the MOSIS educational
program for supporting this project.
REFERENCES
[1]
[2]
[3]
Figure 10. Microphotograph of the test chip showing the fabricated two and
three stage op-amps.
A performance comparison of the op-amp topologies
fabricated on the test chip is presented in Table 1. The chip
test results exhibit that the indirect-compensated two-stage opamps exhibit nearly ten times improvement in the gain
bandwidth (fun) and four times faster transient settling when
compared to the Miller compensated op-amps. Also the
indirect compensation results in 40% reduction in power and
50% reduction in the layout area of the two-stage op-amps.
Further, the proposed three-stage topology leads to around 26
dB higher gain with almost the same unity-gain frequency (as
SLCL op-amp) by consuming only 20% more power while
[4]
[5]
[6]
[7]
R. J. Baker, CMOS: Circuit Design, Layout and Simulation, 2nd ed.,
Wiley-IEEE, 2005.
P.R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, “Analysis and design
of Analog Integrated Circuits,” 4th ed., John Wiley & Sons, 2001.
B. K. Ahuja, “An Improved Frequency Compensation Technique for
CMOS Operational Amplifiers,” IEEE Journal of Solid-State Circuits,
vol. 18, pp. 629-633, Dec. 1983.
P. J. Hurst, S. H. Lewis, J. P. Keane, “Miller Compensation Using
Current Buffers in Fully Differential CMOS Two-Stage Operational
Amplifiers,” IEEE Tran. on Circuits and Systems I- Regular Papers,
vol. 51, no. 2, Feb. 2004.
V. Saxena, R. J. Baker, “Indirect Feeback Compensation of CMOS OpAmps,” proceedings of the IEEE/EDS WMED, pp. 3-4, April, 2006.
V.Saxena, “Indirect Feedback Compensation Techniques for MultiStage Operational Amplifiers,” Masters Thesis, Boise State University,
Oct 2007.
V.Saxena, R.J. Baker, “Compensation of CMOS Op-amps using SplitLength Transistors,” submitted to IEEE International MWSCAS, Aug
2008.