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COEN6511 LECTURE 4 NOISE MARGIN Inverters are usually made up of transistors which are themselves based on semiconductor materials. The material and the transistors and consequently the gates are affected by change in voltage, temperature and process variation. These changes lead to uncertainties in performance. The best logic family is the one that is immune to mentioned variation. Also, it is ideal that the logic family characteristics is not affected by the choice of the design parameters drastically to be non functional. Looking back at the inverter, when driving a load, we need to have some tolerance in the voltages corresponding to a logic ‘1’ or logic ‘0’. Noise margin: What is considered to be high or low at Vout from one stage should be considered valid as input by another stage. NM NM L VIL ( MAX ) VOL( MAX ) H VIH ( MIN ) VOH ( MIN ) Page 1 of 12 Lecture#4 Overview If we do the mathematical analysis, 1 V OUT at point A where PMOS is in saturation and NMOS is in linear region V IN Similarly, 1 V OUT at point B where PMOS is in linear and NMOS is in saturation region. V IN For a given (5 V Vdd) and after manipulation, we obtain: NM V V L IL( MIN ) OL( MAX ) NM L NM H NM V H 3V DD 3V 3V TP TN 8 IH ( MAX ) 3V DD V OH ( MIN ) 5V 3V TP TN 8 Design Guidelines: Usually we like to have VIH=VIL and half way through the characteristic. This is to say that we should have fast and abrupt switching. Keep r=1. \ Page 2 of 12 Lecture#4 Overview NON-RATIOED LOGIC – CMOS In standard CMOS when we change r the characteristic curve is shifted right or left but we always get rail to rail switching as shown in the figure below; However depending on the load condition several classes of logic families exist that the Voltage output in particular VoL depends on the ratio of the pull up to the pull down devices. These are called ratioed logic and we will review one such logic family called pseudo-nmos. Page 3 of 12 Lecture#4 Overview PSEUDO-NMOS The VTC of this inverter is shown above. When Vin = 0V, NMOS is off, PMOS is on and the output node is connected to VDD. However when Vin is VDD we have a different scenario. Using the following resistive model, Let us look at this inverter: V OUT V DD R 2 R R 1 2 1 Let R R 1 2 V OUT V DD 2 Not an acceptable logic level! The W/L ratio affects the behavior of the circuit and hence changes Vout as well. When Vin = Vdd, NMOS is on, PMOS is also on. Let us have a closer look: NMOS is in linear region as Vds<Vgs-Vt while PMOS is in the saturation region. Page 4 of 12 Lecture#4 Overview Equating the current in both transistors we get: p Vdsn ] [Vgsp Vtp ]2 2 2 Replacing in equation above Vgsn VDD , Vgsp VDD , Vdsn VO , Vt 0.2VDD , Vp VO .VDD I D n [(Vgsn Vtn )Vdsn 2 n [(V DD 0.2V DD )VO ] 2 n p p 2 [V DD 0.2V DD ] 2 [(V DD 0.2V DD )VO ] [V DD 0.2V DD ]2 p [0.8V DD ] 2 VOL 2 n 0.8V DD p VOL 0.8V DD 2 n VOL p 0.4VDD n WP 2 LP * 0.4VDD W N Cox N 2 LN P Cox VOL Assume CoxN CoxP and LP LN Now VOL PWP * 0.4VDD N WN VOL WP * (0.4 / 3)VDD WN N 3 P For VoL to be valid, VOL Vtp or Vtp If we assume VOL to be approximately Vtn/2, say 0.3V then, for VDD=3.3V W 0.3V P * (0.4 / 3)VDD ,VDD 3.3V WN 0. 3 Then WP / WN 1.1 * 4 Page 5 of 12 Lecture#4 Overview Both transistors have to meet the minimum criteria for design rule. W Choose P to the correct ratio and verify that WP and WN are greater than W MIN . WN In this case, we can keep WP to a minimum and increase WN to the appropriate ratio, assuming that both Lengths are equal. Alternatively if the speed is not an issue, then we can increase LP which would imply increasing resistance of the transistor, but will have the same effect on r, ie keeping VOL p 0.4VDD . n Generally we can follow the following model for Vol Vol = (VDD Vt ) {1- ( 1 ( p / n ) )0.5} assuming Vt=Vtn=│Vtp│ Page 6 of 12 Lecture#4 Overview TRANSMISSION GATE (TG) CIRCUITS Example of circuit voltages: Vg=5V, Vtn=0.7V ( Drain and Source are defined after applying the voltage) Example of voltage estimates at Source of NMOS for various voltages at the Drain (Vtn = 0.7V). Vin(V) 1 2 3 4 5 Vout(V) 1 2 3 4 4.3 As noticed from the table, an NMOS TG is not a good transmitter of logic ‘1’ (high) signals. Similarly, for PMOS circuits, ( Drain and Source are defined after applying the voltages) Vin(V) 5 4 3 2 1 0 Vout(V) 5 4 3 2 1 0.7 The PMOS is not a good transmitter of logic ‘0’ signal. To remedy the problem we put a pair of PMOS and NMOS transistor in parallel. Page 7 of 12 Lecture#4 Overview CMOS TRANSMISSION GATE The above circuit passes low as well as high level signals without any loss in the output level voltage. Page 8 of 12 Lecture#4 Overview RESISTANCES AND CAPACITANCES We have two types of resistors and capacitors in a VLSI circuit; useful and parasitic. RESISTANCE DESIGN Resistance R * L L * A W *T What are the parameters that we have control over? W, L and some control of . Different resistivity, , is achieved by using diffusion, metal, poly, N-Well and P-Well materials. for a given material is constant and is T commonly called the sheet resistance Rs of a material. L R Rs * W Since thickness is process dependent then Now, if L=W, as with the case of a square shape, then R= Rs . In the above diagram both squares have the same resistance. R is then measured as / Page 9 of 12 Lecture#4 Overview Example of measuring resistance with the help of square shapes. For irregular width, R_corner = Rs (0.46+0.1a) where a = W1/W2 Other factors:- Variation in resistivity across the resistor depth and Temperature, Voltage and process variations may affect the total resistance. Resistor values are a function of teperature R(T ) Ro [1 TC1 * dT TC 2 * dT 2 ] , dT = T – Tnominal at 25* Celcius Constants taken from the process manual The resistance is layout dependent and is calculated from sheet resistance L , w is the width of the drain & w is the process variation factor. R( L) RS * ( w w) The resistance values are a function of the voltage R(V ) RO [1 VC * dV VC 2 dV 2 ] Constants taken from the process manual Page 10 of 12 Lecture#4 Overview STRUCTURAL OVERVIEW OF A RESISTANCE AND ITS ASSOCIATE PARASITIC RESISTANCES For each metal, Rc is the contact resistance, and is measured as Rc/Area. Typical resistance values. For 0.5u process: Values are per square N+ diffusion : 70 P+ diffusion : 140 Polysilicon : 12 Polycide:2-3 / / / / M1: 0.06 / M2: 0.06 / M3: 0.03 / P-well: 2.5K / N-well: 1K / Active resistors These resistors are made with transistors. The resistors are made up from two components: 1) Drain/ Sources Resistance: RD(S) = Rsh * no. of squares + contact resistance. Page 11 of 12 Lecture#4 Overview RCH = -------------------------------1 --------------------------------- ' W K' ----- VGS – VT –V DS L 2) Channel Resistance: This depends on the region of operation: RC H = -------------------------2 --------------------------2W K' ----V – VT L GS Contact resistance: The contact resistance Rc is defined as Rc= c/A where c is the specific contact resistance and A is the contact area. Smaller contacts of higher impurities will increase the resistance. Rc assumes that the current through the contact flows uniformly. However, there is a current crowding phenomena around the corners and leading edges of the contact. Typical Contact resistance values for 0.5m process: Contact resistance: PolyI to MetalI Via resistance: Metal I to Metal II Via resistance: Metal II to metal III Contact resistance: PolyI to MetalI Via resistance: Metal I to Metal II Via resistance: Metal II to metal III 50 1.5 1. 50 1.5 1. Tips for the lab. Download www.cygwin.com and install cygwin if you want to access the Cadence VLSI design suite from home. SSH to any UNIX server, such as dea.ece.concordia.ca End of lecture #4 Page 12 of 12 Lecture#4 Overview