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DESIGN OF LOGIC FAMILIES Some desirable characteristics to have: 1. Low power dissipation 2. High noise margin (Equal high and low margins) 3. High speed 4. Low area 5. Low output resistance 6. High input resistance 7. Reliability, Ease for testing 8. Low cost 9. High fan-out 10. Low fan-in Other important factors are: 1. 2. 3. 4. 5. Single power supply System must have regenerative property System must possess directivity Circuit functionality does not depend on design parameters Rail-to-rail output switching Regenerative Property Directivity Property Page 1 of 17 Lecture#3 Overview Change needs to be propagated in one direction only. This is very difficult to achieve as there is always coupling and feedback. We will be looking for a circuit with minimum feedback or coupling in the system. IDEAL INVERTER VOLTAGE TRANSFER CHARACTERISTIC (VTC) REAL INVERTER VTC Page 2 of 17 Lecture#3 Overview Inverters An inverter can be built with an nMOS and either a resistor, nMOS, nMOS Depletion or a pMOS transistor. Resulting inverter has different characteristics depending on type of load. In our work although we touch on other type of inverters however our focus will be on CMOS inverter, using the pMOS as a load. Load CMOS INVERTER ( Static Characteristic) AND NON_RATIOED LOGIC A CMOS inverter has the following attributes: Simple circuit and hence has minimum silicon area Input to inverter is a capacitance, so practically no current flows in or out of the inverter terminals. The inverter is in a steady state most of the time and as such draws minimum power It has well defined Vout levels Page 3 of 17 Lecture#3 Overview Regions of operation of the inverter: In the steady state regions one of the transistors is off, hence no direct path between Vdd and ground exist as shown below. Page 4 of 17 Lecture#3 Overview In region A, pMOS is in the linear region while nMOS is cut off. Current will not flow to ground but the pMOS is “ON” giving full Vdd at the output. Vout=Vdd. In region B, pMOS is in the linear region while nMOS is in saturation: I D N SAT n 2 Page 5 of 17 [Vgs Vt ] 2 ignoring modulation effect. Lecture#3 Overview p I dsp 2 n I dn [(Vin VDD Vtp )(Vo VDD ) (Vo VDD )2 ] 2 [V gs Vtn ] 2 2 Also Idn = - Idp Equate the two and solve for Vo Vo (Vin Vtp ) (Vin Vtp ) 2 2(Vin V DD Vtp )V DD n (Vin Vtn ) 2 2 p Can be changed as design parameter In region C, Both NMOS and PMOS are in saturation. I dn n [(Vin Vtn )]2 2 p I dp [(Vin VDD Vtp )]2 2 Idn= -Idp , equating and manipulating V DD Vtp Vtn Vin 1 n p n p To obtain the best switching point, the gate threshold voltage (Vin=Vout at VTC) has to be Vdd/2 If n =1, then Vin = Vdd/2. This is our design criterion p hence, manipulating the expression to obtain design parameters Wn and Wp: Wn Ln 1 , Assume Ln=Lp, Coxn= Coxp Wn p Cox Lp n Cox Page 6 of 17 Lecture#3 Overview p 1 N n wn w , 3.1 for CMOSIS 4B 1 or n wp n 3 P p wp Generally, let µR = µN/ µP, then Wp= µR WN Conclusion: This means that we need to make Wp µR times greater than Wn to get switching around Vdd/2. In practice, we use Wp = 2 Wn. (Due to saving in area and also due to the fact that the variation of VTC around Vin is not much.). Making Bn > Bp the VTC curve moves to the left and vice versa as shown below: Page 7 of 17 Lecture#3 Overview EFFECT OF TEMPERATURE An increase in temperature results in a decrease in mobility and a drop in current. I D T 1.5 An increase in temperature results in a decrease of the Threshold Voltage Vt. Increase in Temp. Page 8 of 17 Lecture#3 Overview NOISE MARGIN Inverters are usually made up of transistors which are themselves based on semiconductor materials. The material and the transistors and consequently the gates are affected by change in voltage, temperature and process variation. These changes lead to uncertainties in performance. The best logic family is the one that is immune to mentioned variation. Also, it is ideal that the logic family characteristics is not affected by the choice of the design parameters drastically to be non functional. Looking back at the inverter, when driving a load, we need to have some tolerance in the voltages corresponding to a logic ‘1’ or logic ‘0’. Noise margin: What is considered to be high or low at “Vout” from one stage should be considered valid as input “Vin” by another stage. NM NM L VIL ( MAX ) VOL( MAX ) H VIH ( MIN ) VOH ( MIN ) Page 9 of 17 Lecture#3 Overview If we do the mathematical analysis, 1 V OUT at region D(infliction point) where pMOS is in saturation and nMOS is V IN in linear region Similarly, 1 V OUT at region B (infliction point) where pMOS is in linear and nMOS is in V IN saturation region. For CMOS usually VOLmax is close to 0 and VOHmin is close to VDD. To determine either VILmax or VIHmin we make use of several equations including dVo/dVi = −1, In= −Ip, W 1 2 V V V VDS GS tn DS L 2 nMOS in linear region 1 W VGS Vtn 2 1 VDS K 'n 2 L nMOS in Saturation region W 1 2 K 'P VGS Vtp . VDS VDS L 2 pMOS in Saturation region I DS K 'n I DS I DS 2 1 W K 'P VGS Vtp 1 VDS 2 L pMOS Saturation region To determine VILmax we know nMOS is in Saturation and pMOS is in the linear region, while determining VIHmin, PMOS is in the saturation while nMOS is in the liner region. I DS For a given (say Vdd=5V) and after manipulation, we obtain: NM L V NM L Page 10 of 17 IL(MAX ) 3V DD V OL(MAX ) 3V 3V TP TN 8 Lecture#3 Overview NM H NM V H IH (MIN ) 3V DD V OH (MIN ) 5V 3V TP TN 8 Design Guidelines: Usually we like to have VIH=VIL and half way through the characteristic. This is to say that we should have fast and abrupt switching. Keep r=1. \ Page 11 of 17 Lecture#3 Overview NON-RATIOED LOGIC – CMOS In standard CMOS when we change r the characteristic curve is shifted right or left but we always get rail to rail switching as shown in the figure below; However depending on the load condition several classes of logic families exist that the voltage output in particular VoL depends on the ratio of the pull up to the pull down devices. These are called ratioed logic and we will review one such logic family called pseudo-nMOS. Page 12 of 17 Lecture#3 Overview PSEUDO-NMOS, NON –Ratioed Logic The VTC of this inverter is shown above. When Vin = 0V, NMOS is off, pMOS is on and the output node is connected to VDD. However when Vin is VDD we have a different scenario. Using models, Let us look at a resistive model of this inverter: V OUT V DD R 2 R R 1 2 1 Let R R 1 2 V OUT V DD 2 Not an acceptable logic level! The W/L ratio affects the behavior of the circuit particularly changes Vout. When Vin = Vdd, NMOS is on, pMOS is on and let us have a closer look: nMOS is in linear region as Vds<Vgs-Vt while pMOS is in the saturation region. Page 13 of 17 Lecture#3 Overview Equating the current in both transistors and please notice the simplification of Vt = 0.2 VDD we get: p Vdsn ] [Vgsp Vtp ]2 2 2 Replacing in equation above Vgsn VDD , Vgsp VDD , Vdsn VO , Vt 0.2VDD , Vp VO .VDD I D n [(Vgsn Vtn )Vdsn 2 n [(V DD 0.2V DD )VO ] 2 n p p 2 [V DD 0.2V DD ] 2 [(V DD 0.2V DD )VO ] [V DD 0.2V DD ]2 p [0.8V DD ] 2 2 n 0.8V DD p VOL 0.8V DD 2 n VOL p 0.4VDD n VOL WP 2 LP * 0.4VDD WN N Cox 2 LN P Cox VOL Assume CoxN CoxP and LP LN Now VOL PWP * 0.4VDD N WN VOL WP * (0.4 / 3)VDD WN N 3 P For VoL to be valid, VOL Vtp or Vtp If we assume VOL to be approximately Vtn/2, say 0.3V then, for VDD=3.3V Page 14 of 17 Lecture#3 Overview WP * (0.4 / 3)VDD ,VDD 3.3V WN 0.3 Then WP / WN 1.1 * 0.4 Or WN ≈ 1.5 WP for our process, respecting WP,min 0.3V Both transistors have to meet the minimum criteria for design rule. W Choose P to the correct ratio and verify that WP and WN are greater than W MIN . WN In this case, we can keep WP to a minimum and increase WN to the appropriate ratio. Alternatively, we assume that both Ls are equal and if the speed is not an issue, then we can increase LP which would imply increasing resistance of the transistor. Page 15 of 17 Lecture#3 Overview TRANSMISSION GATE (TG) CIRCUITS Example of circuit voltages: Vg = 5V, Vtn = 0.7V Example of voltage estimates at Source of NMOS for various voltages at the Drain (Vtn = 0.7V). Vin(V) 1 2 3 4 5 Vout(V) 1 2 3 4 4.3 As noticed from the table, an NMOS TG is not a good transmitter of logic ‘1’ (high) signals. Similarly, for PMOS circuits, Vin(V) 5 4 3 2 1 0 Vout(V) 5 4 3 2 1 0.7 The PMOS is not a good transmitter of logic ‘0’ signal. To remedy to the problem we put a pair of PMOS and NMOS transistor in parallel. Page 16 of 17 Lecture#3 Overview CMOS TRANSMISSION GATE The above circuit passes low as well as high level signals without any loss in the output level voltage. Page 17 of 17 Lecture#3 Overview