Download CMOS Transmission Gates

ESE319 Introduction to Microelectronics
CMOS Transmission Gates
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
1
ESE319 Introduction to Microelectronics
Non-negligible Body Effect
NMOS Devices
Body and
source connected
to most negative
voltage, i.e. VSB = 0.
Body effect is
negligible.
PMOS Devices
Only body
Body and
connected
source connected
to most negative to most positive
voltage i.e. VSB ≠ 0. voltage i.e. VSB = 0.
Body effect is
Body effect is
non-negligible.
negligible.
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
Only body
connected
to most positive
voltage i.e. VSB ≠ 0.
Body effect is
non-negligible.
2
ESE319 Introduction to Microelectronics
Non-negligible Body Effect
When VSB ≠ 0 causes the electric field in the vicinity of the
channel to change. (See S&S p 258.) The channel depth is
decreased, increasing the threshold voltage:
V t =V t0    2 f V SB−  2  f 
Vt0 is the zero diode value of Vt, VSB is the back voltage
across the diode and =GAMMA and 2 F =PHI are
process dependent parameters.
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
3
ESE319 Introduction to Microelectronics
Pass Transistor Logic
Transistors are used as switches: two in series form a 3 input AND gate,
while two in parallel, with input “A” held HIGH form a 2 input OR gate.
Y = ABC
Y = A BC 
Note:
1. Inputs “B” and “C” drive the gates of transistor switches.
2. The inputs can be either a variable or a constant HIGH or
LOW quantity.
3. A low resistance to ground is required to obtain LOW output “Y”
when required.
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
4
ESE319 Introduction to Microelectronics
vI HIGH and nMOS Switch Closed
v G =V DD
vI
vo
D
v I =V DD
v O =0 @ t=0
S
Source and drain terminals
depend on relative values
of vI and vO. Note that the
source voltage is equal to
the body voltage only when
vI or vO is 0 V.
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
Switch closed at t = 0:
v G =V DD
v S =v O =0
v D =v i =V DD
v I v O
v DS =v GS =V DD−v O v GS −V tN
nMOS in Sat. mode as C charges
2
1
i D = k n  V DD −v O −V tN 
2
v O V DD −V tN ⇒ v GS =V DD −v O V tN
nMOS in Cutoff when vO > VDD - VtN
5
ESE319 Introduction to Microelectronics
vI HIGH and nMOS Switch Closed
v G=V DD
vI
vo
D
v I =V DD
v O=0 @ t=0
S
2
1
i D = k n  V DD −v O −V tN 
2
V SB =v O ≠ 0
VtN is body-effect dependent:
Two problems:
1. VtN increases with increases in source
(capacitor) voltage.
2. nMOS stops conducting when:
v O V DD −V tN
Hence, the HIGH vO < VDD!
This lower VOH can pose noise-margin
problems if CMOS stages follow.
V tN =V t0N  N   2  fN V SB − 2  f 
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
6
ESE319 Introduction to Microelectronics
vI LOW and nMOS Switch Closed
v G=V DD
vI
vO
S
v I =0 V
v O =V DD @ t=0
D
Switch closed at t = 0:
v D =v O =V DD
v S =v I =0
v G =V DD =v GS =V DD V tN
v DS =v O −v I =v O =V DDv GS −V tN
V SB =v I =0V ⇒V tN =V t0N
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
Hence, nMOS in Sat. initially:
2
1
i D = k n  V DD −V t0N 
2
Capacitor C is discharging, so
eventually,
v DS =v ov GS −V t0N
And discharging continues with
nMOS in Tri.
1. Since the vGS always exceeds
Vt0N, C will fully discharge to vO = 0 V.
2. Since VSB = 0, there is no body
effect!
7
ESE319 Introduction to Microelectronics
vI HIGH CMOS Transmission Gate
Previous nMOS analysis holds
(drain (D) on left).
D
S
vo
vI
v I =V DD
S
v O=0 @ t=0
D
Capacitor C charges vO -> VDD
pMOS device has source (S) on
left and:
V S =V DD =V B ⇒∣V tP∣=∣V t0P∣
VSB = 0; hence there is no pMOS
body effect!
nMOS is ON 0V ≤ vO < VDD - VTN
v SG =V DD−0∣V tP∣ for 0V ≤ vO ≤ VDD
pMOS is ON 0V ≤ vO > VDD
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
8
ESE319 Introduction to Microelectronics
vI LOW CMOS Transmission Gate
S
D
vo
vI
VSB = vO – VDD =>there is a pMOS
body effect and VtP ≠ Vt0P!
VSB = vI = 0V =>there is no nMOS
body effect and VtN = Vt0N!
nMOS: v O =0 @ t =0
v I =0V
nMOS is ON 0V ≤ vO ≤ VDD
D
S
v O =V DD @ t=0
Capacitor C discharges vO -> 0 V
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
pMOS: V SG =v O−0∣V tP∣
for∣V tP∣vO ≤ V DD
pMOS is ON |VtP| < vO > VDD
9
ESE319 Introduction to Microelectronics
CMOS Transmission Gate
vI = VDD
vI
vO
vDSN > vGSN – VtN vDSN > vGSN – VtN vGSN < VtN
vSDP > vSGP – |VtP| vSDP < vSGP – |VtP| vSDP < vSGP – |VtP|
VtN
|VtP|
vO
vI = 0 V
nMOS: LIN
pMOS: OFF
nMOS: LIN
pMOS: SAT
nMOS: SAT
pMOS: SAT
vDSN < vGSN – VtN vDSN < vGSN – VtN vDSN > vGSN – VtN
vSGP < |VtP|
vSDP > vSGP – |VtP| vSDP > vSGP – |VtP|
|VtP|
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
VtN
vO
10
ESE319 Introduction to Microelectronics
CMOS Transmission Gate ON-Resistance
rDSN
vI = VDD
v O =0@ t=0
rDSP
rDSN
rDSP
rDSN
rDSP
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
11
ESE319 Introduction to Microelectronics
RON-SW
vI = VDD
rDSP
rDSN
v O =0@ t=0
RTOT = rDSN || rDSP
vo
© 2006 Philip V. Lopresti (update 07Nov07 KRL)
12