Download Logic Families

Logic Families
C.K. Ken Yang
UCLA
[email protected]
Courtesy of MAH,JR
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Overview
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•
Reading
– Rabaey 6.2 (Static),
– W&H 6.2.1-5
Overview
– This set of notes cover in greater detail Static Logic Families.
Since Static CMOS and Pseudo-NMOS were previously
discussed, we focus the static logic section on various passtransistor logic families.
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Designing Advanced Circuits
•
There are intrinsic tradeoffs between
– Performance (delay)
– Power
– Noise margin
– Layout area
– Complexity / design time (time to market)
– Robustness
• Will it work across variations in process and environment?
Process scaling? Noisy environment?
•
•
•
Usually forced to use the more advanced techniques in the
critical areas of the design (e.g. custom datapaths)
Tradeoff is speed, area, power vs. design time
You’re fighting against I = C dV/dt
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Design Considerations
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Noise sensitivity
– What is the impedance at each node?
– How easy is it to inject noise?
– How close to the “onset of failure” is each node operating?
– Charge sharing in real circuits due to parasitic caps
Timing requirements (we will revisit later when we talk about clocking)
– Number of clocks
– Critical races
Manufacturability and portability
– Do you require control of 2nd order process parameters?
• Well resistors, lateral diodes, etc.
– Will it work after shrink?
• Shrink gives both performance enhancement and cost reduction
•
Reliability
– Are devices operating outside their normal range (bootstrapping)?
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Static CMOS Logic Families
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Static CMOS Families Outline
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Static CMOS
– We knows this one well… so
skip it.
Pseudo-NMOS
– Power hungry but very good for
ORing structures.
– You can turn off the PMOS
during testing.
CVSL, Static DCVS
DSL
Source Follower Logic
Ganged CMOS
Current-mode Logic
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CVSL or DCVS
•
•
Cascode-voltage switched Logic (Heller ’84)
– Static differential cascode voltage switched (DCVS)
Use the faster devices to build the logic.
– Outputs will transition as long as the HIGH inputs can enable the
NMOS to win the fight agains the PMOS (cross-coupled
transistors)
• Only pull-down on one side of the structure.
• Pull down past VTP is sufficient to start the positive feedback
• So sizing ratio is not high P:N=1 is fine.
•
•
Speed and power are worse due to the fighting.
– Only during the transient.
– Falling is the faster (earlier) transition.
Sizing is a tradeoff
– If PMOS is too big, NMOS can’t win.
– If PMOS is too small, pull-up is too slow.
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Example: DCVS Full-Adder Pull-Down Network
Sum
Carry
a
b
c
a
c
c
a
a
Carry
b
a
a
c
Sum
b
b
c
•
•
•
a
b
c
Need true and complementary inputs (doubles the wiring)
Lots of different load structures are possible
– Each becomes a different “logic family”
Sizing is same as in domino
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Static Differential Split-Level Logic (DSL)
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•
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Vref keeps the source (Di,Do) from
rising above Vref-VT. The cross coupled
PMOS is the positive feedback that
pulls the outputs F and F’ to nearly full
swing.
– Di,Do are around VDD/2
The circuit can actually use Do (the low
swing) as the output of the block so the
V is less to reduce power and
improve speed.
However, the circuit burns static
power. Refence value must be pretty
well controlled to keep power low.
Do
Do
Pull-down
Tree
F
F
Vref
Di
Di
PfenningJSSC10/85
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Aside: Cascode Nonthreshold Logic (CNTL)
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•
CNTL (Wang89) is an extension of DSL and a variant of NTL (nonthreshold logic).
NTL
– A pseudo-NMOS gate with an RC to ground.
– DC characteristic is almost linear (gain is R1/R2).
– Output starts to transition before the input hits the logical
threshold… hence NTL.
– But current is actually less, so is it actually faster?
R1
f
f
f’
Pull-dn
R2
CNTL
NTL
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Source Follower Pull-Up Logic (SFPL)
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•
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What slows down CMOS is the NOR-type structures
Recall Diode-Based Logic
We can duplicate it for wide ORing functions
– NMOS pull-up (like a diode) (Simon ’92)
A
B
A or B
• Up to about >VDD/2
• Fights against the static pull-down NMOS
• Skewed inverter following the gate
–
–
Or speed up pull-down with extra devices.
The gate looks like the pseudo-NMOS NOR with gated input.
– DC current because inverter PMOS is slightly ON
A
B
3
C
3
D
3
3
6
(A+B+C+D)’
3
6/0
3
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3
3
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Ganged CMOS
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•
A somewhat wacky idea
– Very similar to the pseudo-NMOS with switched PMOS
device.
– Accept some DC current (like pseudo-NMOS) but less.
Concept is to basically connect the output of inverters together
(Johnson ’88)
– Sizing is a bit tricky.
– Static current only ½ of the time (when? ______)
A
2 B
2
A nor B
4
gdn=____
gup= ____
4
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Current Mode Logic
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•
•
Use transistors as switches that steer a fixed current to the output.
Output voltage swing is IR (2x differentially)
Differential steering so VCM (and VOL) >VTN.
– Not like pseudo-NMOS
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Why CML?
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•
Make the entire pull-down network look like a current source.
RC of output determine the speed.
•
•
•
Small R (big I)
makes it fast.
Differential
inputs reduces
the switching
threshold
Less parasitic
and input
capacitance.
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Building Logic with CML
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•
Stacking is a problem.
– Need to keep devices in saturation.
More on the design consideration when we talk about amplifiers.
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Pass-Transistor Logic Families
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Pass Transistor Outline
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Pass transistor characteristics
Transmission gate logic
– Some examples
– Delay, power and noise characteristics
Full Adder using transmission gate logic
Complementary Pass-Transistor Logic (CPL)
Other pass-transistor logic families
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Review: Transmission Gates (TG)
V = Vdd
C C
C
V=0
A
B
A
B
V = VT*
C
V = Vdd-VT*
•
Complementary transmission gates can be used as switches
– nMOS passes 0 well
– pMOS passes 1 (Vdd)
• pMOS device primarily useful for last part of rising output and to pull-up to full rail
• Make it small to reduce parasitic capacitance (size equal to nMOS)
•
•
•
Can degrade VOL or VOH by VT* if only one type is used
– VT* - body effected
Most heavily used in multiplexors and latches
Also good for implementing static XOR gates and logic that use XORs (adders,
parity generators, multipliers, etc.)
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Pass Transistor Properties
V = 3VT
V = Vdd - VT
V = 2VT
V = Vdd - 2VT
V = VT
V = Vdd - 3VT
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•
This is BAD!
Do not drive pass gate with a pass gate output along a long series
chain
– Quickly degrades outputs and eats into noise margin
– If Vdd = 3.3 and VT = 0.7  Vdd - 3VT = 1.2V (< VS of an inverter)
– Severely limits low voltage operation
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Transmission Gate Properties
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Can be very fast for implementing some functions
No amplification
Only use with a lightly loaded output – can have lots of parasitic
capacitance at the output
Need to generate true and complementary controls for pMOS
and nMOS devices
Series transmission gates get very slow after cascading from
series R and diffusion caps
– Limit to 2 or 3, depending on process
Usually follow a transmission gate network with an inverter or
complex static CMOS gate
– Provides amplification to speed up edges
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Transmission Gate 4:1 MUX Examples
s0
s0
s1
sA sB sC sD
s1
A
A
B
B
out
out
C
C
D
D
(b)
(a)
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•
No decoder needed
Better when control-critical or wire
limited
Parasitic capacitance is distributed
along path
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•
Need to decode select lines
Better when data-critical or gatelimited
Parasitic capacitance lumped at the
output
Multiplexing function easily enables other complex functions.
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Delay in Transmission Gate Circuits
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Transmission gates can be analyzed using an RC model
Must also considering the resistance of the gate driving TG in the RC
network.
S
In
A
out
S’
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Resistance of Pass Transistors
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•
There are 2 devices in parallel, but one is passing a weak value
– Resistance of nMOS pulling up = 2RN_pulldn/sq
– Resistance of pMOS pulling down = 2RP_pullup/sq
Given equal sizing for P and N of transmission gate
– Pull-up is 2R(nMOS) || 2R(pMOS) = R/sq
– Pull-down is R(nMOS) || 4R(pMOS) = 0.8R/sq (~ 1R/sq)
– So, can approximate the resistance as R/sq
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RN
20
RP
R(k)
10
0.00.0
VDD
2
3
Vout
REQ
1.0
2.0
3.0
4.0
5.0
Vout
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Delay of Transmission Gate Example
As an example, compute delay through 4:1 mux designs (a) and (b):
• Let gate and diffusion cap of unit transistor be C
• TG has P:N ratio of 1:1
• On TG has both diffusion and gate capacitance.
• Drive input with unit inverter (P:N=2:1), loaded with inverter of sizing factor of f
R
(a)
6C
R
(b)
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•
R
R
8C
(5+3f)C
t = (37+9f)RC
R
6C
(9+3f)C
t = (24+6f)RC
Series transmission gates get very slow after 2 or 3 cascaded gates
Local wiring makes this worse
Ex: a 64 bit parity generator can be built with 6 stages of transmission gate
XORs. Buffer after every 2nd or 3rd stage, depending on process
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Merging TG Logic with Static CMOS Logic
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Break long series of switches with amplifying elements
– Not only an inverter, but can also use other complex CMOS gates
NAND
B
A
B
F=(AB+ABC) (AC)
C
A
A
C
B
A
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Transmission Gate Caveats
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Contention
– Two transmission gates can be on simultaneously, causing glitches
and burn power
– Often because pMOS and nMOS don’t turn off simultaneously or
because two mutually exclusive mux selects have a race
– Especially bad when driven by a dynamic node (illegal)
sel
sel
sel
sel
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More Caveats: Coupling and Noise
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Coupling / Noise
– What happens if the source input goes above Vdd or below Gnd?
• Can inadvertently turn on a pass transistor
• Can happen when driven through a long wire and on-chip Vdd and Gnd
are different
– Noise coupling in long wires can glitch the output
V
Vdd
VddV
VddVt
V
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Example: Transmission Gate Full Adder
S  A  BC
C O  AB  AC  BC
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•
•
•
B
Can easily implement XORs in
transmission gate logic to build
adders
Input to Output speed paths differ for
A, B and CI
– CI is closest to the output and
therefore the fastest input
– B is farthest and slowest
– Order inputs according to signal
speeds
Can taper transmission gate sizes
Reduce input loading by eliminating
unnecessary pass transistors
– Given static inputs Vdd and Gnd
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CI
S
A
B
CI
CO
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Example: Other Transmission Gate XORs
A
B
F = AB + AB
A
B
A
A
F = AB + AB
F = AB + AB
B
B
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8 transistor XOR
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6 transistor XOR
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Example: Using the XORs in Full Adder
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Avoid series T-gates.
– A, B, and Ci are driven by inverters.
– P and P’ (output of T-gates) only drives gates of transistors.
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
VDD
S Sum Generation
Ci
P
B
P
A
Co Carry Generation
P
Ci
VDD
Ci
A
P
Setup
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Transmission Gate Tricks
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pMOS device in a transmission gates are annoying
– Doesn’t speed up path much
– Adds capacitance and requires complementary control lines
Get rid of the pMOS  degrades output VOH to Vdd-VT
– Compensate by skewing subsequent gate so that its input switching
point is low
– Or, restore output with weak feedback or pseudo-nMOS
•
weak
•
•
weak
Noise margins are still degraded and have been known to fail when
Vdd is reduced
Use carefully, if at all…
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Impact of Level Restoring Transistor
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There is a name for this!
– LEAN Integration with Pass-transistors –
LEAN (Yano 96)
5.0
B
A=VDD
X
with
5.0
without
Vout
3.0
VX
without
3.0
with
out
VB
1.0
-1.0
1.0
0
2 t (nsec) 4
6
-1.0
(a) Output node
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2
4
t (nsec)
(b) Intermediate node X
6
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Complementary Pass-Transistor Logic (CPL)
B
B
B
A
B
A
AB
B
A+B
B
B
B
AB
A
A+B
A
Yano JSSC4/90
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nMOS only pass-transistor network for logic operations
– Significantly cuts down transistor count and parasitic caps
– Requires complementary inputs and provides complementary outputs
Degraded VOH due to VT drop
– Can use low VT nMOS devices
• increases processing complexity for these devices
• reduces noise immunity
• more leakage
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A CPL Full Adder
A
C
A
C
A
C
A
B
B
B
B
A
A
B
A
A
C
C
Carry
•
B
C
Carry
XOR
Sum
Sum
According to paper: 60% delay, 80% power, similar area as a standard
CMOS.
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Aside: Double Pass-Transistor Logic
CPL
R
R
3W
DPL
R
W
2W
A
B
B
A
A
B
A
Out
Out
NAND/AND
Example Suzuki JSSC11/93
R/3
R
B
R
•
Extending upon CPL, to better pass a high signal (especially in low
supply) by using PMOS transistors for transmission.
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Small improvement (5%)
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Aside: DPL Adder Example
Sum
Circuit
Carry
Circuit
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Other Variants of Pass-Transistor Logic
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Several other families
– Most are extensions of CPL using different implementations
of the tricks mentioned earlier.
Example: Energy Economized PTL – EEPL (Song 96)
– Drives the pull-up PMOS from out’
– Turn off the fighting on the pull-down)
• But the fighting is turned off after a delay… so the improvement
is not clear.
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Variants that Eliminates the Output Inverter
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Since the PMOS essentially restores the voltage levels…
– One can argue that we don’t really need the inverter
• DCVS-PG – uses the same pull-up as DCVS.
• PPL – similar to DPL where two separate networks are used;
except use NMOS restore transistor for the PMOS network.
– The problem is that the cross-coupled devices now needs to
be bigger to restore the swing well.
• Otherwise, this results in a long chain of pass-transistors.
• Net result is a more noise sensitive logic.
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Swing-Restored Pass-Transistor Logic
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SRPL (Parameswar JSSC 96)
– Use cross-coupled inverters
to restore swing.
• Basically added NMOS
cross-coupling
•
Sizing issue
– NMOS cross-coupling will
fight against the pull-up so
the sizing can’t be too big.
– Small inverters wont buffer
well.
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Gate Optimization in SRPL
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Sizing focuses on the PMOS
– Size PMOS small to have a
high-speed latch
– Size PMOS large to increase
driving ability
Adjust platch/nnetwork and nlatch/nnetwork
– Wide range of ratio
The author’s simulation shows a
substantial design margin
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Pass-Transistor Logical Effort (PTL)
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•
Consider the pass-gate and the driving gate together as a single gate.
Assume true and complement inputs/outputs as clusters (a single
signal).
– S and S’ = 5 unit capacitance.
– The assumption is that S’ is generated with a FO1 delay (short
delay)
– LE S (pull up) ~ __________
– LE In (pull up) ~ __________
In
S’
1
2
A
2
S
S
4
B
4
3
2
S’
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Logical Effort: CPL Example
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CPL Example:
Let M1=M2=M3=4
– LE a-input = 4/3
– LE b-input = 2/3
– A-input is not any better than a normal NAND gate
• Would be better if we precharge M2.
•
Wont be able to distinguish between CPL and EEPL or SRPL.
M1
M2
M3
b
M3
a
C2
C1
C3
C1
M1
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Pass-Transistor for a Decoder
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•
For decoder, some addresses may arrive earlier,
– Let, a, be the early arrivals
Signals may be shared
– c may be distributed over a long wire to all the final decodes.
– Make M1 large and drive the address line C1.
– The effect is an AND function that is smaller.
– Delay is also much smaller
M2
d
b
M3
a
C1
C2
c
M1
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Summary
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Static logic families other than static CMOS improves
performance in a number of ways
– Reducing voltage swing
– Eliminating the complementary block
– Reducing the switching threshold
– Compacting the switch network using both S/D and gate as
inputs.
Often results in tradeoffs
– More sensitive to noise
– DC power dissipation.
Can be very effective when used judiciously
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