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CMPEN 411 VLSI Digital Circuits Lecture 06: Static CMOS Logic Kyusun Choi [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L06 S.1 Review: CMOS Process at a Glance Define active areas Etch and fill trenches One full photolithography sequence per layer (mask) Built (roughly) from the bottom up Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers CMPEN 411 L06 S.2 4 2 3 1 metal polysilicon exception! source and drain diffusions tubs (aka wells, active areas) CMOS Circuit Styles Static complementary CMOS - except during switching, output connected to either VDD or GND via a lowresistance path high noise margins - full rail to rail swing - VOH and VOL are at VDD and GND, respectively low output impedance, high input impedance no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise CMPEN 411 L06 S.3 Static Complementary CMOS Pull-up network (PUN) and pull-down network (PDN) VDD PMOS transistors only In1 In2 PUN InN In1 In2 InN pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1 F(In1,In2,…InN) PDN pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0 NMOS transistors only Question : How many transistors are used to implement N-input function F(In1,In2,…InN) ? CMPEN 411 L06 S.4 Construction of PDN NMOS devices in series implement a NAND function A•B A B NMOS devices in parallel implement a NOR function A+B A CMPEN 411 L06 S.5 B Dual PUN and PDN PUN and PDN are dual networks DeMorgan’s theorems A+B=A•B [!(A + B) = !A • !B or !(A | B) = !A & !B] A•B=A+B [!(A • B) = !A + !B or !(A & B) = !A | !B] a parallel connection of transistors in the PUN corresponds to a series connection of the PDN Complementary gate is naturally inverting (NAND, NOR, AOI, OAI) Number of transistors for an N-input logic gate is 2N CMPEN 411 L06 S.6 CMOS NAND A A B F 0 0 1 0 1 1 1 0 1 1 1 0 B A•B A B A B CMPEN 411 L06 S.7 CMOS NOR B A A+B A B A B CMPEN 411 L06 S.8 A B F 0 0 1 0 1 0 1 0 0 1 1 0 Complex CMOS Gate B A C D OUT = !(D + A • (B + C)) A D B CMPEN 411 L06 S.10 C Static Complementary CMOS Naturally inverting, implementing only functions such as NAND, NOR, and XNOR in a single stage. VDD PMOS transistors only In1 In2 PUN InN In1 In2 InN pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1 F(In1,In2,…InN) PDN pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0 NMOS transistors only Question1: why PUN are PMOS only and PDN are NMOS only? CMPEN 411 L06 S.11 Threshold Drops VDD PUN VDD S D VDD D 0 VDD VGS S CL VDD 0 PDN D VDD S CMPEN 411 L06 S.13 CL 0 VDD - VTn CL VGS VDD |VTp| S D CL Standard Cell Layout Methodology Routing channel VDD signals GND What logic function is this? CMPEN 411 L06 S.14 OAI21 Logic Graph X A j C C B X = !(C • (A + B)) C A i i X B VDD j B A B C CMPEN 411 L06 S.15 PUN GND A PDN Two Stick Layouts of !(C • (A + B)) crossover requiring vias A C B A B C VDD VDD X X GND GND uninterrupted diffusion strip CMPEN 411 L06 S.16 Consistent Euler Path An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X C i X B VDD j GND A A B C For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same) CMPEN 411 L06 S.18 OAI22 Logic Graph A C B D X D X = !((A+B)•(C+D)) C D A B CMPEN 411 L06 S.19 C VDD X B A B C D PUN A GND PDN OAI22 Layout A B D C VDD X GND Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!) CMPEN 411 L06 S.20 XNOR/XOR Implementation XNOR XOR A A AB B A B B AB A B AB How many transistors in each? Can you create the stick transistor layout for the lower left circuit? CMPEN 411 L06 S.21 AB Static CMOS Full Adder Circuit (page 565) Cout=AB+BCin+ACin Sum = ABCin+!Cout(A+B+Cin) B A B B A Cin A B Cin Cin !Cout !Sum A A B A Cin B A B Cin A B Cout = Cin & (A | B) | (A & B) CMPEN 411 L06 S.24 Sum = !Cout & (A | B | Cin) | (A & B & Cin) # transistors = 24+4 Two chips you are seeing today Microprocessor CMPEN 411 L06 S.25 ASIC (Application Specific IC) Standard Cell Library NAND CMPEN 411 L06 S.26 INV Standard Cell Library NAND CMPEN 411 L06 S.27 INV NAND The design flow VHDL Simulation Synthesis (decoder.vhd) Standard Verilog netlist (decoder.v) Place/Route Physical layout (decoder.cif) CMPEN 411 L06 S.28 Cell Lib The IBM ASIC Design Flow CMPEN 411 L06 S.29 Next Lecture and Reminders Next lecture Pass transistor logic - Reading assignment – Rabaey, et al, 6.2.3 CMPEN 411 L06 S.30