Download Switching Energy in CMOS Logic

Switching Energy in CMOS Logic:
How far are we from physical limit?
Saibal Mukhopadhyay
Arijit Raychowdhury
Professor: Kaushik Roy
Dept. of Electrical & Computer Engineering
Purdue University
NRL NANOELECTRONICS
RESEARCH LAB
Network for Computational
Nanotechnology
2
Outline
• Switching energy in charge transfer based
Digital Logic
– Basics and Physical Limits
• Practical consideration for switching energy
in CMOS Logic
– Static requirements
– Dynamic requirements
– System considerations
• What can we do to reduce switching energy ?
• Summary
3
+
–
Ron
Vmin
C
Vout = Q
C
Voltage
Charge Based Digital Logic
Vmin
“1”
“0”
Time
Key principles in the charge based digital logic
1. Representation of digital states
Logic “0”: No Charge in the capacitor
Logic “1”: Charge stored in the capacitor
2. Change of digital state
Charge/dis-charge capacitor through a resistor
4
Switching Energy
+
–
Ron
Vmin
C
dv o
iC ( t ) = C
dt
Voltage
i DD ( t )
Vmin
“1”
“0”
∞
VDD
ETotal = ∫0 i DD ( t )Vmin dt = ∫0 CVmin dv0 = CV
1
∞
VDD
2
ECap = ∫0 iC (t )v0 ( t )dt = ∫0 Cv 0 dv0 = CVmin
2
1
2
∴ Ediss (0 → 1) = ETotal − ECap = CVmin
2
2
min
Time
2
Ediss = CVmin
= QVmin
Switching energy can be minimized by
reducing Q and/or Vmin
5
Physical Medium for Computation:
Barrier Model
GATE
V=0
SOURCE
DRAIN
Leff
V=Vmin=Ebmin
Tox
Vg
Eb
Vd
6
Eb
Lch
Perr = Perr _ cl + Perr _ QM
− Perr _ cl Perr _ QM
For Lch > 10nm
Min barrier height (Eb) in kBT
Minimum Barrier Height:
Zhirnov’s Model
Lch=32nm
Lgate = 45nm
Channel Length (Lch) [nm]
Perr ~ exp ( − Eb k BT ) => E b = k BTln 1 Perr 
Minimum barrier height = Ebmin ~ kBTln(2)
7
Minimum Operating Voltage and
Switching Energy
V=0
V=Vmin=Ebmin
Eb
• Minimum operating voltage
Vmin ~ kBTln(2)
• Minimum switching energy
Ediss= QminV min=qkBTln(2) ~ 0.7kBT
Switching energy for an minimum sized inverter
designed using in 45nm gate length devices ~
35000kBT
Why are we so far from the limit?
1. Can we operate with Vmin ~ KBTln2 ?
2. Can we operate with Qmin = q ?
9
Outline
• Switching energy in charge transfer based
Digital Logic
– Basics and Physical Limits
• Practical consideration for switching energy
in CMOS Logic
– Static requirements
– Dynamic requirements
– Circuit/System considerations
• What can we do to reduce switching energy ?
• Summary
10
Gate failure probability
Outputs
Inputs
Reliability of Circuit Operation
Ndev~100million
Ndev~300million
Perr ~5x10-12
Ndev~500million
Circuit failure prob [%]
# of devices = Ndev
Prob. of error of a single gate = Perr
Prob. of error of the circuit = Pcirc = 1 – (1-Perr)Ndev
Reliable operation of the circuit imposes stronger
constraint on the reliability of the gate operation
11
Reliable Operation for a Device
– Perr = 0.5
=> Eb= 0.7kBT
– Perr = 5x10 -12
=> Eb= 25kBT
• 0.1% failure rate for a
circuit of 300 million
devices => Vmin~25kBT
kBTln(2)
Eb=25kBT
Barrier Height in kBT
• Reliable operation
requires a higher
barrier
Lgate =45nm
Lch=32nm
Perr ~ 5x10-12
Device error probability (Perr)
Reliability
25kBT
12
CMOS Logic: Physical Model
VDD
Vin
Vin
Vo
Vout
“0” ≡ 0V “1” ≡ VDD
“1” ≡ VDD
“0” ≡ 0V
CMOS logic operates based on presence or absence
of charge and not on localization of charge
13
Operation of MOS Device
V=0
Vg
V=VDD=EbOFF – EbON
η = 1 + C semi C ox
Cox
EbOFF
EbON
Csemi
VDD
k BT  pon
=η
ln 
p
q
 off



Operation with a larger pon/poff requires a higher
supply voltage
14
Operation of CMOS Logic
VOH
NML = VIL-VOL
VDD
Vin
NMH = VOH-VIH
Vo
Av= Max gain
o
V
=
n
Vi
VIL
VIH
VOL
 1 − exp ( − q (VDD − V0 ) k B T ) 
 pon 
k BT
kBT

Vin = 0.5η
× ln 
+ 0.5η
× ln 

 p 


q
q
1 − exp ( − qV0 k BT )
 off 


15
Operation of CMOS Logic
p on
= 100
poff
p on
= 10
p off
p on
=4
poff
p on
=2
poff
Higher pon/poff improves maximum gain and
noise margin
16
Operation of CMOS Logic
2n+1 stages
Vol
“0”
Voh
Vout
“1”
?
Vin = VDD 2- ∆
Vo(1) = Vin(2) = VDD 2 +∆A v
M
Vo(2n+1) = VDD 2 -∆ (-1)2n+1 Av2n+1
if Av < 1, as n → ∞ , VO → VDD 2
if Av > 1, as n → ∞ , VO → VOH
Vin
17
Operation of CMOS Logic
distinguishability
=> Gain (AV) > 1
pon/poff=4
for CMOS inverter
Minimum pon/poff
is “4”
and
not “2”
Vmin= kBTln(2)
AV =1
VDD
kBT
=2
ln ( 1 + η Av )
q
=> Vmin = 2 ( k BT q ) ln ( 2 )
Device to Inverter
Vmin= 2kBTln(2)
Noise margin in kBT (NM/kBT)
Operation of CMOS Logic
supply voltage in kBT (VDD/kBT)
To prevent spontaneous change of state noise
margin needs to be at least higher than kBT
=> VDD > 3kBT
18
19
Gate failure probability
Outputs
Inputs
Reliability of Circuit Operation
Ngate~100million
Ngate~300million
Perr ~5x10-12
Ngate~500million
Circuit failure prob [%]
# of gates = Ngate
Prob. of error of a single gate = Perr
Prob. of error of the circuit = Pcirc = 1 – (1-Perr)Ndev
Reliable operation of the circuit imposes stronger
constraint on the reliability of the gate operation
20
Reliability of CMOS Inverter Operation
NM
NM
σN
Vnoise
Noise Margin in kBT
Perr~5x10-12
Perr~5x10-10
Perr~5x10-8
Std. dev of noise voltage [mV]
Higher noise requires a larger noise margin for
reliable operation
21
Noise margin in kBT (NM/kBT)
Reliability of CMOS Inverter Operation
~13kBT
~10kBT
supply voltage in kBT (VDD/kBT)
Vmin= 2kBTln(2)
Reliability
Vmin= 10kBT
Operations of CMOS Logic
1. It is a “single well - double barrier” system.
2. Presence or absence of charge at the “well”
determines the logic state
3. At both logic states, the well is strongly
coupled to VDD or GND through a “on” device
The “driven” nature of CMOS logic makes it
reliable even at very low voltage operation
23
Limit of poff : Leakage Power
EbOFF
1mA/µm
0.1mA/µm
Lch
Ids
I leak
 EbOFF
= I0 exp  −
 kBT

 = I 0 poff

1nA/µm
Vt
Vgs
I leak ~ 1nA / µ m ⇒ poff ~ 10−5
( ) ~ 11k T
⇒ E bOFF = k BT × ln 10
5
B
EbOFF ~ 11kBT helps to meet a leakage
requirement of 1nA/µm
VDD
24
Outline
• Switching energy in charge transfer based
Digital Logic
– Basics and Physical Limits
• Practical consideration for switching energy
in CMOS Logic
– Static requirements
– Dynamic requirements
– Circuit/System considerations
• What can we do to reduce switching energy ?
• Summary
25
Delay in CMOS Logic
Vin
Voltage
VDD
Vmin
“1”
Vo
“0”
+
–
Voltage
Time
Ron
Vmin
Vmin
“1”
C
“0”
Time
26
+
–
Ron
Vmin
C
Voltage
Delay and Switching Energy
Vmin
~RonC
“1”
“0”
Time
• Delay through an RC circuit
– Independent of applied voltage Vmin
– Lower C reduces both delay and switching energy :
key principle in technology scaling
27
Delay and Switching Energy :
V
CMOS Logic
g
Ron
C
gmV gs
The dependence of Ron
on the applied gate bias
makes delay and energy
correlated for CMOS
C gateVDD = τ I on
For : W P = 2W N = 2 Lmin
C par

1 +
C ox

 2
Lmin

EbOFF 
C ox  VDD − η
 3 Lmin C oxVDD = τµeff

2 Lmin
q 


2
28
Supply Voltage in kBT
Impact of Delay on Minimum VDD
µ neff ~ 300 cm 2 / V-sec
Cpar ~ 30% x Cgate
No parasitics
Delay Target [ps]
Vmin= 10kBT
Delay (1ps)
Vmin= 28kBT
29
Non-ideal subthreshold slope
V=0
V=VDD=EbOFF – EbON
EbOFF
EbON
VDD
k BT  pon
=η
ln 
p
q
 off



A larger subthreshold slope requires a higher
VDD to achieve a pon/poff
30
Ids
VDD
Vgs
Supply voltage in kBT [ps]
Non-ideal subthreshold slope
37kBT
η=1.5
η=1.0
Delay Target [ps]
Non-ideal subthreshold slope increases the
VDD required to achieve a certain delay
31
2-D Electrostatics
Vg
Cs Csemi
∆Eb
Cox
Cd
Vds
Degraded Sub-slope
Drain Induced Barrier Lowering
Vout
Voltage
NMOS in linear
Vin
Delay increase
due to SCE & DIBL
Time
32
VDD required for τ = 1ps
2-D Electrostatics
VDD ~ 39kBT
Barrier Lowering (mV)
Under same leakage power 2-D effect increases
the VDD required to achieve a target delay
33
Process Variability
∆Eb
Vds
Ids
Variation in Process Parameters
VDD
• Leakage ~ poff variation
Vgs
• Reliability ~ pon/poff variation
• Delay ~ variation in EbOFF will change the delay
The designed EbOFF and VDD needs to be
increased to account for the effect of variation
± 10% variation in EbOFF => VDD ~ 42kBT
34
Why We are using VDD much larger
than the kBTln(2) limit?
kBT
ln(2) CMOS Logic
q
kBT
2
ln(2)
q
Reliability
Noisetolerance
Distinguishability
10 ( k BT q )
42 ( k BT q )
Subth. Slope, 2-D effect,
Process variation, etc.
Non-idealities
28 ( kBT q )
Delay (1ps)
35
Drivability in Digital Logic
Vmin
Vmin
Vmin
“0”
“0”
“1”
“0”
Vmin
C
C
“1”
“0”
+
–
Vmin
Ron
V
min
“0”
C
Ron
“0”
Vmin
C
Vmin needs to be developed across a finite
capacitance for driving the next gate
36
Drivability and Minimum Charge
Qmin = CVmin
Number of electrons
FO4 (w/ par) + local interconnect ~5300
min size INV ~ 800
min size NMOS ~260
T
B
k
42
~
)
2
(
n
i
ln
Vm
T
kB
2
~
n
i
Vm
Lgate =45nm
Lch=32nm
Load Capacitance [F]
Drivability requirement does not allow to operate
with a single electron for CMOS logic operation
Switching energy in kBT
Drivability and Switching Energy
FO4 (w/ par) + local interconnect ~ 220,000
min size INV ~ 33000
min size NMOS ~11000
V min
V min
T
k
B
2
4
~
~
(2)
n
l
T
2k B
Lgate =45nm
Lch=32nm
Capacitance [F]
Drivability requirement increases the minimum
switching energy for an inverter to ~ 33,000 kBT
37
Switching Energy in CMOS Logic
Delay ~ 1ps, High reliability
kBTln(2) Delay/Reliability
42kBT
Drivability
33000kBT
39
Outline
• Switching energy in charge transfer based
Digital Logic
– Basics and Physical Limits
• Practical consideration for switching energy
in CMOS Logic
– Static requirements
– Dynamic requirements
– Circuit/System considerations
• What can we do to reduce switching energy ?
• Summary
40
Operation of CMOS Circuits
F/F
F/F
C
4C
• For logic operation a gate has to drive more than one
gates in a CMOS logic
• Typical fanout is assumed to be 4
Switching Energy in CMOS Logic
Delay ~ 1ps, High reliability
kBTln(2) Delay/Reliability
42kBT
Drivability
220,000kBT
FO4
33000kBT
42
Switching Energy in kBT
Switching Energy for a System
28,000,000
2,800,000
280,000
Capacitance [F]
Driving “long” interconnects can significantly
increase the switching energy
43
Switching Energy for a System
Interconnect capacitance values
were estimated from ITRS 2004
Interconnect of length ~400µm has 100 fF of cap
which requires ~28,000,000 kBT to switch
44
How many long interconnects exists in
an Integrated Circuits?
•
•
•
For a logic block of ‘N’ elements (say inverters) the total
number of external interconnects : T = kNp
p = Rent’s exponent – represents the balance between
local and global interconnects
Rent’s rule → Int. conn. length distribution
Density = i(l) = # of Int with length ‘l’ s.t. a < l <b
Distribution = I(l) = # of Int with length less than ‘l’
Wiring capacitance can be calculated from interconnect
length distribution
1. Feynman Lectures on Computation, pages 277-282
2. W.E. Donath, IBM J. Res. Develop. 25, 152 (1981)
3. J.A. Davis, et. al, IEEE TED, vol. 45, March 1998, pp:580 - 597
45
N ~ 300 million, k = 4
Rent’s ex = 0.9
Rent’s ex = 0.6
Length in gate pitches
Interconnect distribution
Interconnect density
Distribution of Interconnect
Rent’s ex = 0.9
Rent’s ex = 0.9
Length in gate pitches
A higher Rent’s exponent indicates a higher
number of global interconnects
46
Switching Energy in kBT
Switching Energy for a System
1,200,000 kBT
Rent’s ex ~ 0.7
Capacitance [F]
Interconnect (or wiring) capacitance can increase
the average switching energy of a gate to
~1,200,000 kBT
Practical Limits in Switching
Energy in CMOS Systems
Physical Limit: kBTln(2)
Requirement for Computation: 33,000 kBT
Reliability, Speed and Drivability
Requirement for Communication:
1,200,000 kBT
Local and global communication
48
How can we reduce the practical
switching energy limit?
49
Switching Energy and Leakage
Power Trade-off
Cpar ~ 0.3 x COX, η=1.5
Delay target ~ 1ps
Target Ioff
VDD
VDD required in kBT
Ids
Vgs
Leakage Current [nA/µm]
Operating at 10X higher leakage can reduce the switching
energy from 33,000kBT to 23,000 kBT
50
Ids
Higher µ
VDD
Vgs
Supply voltage required in kBT
Can Higher Mobility help?
Cpar ~ 0.3 x COX, η=1.5
Delay target ~ 1ps
33,000 kBT
23,000 kBT
11,000 kBT
Mobility Enhancement Factor
Devices with higher mobility and higher
leakage target can reduce switching energy
51
Supply Voltage in kBT
Switching Energy and Delay Trade-off
pon=1
pon < 1
Reliability req.
Delay Target [ps]
For delay targets > 100ps subthreshold
operation is more energy efficient
52
1,200,000 kBT
230,000 kBT
# of interconnects
Int. conn. cap per gate [fF]
Switching Energy for a System
Rent’s Exponent
Reducing the number of local interconnects can
significantly reduce the system switching energy
53
Single Electron Operation in CMOS
Number of electrons
Qmin = CVmin
V min
T
B
k
2
~4
V min
)
2
(
n
l
T
kB
~2
Load Capacitance [F]
Single electron operation at room temperature is
only possible if C < 9aF
54
Minimum # of electrons
Scaling and Single Electron
Operation in CMOS
Vmin ~ 42kBT
Vmin ~ 2kBT ln (2)
EOT ~ 1.8nm
Lch~ 8nm
Channel Length [nm]
Single electron operation in CMOS logic is
possible for L < 8nm
55
Scaling and Switching Energy
Scaling helps to reduce switching energy even if
the supply voltage remains the same
56
Scaling and Thermal Noise
+
–
Ron
C
4kB TR
4k BT
Vnoise = σ noise =
=
RC
C
For : C = 0.1 fF => σ noise = 12mV
For : C = 9aF => σ noise = 43mV
Increase in thermal noise at lower capacitance
can reduce the energy benefit of scaling
57
Summary
1. Can we operate with Vmin ~ KBTln2 ?
•
•
•
Reliability
Delay
sub. slope, 2-D effects, variability etc.
2. Can we operate with Qmin = q ?
•
•
Drivability
Parasitic and Interconnect capacitance
Device/Circuit/System level investigations can
reduce the practical limit of switching energy,
but it is very difficult to achieve the physical
limit in CMOS logic
58
References
1. V. Zhirnov et. al, Proceedings of the IEEE, vol.
91, Nov 2003 pp. 1934 – 1939.
2. J. D. Meindl, Proceedings of the IEEE, Vol.83, April
1995, pp.:619 - 635
3. W.E. Donath, IBM J. Res. Develop. 25, 152 (1981)
4. J.A. Davis, et. al, IEEE TED, vol. 45, March 1998,
pp:580 – 597 (two consecutive papers)
5. L. B. Kish, Phys. Lett. A, vol. 305, pp. 144–149, 2002.
6. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI
Devices, Cambridge University Press, 1998
59
Questions and Answers
60
Minimum # of electrons
Scaling and Single Electron
Operation in CMOS
Vmin ~ 42kBT
Vmin ~ 2kBT ln (2)
EOT ~ 1.8nm
Lch~ 8nm
Channel Length [nm]
Single electron operation in CMOS logic is
possible for L < 8nm
61
Drivability in Digital Logic
Vmin
Vmin
Vmin
“0”
“0”
“1”
“0”
Vmin
C
C
“1”
“0”
+
–
Vmin
Ron
V
min
“0”
C
Ron
“0”
Vmin
C
Vmin needs to be developed across a finite
capacitance for driving the next gate
62
Drivability and Minimum Charge
Qmin = CVmin
Number of electrons
FO4 (w/ par) + local interconnect ~5300
min size INV ~ 800
min size NMOS ~260
T
B
k
42
~
)
2
(
n
i
ln
Vm
T
kB
2
~
n
i
Vm
Lgate =45nm
Lch=32nm
Load Capacitance [F]
Drivability requirement does not allow to operate
with a single electron for CMOS logic operation