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Digital to Analog Converter for High-Fidelity Audio Applications Matt Smith Alfred Wanga CSE598A Summary • R-2R Ladder Architecture • Current progress – Poly resistor, NOR gates, D-flipflops • Remaining work • Observations and challenges • Schedule R-2R Ladder Architecture 3R2 R2 Vout [ ]x3 Gain of 3 on output stage allows full voltage range on output, in addition to buffering for low output impedance Current Progress • Digital Logic – Flip flops used to latch digital inputs – Gate logic optimized for digital transition point – D flip flop was designed from NOR gate logic – Layout and testing complete • Polysilicon Resistors – Values of 7kΩ and 14kΩ chosen for R-2R ladder resistors Polysilicon Resistors • Serpentine pattern used to construct standard (7k) and double (14k) sized resistors • Resistance calculated from process parameters • Since resistors are needed in R-2R ratios, exact poly sheet resistance is no concern (all resistors are affected proportionately) NOR Gate Logic A B OUT D Flip Flop • Layout done with metal1 and metal2, leaving metal3 for global routing Inverter NOR3 NOR2 D Flip-Flop Simulation Results CLK DIN Q QNOT Remaining Work • Output Buffer – Linear, Large (Current) Gain – Large output swing needed • Design Layout Characterization – Signal Distortion – Maximum Load Impedance – Frequency Response Observations and Challenges • Use of hierarchical cells reduced the complexity and time needed for schematics and layout • Line resistance is not calculated during layout extraction, making simulation of polysilicon-based resistors more difficult The Schedule • 3/13 – Finish individual cells, figure out how to properly simulate poly resistors • 3/20 – Do full layout • 3/27 – Simulation • 4/3 – Debug, prepare presentation