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1. COMPUTER ORGANIZATION &OPERATING SYSTEMS 2.SYLLABUS COMPUTER ORGANIZATION AND OPERATING SYSTEMS UNIT I Basic structure of computers: Computer types, functional unit, basic operational concepts, bus structures, software, performance ,multiprocessors and multi computers, data representation, fixed point representation, floating-point representation. Register transfer language and micro operations: Register transfer language ,register transfer bus and memory transfers ,arithmetic micro operations ,logic micro operations, shift micro operations, arithmetic logic shift unit, Instruction codes, computer registers computer instructions-instruction cycle. Memory-reference instructions, input-output and interrupt, stack organization, instruction formats, addressing modes, data transfer and manipulation, program control ,reduced instruction set computer. UNIT II Micro programmed control: control memory, address sequencing, micro program examples, design of control unit ,hard weird control, micro programmed control The memory system :basic concepts of semiconductor RAM memories, read-only memories, cache memories performance considerations, virtual memories secondary storage, introduction to RAID. UNIT III Input-output organization: peripheral devices ,input-output interface, asynchronous data transfer modes, priority interrupt, direct memory access, input- output processor(iop),serial communication, introduction to peripheral components ,interconnect(pci)bus, introduction to standard serial communication protocols like RS232,USB,IEEE1394. UNIT IV: Computer System and Operating System Overview: Overview of computer operating systems functions , protection and security, distributed systems special purpose systems, operating systems structures-operating system services and systems calls, system programs, operating systems generation. Memory Management : Swapping, contiguous memory allocation, paging, structure of the page table , segmentation, virtual memory, demand paging, page-Replacement algorithms, allocation of frames, thrashing case studies UNIX, Linux, Windows. Principles of deadlock : system model, deadlock characterization, deadlock prevention, detection and avoidance, recovery form deadlock. UNIT V: File system Interface: the concept of a file, Access Methods, Directory structure, File system mounting, file sharing, protection. File System implementation: File system structure, file system implementation, directory implementation, directory implementation, allocation methods, free-space management. TEXT BOOKS 1. computer organization-Carl Hamacher, Zvonks Vranesic,safeazaky,5th edition,McGrawHill. 2. computer systems architecture-M.MorisMano,3rd Edition,pearson. 3. Operating System Concepts- Abraham Silberchatz, Peter B. Galvin, Greg Gagne 7th Edition, John Wiley. REFERENCE BOOKS 1.computer organization and architecture-William Stallings 6th Edition, Pearson 2.structured computer organization-Andrew s.tanenbaum,4th edition PHI 3.fundamentals of computer organization and design-Sivaraama Dandamudi Springer int.Edition. 4.operating systems-internals and design principles.stallings,6th edition-2009,pearson education. 3.Vision of the Department To impart quality technical education in Electronics and Communication Engineering emphasizing analysis, design/synthesis and evaluation of hardware/embedded software using various Electronic Design Automation (EDA) tools with accent on creativity, innovation and research thereby producing competent engineers who can meet global challenges with societal commitment. 4.Mission of the Department i. To impart quality education in fundamentals of basic sciences, mathematics, electronics and communication engineering through innovative teaching-learning processes. ii. To facilitate Graduates define, design, and solve engineering problems in the field of Electronics and Communication Engineering using various Electronic Design Automation (EDA) tools. iii. To encourage research culture among faculty and students thereby facilitating them to be creative and innovative through constant interaction with R & D organizations and Industry. iv. To inculcate teamwork, imbibe leadership qualities, professional ethics and social responsibilities in students and faculty. 5.Program Educational Objectives and Program outcomes of B. Tech (ECE) Program Program Educational Objectives of B. Tech (ECE) Program : I. To prepare students with excellent comprehension of basic sciences, mathematics and engineering subjects facilitating them to gain employment or pursue postgraduate studies with an appreciation for lifelong learning. II. To train students with problem solving capabilities such as analysis and design with adequate practical skills wherein they demonstrate creativity and innovation that would enable them to develop state of the art equipment and technologies of multidisciplinary nature for societal development. III. To inculcate positive attitude, professional ethics, effective communication and interpersonal skills which would facilitate them to succeed in the chosen profession exhibiting creativity and innovation through development both as team member and as well as leader. research and Program Outcomes of B.Tech ECE Program: 1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve complex engineering problems of Electronics and Communication Engineering systems. 2. An ability to model, simulate and design Electronics and Communication Engineering systems, conduct experiments, as well as analyze and interpret data and prepare a report with conclusions. 3. An ability to design an Electronics and Communication Engineering system, component, or process to meet desired needs within the realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability and sustainability. 4. An ability to function on multidisciplinary teams involving interpersonal skills. 5. An ability to identify, formulate and solve engineering problems of multidisciplinary nature. 6. An understanding of professional and ethical responsibilities involved in the practice of Electronics and Communication Engineering profession. 7. An ability to communicate effectively with a range of audience on complex engineering problems of multidisciplinary nature both in oral and written form. 8. The broad education necessary to understand the impact of engineering solutions in a global, economic, environmental and societal context. 9. A recognition of the need for, and an ability to engage in life-long learning and acquire the capability for the same. 10. A knowledge of contemporary issues involved in the practice of Electronics and Communication Engineering profession 11. An ability to use the techniques, skills and modern engineering tools necessary for engineering practice. 12. An ability to use modern Electronic Design Automation (EDA) tools, software and electronic equipment to analyze, synthesize and evaluate Electronics and Communication Engineering systems for multidisciplinary tasks. 13. Apply engineering and project management principles to one's own work and also to manage projects of multidisciplinary nature 6. COURSE OBJECTIVES AND OUTCOMES : Course objectives: Should be able to explain the basic structure, operation and data representation of a digital computer Should be able to perform arithmetic operations on fixed point and floating point numbers using standard algorithms. Should be able to perform micro operations on registers. Should be able design control unit using micro programming by properly selecting the type of memory for the given purpose. Should be able to differentiate ways of communicating with IO devices and standard IO interfaces. Should be able to differentiate cache memory and virtual memory with the understanding of the hierarchical memory system. Should be able to demonstrate the knowledge of functions of operating system memory management scheduling, file system and interface, distributed systems, security and Dead locks. Should be able to implement a significant portion of an operating system. Course Outcomes: At the end of course, student will Explain the basic structure, operation and data representation of a digital computer. Perform arithmetic operations on fixed point and floating point numbers using standard algorithms. Design control unit using micro programming (using micro operations) and proper type of memory. Differentiate ways of communicating with IO devices and standard IO interfaces. Differentiate cache memory and virtual memory with the understanding of the hierarchical memory system. Demonstrate the knowledge of functions of operating system memory management scheduling, file system and interface, distributed systems, security and Dead locks. Implement a significant portion of an operating system. 7. Brief Notes On The Importance Of The Course And How It Fits Into The Curriculum Computer organization and Operating systems (COOS) course explains fundamental knowledge needed for the design of digital systems, logical operation of the most common standard digital components, register transfer language and shows how it is used to express micro operations, algorithms for arithmetical operations, memory organization Input/output organization and processor organization and provide a set of functions needed and used by most application programs on a computer, and the linkages needed to control and synchronize computer hardware. On the first computers, with no operating system, every program needed the full hardware specification to run correctly and perform standard tasks, and its own drivers for peripheral devices like printers and punched paper card readers. The growing complexity of hardware and application programs eventually made operating systems a necessity. 8. Prerequisites : . Students should have little basics of computer components, microprocessor interfacing lab and operating system that would be able to use computer. 9.Instructional Learning Outcomes UNIT-1: Students will be able to Identify Basic components of the computer and its functionality. Analyze the Basic operations between the memory and processor. Analyze Data transfer between the components. Compute binary arithmetic operations. Recognize Register transfer language notations for data transfer (basic assembly language). Distinguish Instruction formats and different addressing modes. Write Data transfer and manipulation notations . Describe Instruction cycle and arithmetic and logical shift operations. UNIT-2: Students will be able to Outline on Control memory operations. Analyze Program execution sequence . Compare hard wired and micro programmed designs Summarize Basic concepts on memory and differences between those memories. Apply different Cache memory mapping techniques . Recall Virtual memory concepts . Identify Different secondary storage devices UNIT-3: At the end of this unit students will Recall Basic concepts on different input and output devices . Identify Types I/O interfaces . Compare Different kinds of data transfers between the devices . UNIT-4: At the end of the unit student will Know what is an operating system and the role it plays. Use the design aspects of operating system. Use the services provided by operating systems. Exposure to some details of major OS concepts. Learn difference between multiprogramming, multitasking, multithreading, and multiprocessor. Compare and Contrast kernel and user mode in an operating system. Appreciate the need for memory management in operating systems, and the limits of fixed memory allocation schemes. Learn fragmentation in dynamic memory allocation, and dynamic allocation approaches. Learn how program memory addresses relate to physical memory addresses, memory management in base-limit machines, and swapping Techniques. An overview of virtual memory management, including paging and segmentation. Implement Page replacement Algorithms: FIFO, LRU and OPTIMAL Use the different methods of Deadlock recovery. Determine the deadlock by using Resource Allocation Graph. Implement Banker‘s algorithm for Deadlock prevention and Deadlock Avoidance. UNIT-5: At the end of the unit student will Implement the File allocation techniques: sequential, Indexed and Linked. Know how to manage free-space in memory. Learn the structure of Directory and Structure of Files. Describe File sharing and File system mounting. 10.Course mapping with PEOs and POs Mapping of Course to PEOs and Pos Course PEOS POs Computer organization& Operating Systems PEO1,PEO2 PO1,PO3,PO9,PO2,PO4,PO9,po10,PO13, Mapping of Course outcomes to Program Outcomes S.No. Course Outcome POs 1. Explain the basic structure, operation and data representation of a digital computer PO1,po3 2. Perform arithmetic operations on fixed point PO9 and floating point numbers using standard algorithms. 3. Design control unit using micro programming (using micro operations) and proper type of memory Po2,po1 4. Differentiate ways of communicating with IO devices and standard IO interfaces Po4 5. Differentiate cache memory and virtual memory Po9 with the understanding of the hierarchical memory system. 6. Demonstrate the knowledge of functions of operating system memory management scheduling, file system and interface, distributed systems, security and Dead locks Po10 7. Implement a significant portion of an operating system Po10,po13 13.MICROPLAN WITH METHODOLOGY BEING USED/ ADOPTED Date Topic Covered No of Periods Lecture methodology ECE-A(M.Raja Krishna Kumar) 1 23-06-2015 Computer Types, Generations, Functional units 2 BB 2 3 25-06-2015 26-06-2015 Basic operational concepts, Bus structures Softwares 1 1 BB BB 4 27-06-2015 Tutorial Class 1 BB, Learning by doing 5 6 7 30-06-2015 02-07-2015 03-07-2015 Performance ,Multi processor &Computers Fixed &floating point Representation Number system 2 1 1 BB BB BB 04-07-2015 Tutorial Class 1 BB, Learning by doing 07-07-2015 09-07-2015 complements Binary codes 2 1 BB BB 1 BB 2 1 1 2 BB BB BB BB 1 BB 1 BB 8 9 10 UNIT-1 SNO Unit No 11 10-07-2015 12 13 14 15 14-07-2015 16-07-2015 17-07-2015 21-07-2015 16 23-07-2015 17 24-07-2015 Register transfer language, register transfer bus ,memory transfers Arithmetic, logical, shift micro operations Computer registers ,instruction codes Instructions &instruction cycles Memory, i/o references, interrupts Stack organization, instruction formats, addressing modes Data transfer and manipulation Tutorial Class 1 BB, Learning by doing Program control ,RISC Micro programming, program execution sequencing 2 BB 1 BB 31-07-2015 Hard wired and micro programmed designs 1 BB 22 01-08-2015 Tutorial Class 1 BB, Learning by doing 23 04-08-2015 Algorithms for fixed &Floating point addition, subtraction 2 BB 1 1 2 BB BB BB 1 BB 1 2 1 1 BB BB BB BB 1 BB, Learning by doing 2 BB 1 BB 1 BB 19 28-07-2015 20 30-07-2015 21 27 13-08-2015 28 29 30 31 14-08-2015 18-08-2015 20-08-2015 21-08-2015 Multiplication ,division Floating point arithmetic operations Decimal arithmetic unit & operations Semiconductor RAM &ROM memories, hierarchy Cache memory Virtual memories Secondary storage devices Raid levels 32 22-08-2015 Tutorial Class 33 25-08-2015 34 35 UNIT-3 24 25 26 UNIT-2 18 25-07-2015 06-08-2015 07-08-2015 11-08-2015 27-08-2015 28-08-2015 Peripheral devices, i/o interfaces, asynchronous data transfer modes Priority interrupt, DMA I/O processor serial communication, introduction to peripheral components 29-08-2015 Tutorial Class 1 BB, Learning by doing 37 01-09-2015 Introduction to standard serial protocols like rs232,usb,IEEE1394 2 BB 38 03-09-2015 1 BB 39 04-09-2015 Computer System-Overview & Architecture Introduction to OS, Operating System Structure 1 BB System Calls, OS Functions Transition from user to kernel mode Memory management, Swapping Paging, Structure of Page Table Free frames 2 1 1 2 1 BB BB BB BB BB 40 41 42 43 44 UNIT-4 36 08-09-2015 10-09-2015 11-09-2015 15-09-2015 18-09-2015 Tutorial Class 1 BB, Learning by doing 22-09-2015 24-09-2015 25-09-2015 Segmentation Case study Deadlocks, Deadlock Characteristics 2 1 1 BB BB BB 49 26-09-2015 Tutorial Class 1 BB, Learning by doing 50 51 29-09-2015 01-10-2015 Deadlocks avoidance, Detection Deletion algorithm usage 2 1 BB BB 52 03-10-2015 Tutorial Class 1 BB, Learning by doing 06-10-2015 08-10-2015 09-10-2015 09-10-2015 File system interface: concept, structure File system interface: mounting, protection File system implementation File sharing 2 1 1 1 BB BB BB BB 46 47 48 53 54 55 56 Unit-5 45 19-09-2015 Date Topic Covered Lecture methodo logy SNO Unit No No of Periods ECE-B(M.Raja Krishna Kumar) 1 BB 1 1 1 BB BB BB BB, Learning by Doing BB BB BB BB BB, Learning by Doing 22-06-2015 2 3 4 23-06-2015 25-06-2015 26-06-2015 Computer Types, Generations, Functional units Basic operational concepts, Bus structures Softwares Performance ,Multi processor &Computers 5 27-06-2015 Tutorial Class 1 29-06-2015 30-06-2015 02-07-2015 03-07-2015 Fixed &floating point Representation Number system complements Binary codes 1 1 1 1 10 04-07-2015 Tutorial Class 1 11 06-07-2015 12 07-07-2015 6 7 8 9 UNIT-1 1 Register transfer language, register transfer bus ,memory transfers Arithmetic, logical, shift micro operations 1 BB 1 BB 13 14 15 09-07-2015 10-07-2015 13-07-2015 Computer registers ,instruction codes Instructions &instruction cycles Memory, i/o references, interrupts Stack organization, instruction formats, addressing modes 1 1 1 BB BB BB 16 14-07-2015 1 BB 17 18 19 16-07-2015 17-07-2015 20-07-2015 Data transfer and manipulation Program Control RISC 1 1 1 BB 20 21-07-2015 Micro programming, program execution sequencing 1 BB 21 23-07-2015 1 BB 22 24-07-2015 1 BB Hard wired and micro programmed designs Algorithms for fixed &Floating point addition, subtraction BB 25-07-2015 Tutorial Class 1 24 25 26 27-07-2015 28-07-2015 30-07-2015 Multiplication ,division Floating point arithmetic operations Decimal arithmetic unit & operations Semiconductor RAM &ROM memories, hierarchy 1 1 1 1 BB 27 UNIT-2 23 BB, Learning by Doing BB BB BB 31-07-2015 01-08-2015 Tutorial Class 1 29 30 31 32 03-08-2015 04-08-2015 06-08-2015 07-08-2015 1 1 1 1 33 10-08-2015 Cache memory Virtual memories Secondary storage devices Raid levels Peripheral devices, i/o interfaces, asynchronous data transfer modes Priority interrupt, DMA 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB BB, Learning by Doing BB 34 35 UNIT-3 28 BB, Learning by Doing BB BB BB BB 11-08-2015 13-08-2015 21-08-2015 Introduction to standard serial protocols like rs232,usb,IEEE1394 Computer System-Overview & Architecture Introduction to OS, Operating System Structure System Calls, OS Functions 22-08-2015 Tutorial Class 1 24-08-2015 Transition from user to kernel mode 1 14-08-2015 38 18-08-2015 39 20-08-2015 41 42 UNIT-4 36 40 I/O processor serial communication, introduction to peripheral components 25-08-2015 27-08-2015 28-08-2015 Memory management, Swapping Paging, Structure of Page Table Free frames 1 1 1 46 29-08-2015 Tutorial Class 1 47 48 49 50 51 52 53 54 55 31-08-2015 01-09-2015 03-09-2015 04-09-2015 07-09-2015 08-09-2015 10-09-2015 11-09-2015 14-09-2015 Segmentation Case study Deadlocks, Deadlock Characteristics Deadlocks avoidance, Detection Deletion algorithm usage File system interface: concept, structure File system interface: mounting, protection File system implementation File sharing 1 1 1 1 1 1 1 1 1 Unit-5 43 44 45 BB BB BB BB, Learning by Doing BB BB BB BB BB BB BB BB BB ECE-C SNO Unit No 1. UNIT-1 Date Topic Covered 22/06/2015, Computer Types, 24/06/2015 Generations, Functional units No of Periods 2 Lecture methodology BB 2. 25/06/2015 Basic operational concepts, Bus structures 1 BB 3. 26/6/2015 Soft wares 1 BB 4. 27/6/2015 Performance ,Multi processor &Computers 1 BB 5. 29/06/2015 Fixed &floating point Representation 1 BB 6. 1/7/2015 Number system 2 BB 7. 2/7/2015 complements 1 BB 8. 3/7/2015 Binary codes 1 BB 9 4/7/2015 Register transfer language, register transfer bus ,memory transfers 1 BB 10 6/7/2015 Arithmetic, logical, shift micro operations 1 BB 11 8/7/2015 Computer registers ,instruction codes 1 BB 12 9/7/2015 Instructions &instruction cycles 1 BB 13 10/7/2015 Memory, i/o references, interrupts 2 BB 14 11/70/2015, Stack organization, 13/7/2015 instruction formats, addressing modes 2 BB 15 15/7/2015 Data transfer and manipulation 1 BB 16 16/7/2015 Program control ,RISC 1 BB 17 17/7/2015 1 BB 18 20/7/2015, 22/7/2015, 23/7/2015, 24/7/2015. Micro programming, program execution sequencing Hard wired and micro programmed designs 4 BB BB UNIT-2 19 25/7/2015, 27/7/2015. 20 29/7/2015, 30/7/2015. 31/7/2015, 1/8/2015. 3/8/2015, 5/8/2015. 6/8/2015 21 22 23 7/8/2015 24 25 8/8/2015, 10/8/2015, 12/8/2015. 13/8/2015, 14/8/2015. 26 27 17/8/2015, 19/8/2015. Algorithms for fixed &Floating point addition, subtraction Multiplication ,division 2 BB 2 BB Floating point arithmetic operations Decimal arithmetic unit & operations REVISION 2 BB 2 BB BB Semiconductor RAM &ROM memories, hierarchy Cache memory 1 BB BB 3 BB Virtual memories and secondary storage devices Raid levels 2 BB 2 BB UNIT-3 27 BB 20/8/2015, 21/8/2015. Peripheral devices, i/o interfaces, 2 BB 28 22/8/2015, 24/8/2015. 26/8/2015, 27/8/2015. 29 30 28/8/2015 asynchronous data transfer modes Priority interrupt, DMA I/O processor serial communication, introduction to peripheral components Introduction to standard serial protocols like rs232,usb,IEEE1394 2 BB 2 BB 1 BB UNIT-4 31 32 33 BB 29/8/2015 Introduction to OS Computer-system 31/8/2015 overview Computer-system 2/9/2015 architecture - 1 BB 1 BB 1 BB BB 34 35 36 37 38 39 40 41 3/9/2015 Tutorial class 4/9/2015 Discussion hour 1 BB 1 BB Operating 7/9/2015 structure 9/9/2015 System calls 1 BB 1 BB 1 BB 1 BB 1 BB Discussion hour 1 BB Memory management 1 BB Swapping 1 BB Paging 1 BB Free frames 1 BB Structure of page table 1 BB Segmentation 1 BB Case study 1 BB Tutorial class 1 BB system 10/9/2015 Os functions Transition from user 11/9/2015 to kernel mode 12/9/2015 Tutorial class 14/9/2015 42 16/9/2015 43 18/9/2015 44 19/9/2015 45. 46. 47. 48. 49. 21/9/2015 24/9/2015 25/9/2015 26/9/2015 28/9/2015 50 30/9/2015 51 1/10/2015 52 53 54 55 56 57 Unit-5 58 59 60 61 62 63 64 Discussion hour 1 BB Deadlocks 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB Deadlock 3/10/2015 characteristics Deadlocks avoidance 5/10/2015 Deletion algorithm 7/10/2015 usage Tutorial class 8/10/2015 Discussion hour 9/10/2015 Deadlock detection 10/10/2015 File system interface: 12/10/2015 concept, structure File system interface: 14/10/2015 mounting protection 15/10/2015 File system 16/10/2015 implementation Tutorial class 17/10/2015 Discussion hour 19/10/2015 File sharing 23/10/2015 ECE-D SNO Unit No 9. UNIT-1 Date Topic Covered No of Periods 2 Lecture methodology BB 22-06-2015 Computer Types, Generations, Functional units 10. 23-06-2015 Basic operational concepts, Bus structures 1 BB 11. 24-06-2015 Soft wares 1 BB 12. 27-06-2015 Performance ,Multi processor &Computers 1 BB 13. 29-06-2015 Fixed &floating point Representation 1 BB 14. 29-06-2015 30-06-2015 Number system 2 BB 15. 1-07-2015 complements 1 BB 16. 4-07-2015 Binary codes 1 BB 9 06-07-2015 Register transfer language, register transfer bus ,memory transfers 1 BB 10 06-07-2015 07-07-2015 Arithmetic, logical, shift micro operations 2 BB 11 08-07-2015 Computer registers ,instruction codes 1 BB 12 11-07-2015 Instructions &instruction cycles 1 BB 13 13-07-2015 Memory, i/o references, interrupts 2 BB 14 14-07-2015 15-07-2015 Stack organization, instruction formats, addressing modes 2 BB 15 20-07-2015 Data transfer and manipulation 1 BB 16 21-07-2015 Program control ,RISC 1 BB 17 21-07-2015 1 BB 18 22-07-2015 25-07-2015 25-07-2015 27-07-2015 Micro programming, program execution sequencing Hard wired and micro programmed designs 4 BB Algorithms for fixed &Floating point addition, subtraction Multiplication ,division 2 BB 2 BB Floating point arithmetic operations Decimal arithmetic unit & operations REVISION 2 BB 2 BB Semiconductor RAM &ROM memories, hierarchy Cache memory 1 BB 3 BB UNIT-2 19 28-07-2015 29-07-2015 20 1-08-2015 3-08-2015 3-08-2015 4-08-2015 5-08-2015 8-8-2015 10-8-2015 21 22 23 11-08-2015 24 25 12-08-2015 17-08-2015 2 26 18-08-2015 19-08-2015 27 22-08-2015 24-08-2015 Virtual memories and secondary storage devices Raid levels 2 BB 2 BB UNIT-3 BB 27 24-08-2015 25-08-2015 28 26-08-2015 29-08-2015 31-08-2015 1-09-2015 29 30 2-09-2015 Peripheral devices, i/o interfaces, asynchronous data transfer modes Priority interrupt, DMA 2 BB 2 BB I/O processor serial communication, introduction to peripheral components Introduction to standard serial protocols like rs232,usb,IEEE1394 2 BB 1 BB UNIT-4 31 32 33 7-09-2015 Introduction to OS Computer-system 7-09-2015 overview Computer-system 7-09-2015 architecture - 1 BB 1 BB 1 BB BB 34 35 36 37 38 39 40 8-09-2015 Tutorial class 9-09-2015 Discussion hour 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB Discussion hour 1 BB Memory management 1 BB Swapping 1 BB Paging 1 BB Operating 12-09-2015 structure 14-09-2015 System calls system 14-09-2015 Os functions Transition from user to 15-09-2015 kernel mode 16-09-2015 Tutorial class 41 19-09-2015 42 21-09-2015 43 21-09-2015 44 22-09-2015 45. 46. 53 54 55 56 57 64 Segmentation 1 BB Case study 1 BB Tutorial class 1 BB Discussion hour 1 BB Deadlocks 1 BB Deadlock 3-10-2015 characteristics Deadlocks avoidance 5-10-2015 Deletion algorithm 5-10-2015 usage Tutorial class 6-10-2015 Discussion hour 7-10-2015 Deadlock detection 10-10-2015 File system interface: 12-10-2015 concept, structure File system interface: 12-10-2015 mounting protection 14-10-2015 File system 17-10-2015 implementation Tutorial class 19-10-2015 Discussion hour 20-10-2015 File sharing 24-10-2015 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1 BB 1-10-2015 52 63 BB 30-09-2015 51 62 1 29-09-2015 50 61 Structure of page table 28-09-2015 49. 60 BB 28-09-2015 48. 59 1 26-09-2015 47. 58 Free frames 26-09-2015 Unit-5 14.DETAILED NOTES Unit I Basic Structure of Computers Computer Architecture in general covers three aspects of computer design namely: Computer Hardware, Instruction set Architecture and Computer Organization. Computer hardware consists of electronic circuits, displays, magnetic and optical storage media and communication facilities. Instruction set Architecture is programmer visible machine interface such as instruction set, registers, memory organization and exception handling. Two main approaches are mainly CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) Computer Organization includes the high level aspects of a design, such as memory system, the bus structure and the design of the internal CPU. Computer Types Computer is a fast electronic calculating machine which accepts digital input, processes it according to the internally stored instructions (Programs) and produces the result on the output device. The internal operation of the computer can be as depicted in the figure below: Figure 1: Fetch, Decode and Execute steps in a Computer System The computers can be classified into various categories as given below: • Micro Computer • Laptop Computer • Work Station • Super Computer • Main Frame • Hand Held • Multi core Micro Computer: A personal computer; designed to meet the computer needs of an individual. Provides access to a wide variety of computing applications, such as word processing, photo editing, e-mail, and internet. Laptop Computer: A portable, compact computer that can run on power supply or a battery unit. All components are integrated as one compact unit. It is generally more expensive than a comparable desktop. It is also called a Notebook. Work Station: Powerful desktop computer designed for specialized tasks. Generally used for tasks that requires a lot of processing speed. Can also be an ordinary personal computer attached to a LAN (local area network). Super Computer: A computer that is considered to be fastest in the world. Used to execute tasks that would take lot of time for other computers. For Ex: Modeling weather systems, genome sequence, etc (Refer site: http://www.top500.org/) Main Frame: Large expensive computer capable of simultaneously processing data for hundreds or thousands of users. Used to store, manage, and process large amounts of data that need to be reliable, secure, and centralized. Hand Held: It is also called a PDA (Personal Digital Assistant). A computer that fits into a pocket, runs on batteries, and is used while holding the unit in your hand. Typically used as an appointment book, address book, calculator and notepad. Multi Core: Have Multiple Cores – parallel computing platforms. Many Cores or computing elements in a single chip. Typical Examples: Sony Play station, Core2Duo,i3,i7etc Functional Unit A computer in its simplest form comprises five functional units namely input unit, output unit memory unit, arithmetic & logic unit and control unit. Figure 2 depicts the functional units of a computer system. Figure 2: Basic functional units of a computer Let us discuss about each of them in brief: 1. Input Unit: Computer accepts encoded information through input unit. The standard input device is a keyboard. Whenever a key is pressed, keyboard controller sends the code to CPU/Memory. Examples include Mouse, Joystick, Tracker ball, Light pen, Digitizer, Scanner etc. 2. Memory Unit: Memory unit stores the program instructions (Code), data and results of computations etc. Memory unit is classified as: • Primary /Main Memory • • Secondary Memory/Auxiliary Primary memory is a semiconductor memory that provides access at high speed. Run time program instructions and operands are stored in the main memory. Main memory is classified again as ROM and RAM. ROM holds system programs and firmware routines such as BIOS, POST, I/O Drivers that are essential to manage the hardware of a computer. RAM is termed as Read/Write memory or user memory that holds run time program instruction and data. While primary storage is essential, it is volatile in nature and expensive. Additional requirement of memory could be supplied as auxiliary memory at cheaper cost. Secondary memories are non volatile in nature. 3. Arithmetic and logic unit: ALU consist of necessary logic circuits like adder, comparator etc., to perform operations of addition, multiplication, comparison of two numbers etc. 4. Output Unit: Computer after computation returns the computed results, error messages, etc. via output unit. The standard output device is a video monitor, LCD/TFT monitor. Other output devices are printers, plotters etc. 5. Control Unit: Control unit co-ordinates activities of all units by issuing control signals. Control signals issued by control unit govern the data transfers and then appropriate operations take place. Control unit interprets or decides the operation/action to be performed. The operations of a computer can be summarized as follows: 1. A set of instructions called a program reside in the main memory of computer. 2. The CPU fetches those instructions sequentially one-by-one from the main memory, decodes them and performs the specified operation on associated data operands in ALU. 3. Processed data and results will be displayed on an output unit. 4. All activities pertaining to processing and data movement inside the computer machine are governed by control unit. Basic Operational Concepts An Instruction consists of two parts, an Operation code and operand/s as shown below: OPCODE OPERAND/s Let us see a typical instruction ADD LOCA, R0 This instruction is an addition operation. The following are the steps to execute the instruction: Step 1: Fetch the instruction from main memory into the processor Step 2: Fetch the operand at location LOCA from main memory into the processor Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the contents of register R0 Step 4: Store the result (sum) in R0. The same instruction can be realized using two instructions as Load LOCA, R1 Add R1, R0 The steps to execute the instructions can be enumerated as below: Step 1: Fetch the instruction from main memory into the processor Step 2: Fetch the operand at location LOCA from main memory into the processor Register R1 Step 3: Add the content of Register R1 and the contents of register R0 Step 4: Store the result (sum) in R0. Figure 3 below shows how the memory and the processor are connected. As shown in the diagram, in addition to the ALU and the control circuitry, the processor contains a number of registers used for several different purposes. The instruction register holds the instruction that is currently being executed. The program counter keeps track of the execution of the program. It contains the memory address of the next instruction to be fetched and executed. There are n general purpose registers R0 to Rn-1 which can be used by the programmers during writing programs. Figure 3: Connections between the processor and the memory The interaction between the processor and the memory and the direction of flow of information is as shown in the diagram below: Figure 4: Interaction between the memory and the ALU BUS STRUCTURES Group of lines that serve as connecting path for several devices is called a bus (one bit per line). Individual parts must communicate over a communication line or path for exchanging data, address and control information as shown in the diagram below. Printer example – processor to printer. A common approach is to use the concept of buffer registers to hold the content during the transfer. Figure 5: Single bus structure SOFTWARE If a user wants to enter and run an application program, he/she needs a System Software. System Software is a collection of programs that are executed as needed to perform functions such as: • Receiving and interpreting user commands Entering and editing application programs and storing then as files in secondary storage devices • Running standard application programs such as word processors, spread sheets, games etc… Operating system - is key system software component which helps the user to exploit the below underlying hardware with the programs. USER PROGRAM and OS ROUTINE INTERACTION Let‘s assume computer with 1 processor, 1 disk and 1 printer and application program is in machine code on disk. The various tasks are performed in a coordinated fashion, which is called multitasking. t0, t1 …t5 are the instances of time and the interaction during various instances as given below: t0: the OS loads the program from the disk to memory t1: program executes t2: program accesses disk t3: program executes some more t4: program accesses printer t5: program terminates Figure 6 :User program and OS routine sharing of the processor PERFORMANCE The total time required to execute a program is the most important measure of performance for a computer. (t0-t5 of earlier example). Compiler, instruction set and hardware architecture, program all have impact on performance. Basic Performance Equation: The basic performance equation is given by T = (N * S) / R where T=execution time, N=number of instructions, S=average cycles per instruction, R=clock rate in cycles per second CACHING Commonly used data are copied to on-processor memory (cache) to reduce access time. Small memories can be made with higher speed than large ones. In a computer, we need both. Figure 7: The processor cache PIPELINING and SUPERSCALR OPERATION Pipelining: Like a production line, instruction execution overlapped so greater parallelism is achieved. Superscalar operation: Execute several instructions simultaneously using multiple ALU‘s. CISC vs RISC Reduced instruction set computer – Large N, small S Complex instruction set computer – Small N, large S COMPILER Translates high level language such as C, C++ and Java to machine instructions. Aims to reduce N×S PERFORMANCE MEASUREMENT Benchmark refers to standard task used to measure how well a processor operates. To evaluate the performance of Computers, a non-profit organization known as SPEC-System Performance Evaluation Corporation employs agreedupon application programs of real world for benchmarks. Accordingly, it gives performance measure for a computer as the time required to execute a given benchmark program. The SPEC rating is computed as follows Register Transfer and Micro operations Register Transfer Language • • • • • • • • • • • Digital systems are composed of modules that are constructed from digital components, such as registers, decoders, arithmetic elements, and control logic The modules are interconnected with common data and control paths to form a digital computer system The operations executed on data stored in registers are called micro operations A micro operation is an elementary operation performed on the information stored in one or more registers Examples are shift, count, clear, and load Some of the digital components from before are registers that implement micro operations The internal hardware organization of a digital computer is best defined by specifying o The set of registers it contains and their functions o The sequence of micro operations performed on the binary information stored o The control that initiates the sequence of micro operations Use symbols, rather than words, to specify the sequence of micro operations The symbolic notation used is called a register transfer language A programming language is a procedure for writing symbols to specify a given computational process Define symbols for various types of micro operations and describe associated hardware that can implement the micro operations Register Transfer 3. Designate computer registers by capital letters to denote its function 4. The register that holds an address for the memory unit is called MAR 5. The program counter register is called PC 6. IR is the instruction register and R1 is a processor register 7. The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-1 8. Refer to Figure 4.1 for the different representations of a register • Designate information transfer from one register to another by R2 ← R1 • This statement implies that the hardware is available o The outputs of the source must have a path to the inputs of the destination o The destination register has a parallel load capability • If the transfer is to occur only under a predetermined control condition, designate it by If (P = 1) then (R2 ← R1) or, P: R2 ← R1, where P is a control function that can be either 0 or 1 • Every statement written in register transfer notation implies the presence of the required hardware construction • • It is assumed that all transfers occur during a clock edge transition All microoperations written on a single line are to be executed at the same time T: R2 ← R1, R1 ← R2 Bus and Memory Transfers • • • • • • • • • Rather than connecting wires between all registers, a common bus is used A bus structure consists of a set of common lines, one for each bit of a register Control signals determine which register is selected by the bus during each transfer Multiplexers can be used to construct a common bus Multiplexers select the source register whose binary information is then placed on the bus The select lines are connected to the selection inputs of the multiplexers and choose the bits of one register In general, a bys system will multiplex k registers of n bits each to produce an n-line common bus This requires n multiplexers – one for each bit The size of each multiplexer must be k x 1 • • The number of select lines required is log k To transfer information from the bus to a register, the bus lines are connected to the inputs of all destination registers and the corresponding load control line must be activated • Rather than listing each step as BUS ← C, R1 ← BUS, use R1 ← C, since the bus is implied • • • • • • • • Instead of using multiplexers, three-state gates can be used to construct the bus system A three-state gate is a digital circuit that exhibits three states Two of the states are signals equivalent to logic 1 and 0 The third state is a high-impedance state – this behaves like an open circuit, which means the output is disconnected and does not have a logic significance The three-state buffer gate has a normal input and a control input which determines the output state With control 1, the output equals the normal input With control 0, the gate goes to a high-impedance state This enables a large number of three-state gate outputs to be connected with wires to form a common bus line without endangering loading effects • • • • Decoders are used to ensure that no more than one control input is active at any given time This circuit can replace the multiplexer in Figure 4.3 To construct a common bus for four registers of n bits each using three-state buffers, we need n circuits with four buffers in each Only one decoder is necessary to select between the four registers • • Designate a memory word by the letter M It is necessary to specify the address of M when writing memory transfer operations • Designate the address register by AR and the data register by DR • The read operation can be stated as: Read: DR ← M[AR] • The write operation can be stated as: Write: M[AR] ← R1 Arithmetic Micro operations • There are four categories of the most common microoperations: o Register transfer: transfer binary information from one register to another o Arithmetic: perform arithmetic operations on numeric data stored in registers o Logic: perform bit manipulation operations on nonnumeric data stored in registers o Shift: perform shift operations on data stored in registers • • • • • • • The basic arithmetic microoperations are addition, subtraction, increment, decrement, and shift Example of addition: R3 ← R1 +R2 Subtraction is most often implemented through complementation and addition Example of subtraction: R3 ← R1 + R2 + 1 (strikethrough denotes bar on top – 1‘s complement of R2) Adding 1 to the 1‘s complement produces the 2‘s complement Adding the contents of R1 to the 2‘s complement of R2 is equivalent to subtracting Multiply and divide are not included as microoperations • • • • • • • • • A microoperation is one that can be executed by one clock pulse Multiply (divide) is implemented by a sequence of add and shift microoperations (subtract and shift) To implement the add microoperation with hardware, we need the registers that hold the data and the digital component that performs the addition A full-adder adds two bits and a previous carry A binary adder is a digital circuit that generates the arithmetic sum of two binary numbers of any length A binary added is constructed with full-adder circuits connected in cascade An n-bit binary adder requires n full-adders The subtraction A-B can be carried out by the following steps o Take the 1‘s complement of B (invert each bit) o Get the 2‘s complement by adding 1 o Add the result to A The addition and subtraction operations can be combined into one common circuit by including an XOR gate with each fulladder • The increment microoperation adds one to a number in a register • This can be implemented by using a binary counter – every time the count enable is active, the count is incremented by one • If the increment is to be performed independent of a particular register, then use half-adders connected in cascade An n-bit binary incremented requires n half-adders • • • • Each of the arithmetic micro operations can be implemented in one composite arithmetic circuit The basic component is the parallel adder Multiplexers are used to choose between the different operations The output of the binary adder is calculated from the following sum: D = A + Y + Cin Logic Microoperations • • • Logic operations specify binary operations for strings of bits stored in registers and treat each bit separately Example: the XOR of R1 and R2 is symbolized by P: R1 ← R1 ⊕ R2 Example: R1 = 1010 and R2 = 1100 1010 Content of R1 1100 Content of R2 0110 Content of R1 after P = 1 • Symbols used for logical microoperations: o OR: ∨ o AND: ∧ o XOR: ⊕ • The + sign has two different meanings: logical OR and summation • When + is in a microoperation, then summation • When + is in a control function, then OR • Example: P + Q: R1 ← R2 + R3, R4 ← R5 ∨ R6 • There are 16 different logic operations that can be performed with two binary variables • • The hardware implementation of logic micro operations requires that logic gates be inserted for each bit or pair of bits in the registers All 16 micro operations can be derived from using four logic gates Logic micro operations can be used to change bit values, delete a group of bits, or insert new bit values into a register • The selective-set operation sets to 1 the bits in A where there are corresponding 1‘s in B 1010 A before 1100 B (logic operand) 1110 A after A ← A ∨ B • The selective-complement operation complements bits in A where there are corresponding 1‘s in B 1010 A before 1100 B (logic operand) 0110 A after A ← A ⊕ B • The selective-clear operation clears to 0 the bits in A only where there are corresponding 1‘s in B 1010 A before 1100 B (logic operand) 0010 A after A←A∧B • The mask operation is similar to the selective-clear operation, except that the bits of A are cleared only where there are corresponding 0‘s in B 1010 A before 1100 B (logic operand) 1000 A after A ← A ∧ B • • The insert operation inserts a new value into a group of bits This is done by first masking the bits to be replaced and then Oring them with the bits to be inserted 0110 1010 A before 0000 1111 B (mask) 0000 A after 1010 masking 0000 1010 A before 1001 0000 B (insert) 1001 A after 1010 insertion • The clear operation compares the bits in A and B and produces an all 0‘s result if the two number are equal 1010 A 1010 B 0000 A ← A ⊕ B Shift Micro operations • • Shift micro operations are used for serial transfer of data They are also used in conjunction with arithmetic, logic, • • • • • • • • • • • and other data-processing operations There are three types of shifts: logical, circular, and arithmetic A logical shift is one that transfers 0 through the serial input The symbols shl and shr are for logical shift-left and shiftright by one position R1 ← shl R1 The circular shift (aka rotate) circulates the bits of the register around the two ends without loss of information The symbols cil and cir are for circular shift left and right The arithmetic shift shifts a signed binary number to the left or right To the left is multiplying by 2, to the right is dividing by 2 Arithmetic shifts must leave the sign bit unchanged A sign reversal occurs if the bit in Rn-1 changes in value after the shift This happens if the multiplication causes an overflow An overflow flip-flop Vs can be used to detect the overflow Vs = Rn-1 ⊕ Rn-2 • • • • • A bi-directional shift unit with parallel load could be used to implement this Two clock pulses are necessary with this configuration: one to load the value and another to shift In a processor unit with many registers it is more efficient to implement the shift operation with a combinational circuit The content of a register to be shifted is first placed onto a common bus and the output is connected to the combinational shifter, the shifted number is then loaded back into the register This can be constructed with multiplexers 15 Arithmetic Logic Shift Unit • • • • The arithmetic logic unit (ALU) is a common operational unit connected to a number of storage registers To perform a micro operation, the contents of specified registers are placed in the inputs of the ALU The ALU performs an operation and the result is then transferred to a destination register The ALU is a combinational circuit so that the entire register transfer operation from the source registers through the ALU and into the destination register can be performed during one clock pulse period UNIT-IV What is an Operating System? A program that acts as an intermediary between a user of a computer and the computer hardware Operating system goals: Execute user programs and make solving user problems easier Make the computer system convenient to use Use the computer hardware in an efficient manner Computer System Structure Computer system can be divided into four components Hardware – provides basic computing resources CPU, memory, I/O devices Operating system Controls and coordinates use of hardware among various applications and users Application programs – define the ways in which the system resources are used to solve the computing problems of the users Word processors, compilers, web browsers, database systems, video games Users People, machines, other computers Four Components of a Computer System Operating System Definition OS is a resource allocator Manages all resources Decides between conflicting requests for efficient and fair resource use OS is a control program Controls execution of programs to prevent errors and improper use of the computer No universally accepted definition Everything a vendor ships when you order an operating system‖ is good approximation but varies wildly. ―The one program running at all times on the computer‖ is the kernel. Everything else is either a system program (ships with the operating system) or an application program. Computer System Organization Computer-system operation One or more CPUs, device controllers connect through common bus providing access to shared memory Concurrent execution of CPUs and devices competing for memory cycles Computer-System Operation I/O devices and the CPU can execute concurrently Each device controller is in charge of a particular device type Each device controller has a local buffer CPU moves data from/to main memory to/from local buffers I/O is from the device to local buffer of controller Device controller informs CPU that it has finished its operation by causing An interrupt Interrupt Handling The operating system preserves the state of the CPU by storing registers and the program counter Determines which type of interrupt has occurred: polling vectored interrupt system Separate segments of code determine what action should be taken for each type of interrupt Interrupt Timeline Storage Hierarchy Storage systems organized in hierarchy Speed Cost Volatility Caching – copying information into faster storage system; main memory can be viewed as a last cache for secondary storage Caching Important principle, performed at many levels in a computer (in hardware, operating system, software) Information in use copied from slower to faster storage temporarily Faster storage (cache) checked first to determine if information is there If it is, information used directly from the cache (fast) If not, data copied to cache and used there Cache smaller than storage being cached Cache management important design problem Cache size and replacement policy Computer-System Architecture Most systems use a single general-purpose processor (PDAs through mainframes) Most systems have special-purpose processors as well Multiprocessors systems growing in use and importance Also known as parallel systems, tightly-coupled systems Advantages include 1.Increased throughput degradation or fault tolerance Two types 2.Economy of scale 1.Asymmetric Multiprocessing How a Modern Computer Works Symmetric Multiprocessing Architecture 3.Increased reliability – graceful 2.Symmetric Multiprocessing A Dual-Core Design Clustered Systems Like multiprocessor systems, but multiple systems working together Usually sharing storage via a storage-area network (SAN) Provides a high-availability service which survives failures Asymmetric clustering has one machine in hot-standby mode Symmetric clustering has multiple nodes running applications, monitoring each other Some clusters are for high-performance computing (HPC) Applications must be written to use parallelization Operating System Structure Multiprogramming needed for efficiency Single user cannot keep CPU and I/O devices busy at all times Multiprogramming organizes jobs (code and data) so CPU always has one to Execute A subset of total jobs in system is kept in memory One job selected and run via job scheduling When it has to wait (for I/O for example), OS switches to another job Timesharing (multitasking) is logical extension in which CPU switches jobs so frequently that users can interact with each job while it is running, creating interactive computing Response time should be < 1 second Each user has at least one program executing in memory [process If several jobs ready to run at the same time [ CPU scheduling If processes don‘t fit in memory, swapping moves them in and out to run Virtual memory allows execution of processes not completely in memory Memory Layout for Multiprogramming System Operating-System Operations Interrupt driven by hardware Software error or request creates exception or trap Division by zero, request for operating system service Other process problems include infinite loop, processes modifying each Other or the operating system Dual-mode operation allows OS to protect itself and other system components User mode and kernel mode Mode bit provided by hardware Provides ability to distinguish when system is running user code or kernel code Some instructions designated as privileged, only executable in kernel mode System call changes mode to kernel, return from call resets it to user Transition from User to Kernel Mode Timer to prevent infinite loop / process hogging resources Set interrupt after specific period Operating system decrements counter When counter zero generate an interrupt Set up before scheduling process to regain control or terminate program that exceeds allotted time System Calls Programming interface to the services provided by the OS Typically written in a high-level language (C or C++) Mostly accessed by programs via a high-level Application Program Interface (API) rather than direct system call usenThree most common APIs are Win32 API for Windows, POSIX API for POSIX-based systems (including virtually all versions of UNIX, Linux, and Mac OS X), and Java API for the Java virtual machine (JVM) Why use APIs rather than system calls?(Note that the system-call names used throughout this text are generic) Example of System Calls API – System Call – OS Relationship Memory Management To provide a detailed description of various ways of organizing memory hardware To discuss various memory-management techniques, including paging and segmentation To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging Program must be brought (from disk) into memory and placed within a process for it to be run Main memory and registers are only storage CPU can access directly Register access in one CPU clock (or less) Main memory can take many cycles Cache sits between main memory and CPU registers Protection of memory required to ensure correct operation Base and Limit Registers A pair of base and limit registers define the logical address space Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses can happen at three different stages Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes Load time: Must generate relocatable code if memory location is not known at compile time Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers) Multistep Processing of a User Program Logical vs. Physical Address Space The concept of a logical address space that is bound to a separate physical address space is central to proper memory management Logical address – generated by the CPU; also referred to as virtual address Physical address – address seen by the memory unit Logical and physical addresses are the same in compile-time and load-time addressbinding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme Swapping A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued executionnBacking store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory imagesnRoll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executednMajor part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swappednModified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows) System maintains a ready queue of ready-to-run processes which have memory images on disk Schematic View of Swapping Contiguous Allocation Main memory usually into two partitions: Resident operating system, usually held in low memory with interrupt vector User processes then held in high memorynRelocation registers used to protect user processes from each other, and from changing operating-system code and data Base register contains value of smallest physical address Limit register contains range of logical addresses – each logical address must be less than the limit register MMU maps logical address dynamically Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size Produces the smallest leftover hole Worst-fit: Allocate the largest hole; must also search entire list Produces the largest leftover hole First-fit and best-fit better than worst-fit in terms of speed and storage utilization Fragmentation External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time. I/O problem Latch job in memory while it is involved in I/O Do I/O only into OS buffers Paging Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8,192 bytes) Divide logical memory into blocks of same size called pagesnKeep track of all free frames To run a program of size n pages, need to find n free frames and load program Set up a page table to translate logical to physical addresses Internal fragmentation Paging Hardware Paging Model of Logical and Physical Memory Paging Example 32-byte memory and 4-byte pages Free Frames Implementation of Page Table Page table is kept in main memory Page-table base register (PTBR) points to the page table Page-table length register (PRLR) indicates size of the page table In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process Associative Memory Associative memory – parallel search Address translation (p, d) If p is in associative register, get frame # out Otherwise get frame # from page table in memory Page # Frame # Paging Hardware With TLB Effective Access Time Associative Lookup = e time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers Hit ratio = an Effective Access Time (EAT) EAT = (1 + e) a + (2 + e)(1 – a) =2+e–a Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page table: ―valid‖ indicates that the associated page is in the process‘ logical address space, and is thus a legal page ―invalid‖ indicates that the page is not in the process‘ logical address space Valid (v) or Invalid (i) Bit In A Page Table Shared Pages Example Structure of the Page Table Hierarchical Paging Hashed Page Tables Inverted Page Tables Hierarchical Page Tables Break up the logical address space into multiple page tables A simple technique is a two-level page table Two-Level Page-Table Scheme Two-Level Paging Example A logical address (on 32-bit machine with 1K page size) is divided into: a page number consisting of 22 bits a page offset consisting of 10 bits Since the page table is paged, the page number is further divided into: a 12-bit page number a 10-bit page offset Thus, a logical address is as follows: where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table page number pi 12 Address-Translation Scheme Three-level Paging Scheme Hashed Page Tables page offset p2 d 10 10 Common in address spaces > 32 bits The virtual page number is hashed into a page table This page table contains a chain of elements hashing to the same location Virtual page numbers are compared in this chain searching for a match If a match is found, the corresponding physical frame is extracted Hashed Page Table Inverted Page Table One entry for each real page of memory Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs Use hash table to limit the search to one — or at most a few — page-table entries Inverted Page Table Architecture Segmentation Memory-management scheme that supports user view of memory A program is a collection of segments A segment is a logical unit such as: main program procedure function method object local variables, global variables common block stack symbol table arrays Segmentation Architecture Logical address consists of a two tuple: o <segment-number, offset>, Segment table – maps two-dimensional physical addresses; each table entry has: base – contains the starting physical address where the segments reside in memory limit – specifies the length of the segment Segment-table base register (STBR) points to the segment table‘s location in memory Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR Protection With each entry in segment table associate: validation bit = 0 Þ illegal segment read/write/execute privileges Protection bits associated with segments; code sharing occurs at segment level Since segments vary in length, memory allocation is a dynamic storage-allocation problem A segmentation example is shown in the following diagram Segmentation Hardware Example of Segmentation Example: The Intel Pentium Supports both segmentation and segmentation with paging CPU generates logical address Given to segmentation unit Which produces linear addresses Linear address given to paging unit Which generates physical address in main memory Paging units form equivalent of MMU Logical to Physical Address Translation in Pentium Intel Pentium Segmentation Linear Address in Linux Three-level Paging in Linux Deadlock To develop a description of deadlocks, which prevent sets of concurrent processes from completing their tasks.To present a number of different methods for preventing or avoiding deadlocks in a computer system The Deadlock Problem A set of blocked processes each holding a resource and waiting to acquire a resource held by another process in the set. Example :System has 2 disk drives P1 and P2 each hold one disk drive and each needs another one Example :semaphores A and B, initialized to 1 P0 P wait (A); wait(B) wait (B); wait(A) System Model Resource types R1, R2, . . ., Rm.CPU cycles, memory space, I/O devices Each resource type Ri has Wi instances.Each process utilizes a resource as follows: request use release Deadlock Characterization Deadlock can arise if four conditions hold simultaneously Mutual exclusion: only one process at a time can use a resource Hold and wait: a process holding at least one resource is waiting to acquire additional resources held by other processes No preemption: a resource can be released only voluntarily by the process holding it, after that process has completed its task Circular wait: there exists a set {P0, P1, …, P0} of waiting processes such that P0 is waiting for a resource that is held by P1, P1 is waiting for a resource that is held by P2, …, Pn–1 is waiting for a resource that is held by Pn, and P0 is waiting for a resource that is held by P0. Deadlock Prevention Restrain the ways request can be made Mutual Exclusion – not required for sharable resources; must hold for nonsharable resources Hold and Wait – must guarantee that whenever a process requests a resource, it does not hold any other resources.Require process to request and be allocated all its resources before it begins execution, or allow process to request resources only when the process has none.Low resource utilization; starvation possible Deadlock Avoidance Requires that the system has some additional a priori information available.Simplest and most useful model requires that each process declare the maximum number of resources of each type that it may need.The deadlock-avoidance algorithm dynamically examines the resource-allocation state to ensure that there can never be a circular-wait condition.Resourceallocation state is defined by the number of available and allocated resources, and the maximum demands of the processes Resource-Allocation Graph Algorithm nSuppose that process Pi requests a resource Rj.The request can be granted only if converting the request edge to an assignment edge does not result in the formation of a cycle in the resource allocation graph Banker’s Algorithm nMultiple instancesnEach process must a priori claim maximum usenWhen a process requests a resource it may have to wait nWhen a process gets all its resources it must return them in a finite amount of time Data Structures for the Banker’s Algorithm Let n = number of processes, and m = number of resources types. nAvailable: Vector of length m. If available [j] = k, there are k instances of resource type Rj availablenMax: n x m matrix. If Max [i,j] = k, then process Pi may request at most k instances of resource type RjnAllocation: n x m matrix. If Allocation[i,j] = k then Pi is currently allocated k instances of RjnNeed: n x m matrix. If Need[i,j] = k, then Pi may need k more instances of Rj to complete its task.Need [i,j] = Max[i,j] – Allocation [i,j] Safety Algorithm 1. Let Work and Finish be vectors of length m and n, respectively. Initialize:Work = Available Finish [i] = false for i = 0, 1, …, n- 1 2. Find and i such that both: (a) Finish [i] = false(b) Needi £ Work If no such i exists, go to step 4 3. Work = Work + Allocationi Finish[i] = true go to step 2 4. If Finish [i] == true for all i, then the system is in a safe state Detection Algorithm 1. Let Work and Finish be vectors of length m and n, respectively Initialize:(a) Work = Available(b) For i = 1,2, …, n, if Allocationi ¹ 0, then Finish[i] = false;otherwise, Finish[i] = true2. Find an index i such that both:(a) Finish[i] == false(b) Requesti £ WorkIf no such i exists, go to step 4 3. Work = Work + Allocationi Finish[i] = true go to step 24. If Finish[i] == false, for some i, 1 £ i £ n, then the system is in deadlock state. Moreover, if Finish[i] == false, then Pi is deadlocked Algorithm requires an order of O(m x n2) operations to detect whether the system is in deadlocked state Example of Detection Algorithm nFive processes P0 through P4; three resource types A (7 instances), B (2 instances), and C (6 instances) lCan reclaim resources held by process P0, but insufficient resources to fulfill other processes; requests lDeadlock exists, consisting of processes P1, P2, P3, and P4 Detection-Algorithm Usage nWhen, and how often, to invoke depends on: lHow often a deadlock is likely to occur? lHow many processes will need to be rolled back? one for each disjoint cyclenIf detection algorithm is invoked arbitrarily, there may be many cycles in the resource graph and so we would not be able to tell which of the many deadlocked processes ―caused‖ the deadlock. UNIT-V File system Interface To explain the function of file systems To describe the interfaces to file systems To discuss file-system design tradeoffs, including access methods, file sharing, file locking, and directory structures To explore file-system protection. File Concept Contiguous logical address spacenTypes: lData numeric character binary Program File Structure nNone - sequence of words, bytes Simple record structure Lines Fixed length Variable length Complex Structures Formatted document Relocatable load file Can simulate last two with first method by inserting appropriate control characters Who decides: Operating system, Program. Access Methods nSequential Access read next, write next ,reset , no read after last write, (rewrite) nDirect Access read n, write n, position to n, read next,write next ,rewrite n. n = relative block number Sequential-access File Example of Index and Relative Files Directory Structure A collection of nodes containing information about all files Both the directory structure and the files reside on disk Backups of these two structures are kept on tapes Disk Structure Disk can be subdivided into partitions Disks or partitions can be RAID protected against failure. Disk or partition can be used raw – without a file system, or formatted with a file system Partitions also known as minidisks, slices Entity containing file system known as a volume Each volume containing file system also tracks that file system‘s info in device directory or volume table of contents As well as general-purpose file systems there are many special-purpose file systems, frequently all within the same operating system or computer. File System Mounting A file system must be mounted before it can be accessed A unmounted file system (i.e. Fig. 11-11(b)) is mounted at a mount point (a)Existing. (b) Unmounted Partition Mount Point File Sharing Sharing of files on multi-user systems is desirablenSharing may be done through a protection scheme On distributed systems, files may be shared across a networknNetwork File System (NFS) is a common distributed filesharing method File Sharing – Multiple Users User IDs identify users, allowing permissions and protections to be per-user Group IDs allow users to be in groups, permitting group access rights. File Sharing – Remote File Systems Uses networking to allow file system access between systems Manually via programs like FTP Automatically, seamlessly using distributed file systems Semi automatically via the world wide web Protection File owner/creator should be able to control: what can be done by whom n Types of access, Read Write ,Execute ,Append ,Delete ,List 15.ADDITIONAL TOPICS 16. UNIVERSITY QUESTON PAPERS OF PREVIOIUS YEARS 17.QUESTION BANK 1. (a) Differentiate between microprogramming and nano programming. (b) Hardwired control unit is faster than micro programmed control unit. Justify this statement. 2.What are the different types of Mapping Techniques used in the usage of Cache Memory? Explain. 3. (a) Draw the block diagram of a computer system and describe each of its parts along with their functions. Also designate the information flow between the parts with arrows. (b) Explain the term `memory bus bottleneck'. 4. (a) Explain commonly employed bit shift operators such as shift left, right, circular shift left/right and arithmetic shift left/right. Give 8-bit examples. (b) Design a circuit for combined shift left/right operations. Assume register length is 4 bits and employ RS flip-flops. 5. Draw circuit for BCD addition and subtraction. Explain its functionality with mathematical background. 6. (a) What are the different types of I/O communication techniques? Give brief notes. (b) In the above techniques, which is the most efficient? Justify your answer. 7. (a) Explain the variety of techniques available for sequencing of microinstructions based on the format of the address information in the microinstruction. (b) Hardwired control unit is faster than microprogammed control unit. Justify this statement. 8. (a) If cache access time is 70 ns, memory access time is 700ns. i. Compute the formula for average access time. ii. Compute hit and miss ratios if the average access time is 140ns (b) Show the memory hierarchy and give the brief explanation. 9. What do you mean by instruction set architecture (ISA). What is the completeness? and orthogonality with respect to ISA. What are the design issues related to ISA? 10. (a) Find the actual number from its IEEE 754 representation. Sign = 0 Exponent = 1000 0000 Mantissa = 1100 0000 0000 0000 0000 000 (b) What is meant by normalization in oating point representation? Why do we need it? What is bias? What normalization is used in IEEE 754 standard? 11.a) Give a detailed account of how a digital computer is organized and explain its functions clearly. b) Give a detailed explanation of Data Representation in a digital computer with suitable examples. 12. Explain the organization of 4 bit combinational circuit shifter. Illustrate its functioning with an example. 13. Explain the following with examples: a) Micro Operations b) Micro Instructions c) Micro Program d) Micro Code. 14. With the aid of a flow chart explain either addition or subtraction operation of floating point numbers at hard ware level. 15. Explain in detail the organization of a functioning of secondary storage media. 16. Write notes on the following communication protocols: a) RS 232 b) USB c) IEEE 1394. 17.Draw and explain program flow of control without and with interrupts. 18.What is Multiprogramming, Multi Tasking and Multiprocessing. 19.What is Operating System? What are the goals of OS. 20.Write Operating System services and functions. 21.What is System call? Explain the categories of System call. 22.Explain Operating System Structure. 23.What is Virtual memory? Explain Demand Paging technique. 24.Explain the following terms a) Fragmentation b) Swapping c) Thrashing 25. Explain segmentation scheme for memory management. Give the segmentation hardware. 26. Explain Page Replacement Algorithm. a) FIFO b) Optimal c)LRU 27.. What is paging? Write the Structure of the page table 28.What is Deadlock? Explain Deadlock characteristics. 29.What is deadlock? How is it prevented and detected. 30. Explain Deadlock avoidance problem. 31.Explain the method of recovery from Deadlock 32.Explain the concept of a file and access methods. 33.Explain the structure of file and directory. 34.Explain file sharing and file system mounting. 35.Explain the method of free space management. 36. Explain the allocation methods. 18.Assignment Topics 1. Define: Program, Instruction set, Hardware & software. 2. List out the main function of an Operating System. 3. Explain in details the function units of computer with the help of the diagram. 4. Explain in brief the concept of stored program. 5. Differentiate between Primary Memory & Secondary Memory. 6. Write to state characteristics of primary memory. 7. Explain in brief the characteristics of storage. 8. Define: System Nucleus, swapping. 9. Write a short note on device controller (Draw necessary diagram). 10. Explain in brief device interface signals. 11. Explain in brief the meaning of following terms. 1. I/O Device 2. Word length 3. Memory Capacity 4. Access Time 5. Settling Time 6. Cycle Time 7. Bandwidth 12. Explain in brief synchronous interface & Asynchronous interface. 13. What is Memory Addressability? 14. Explain Interface Cycle in detail with the help of diagrams. 15. Explain in brief two steps of CPU. 16. What is CPU Registers? 17. What is Cache Memory? 18. Write short note on CPU registers (draw a diagram) 19. Define: Frequency, Time period, Pulse width and Duty cycle. 20. What is Macro Operation? Explain Micro operation with the help of example. 21. What is Interrupt Service Routing? 22. Explain in details the concept of interrupt OR Explain in brief 1. Interrupt service routing, 2. Nested interrupt 3. Interrupt priority 4. Interrupt masking 5. Interrupt non-masking. 23. Write a short note on method of data transfer or explain in details software method to transferred data. 24. Explain in brief the following terms. 1. I/O Routing 2. I/O Drivers 3. I/O Ports 25. What is BUS? Explain in brief a concept of BUS with help of simple structure OR Explain in brief the functions of Address BUS, Data BUS & Control BUS. 26. Explain in brief the concept of BUS cycle. 27. Explain in brief the characteristics of different type of computer (each three have any one). 28. Explain in brief the factors are response to improve the performance of a computer. 29. What is Multiprogramming, Multi Tasking and Multiprocessing. 30. -What is Operating System? What are the goals of OS. 31. Write Operating System services and functions. 32. What is System call? Explain the categories of System call. 33. Explain Operating System Structure. 34.What is Virtual memory? Explain Demand Paging technique. 35.Explain the following terms a) Fragmentation b) Swapping c) Thrashing 36. Explain about segmentation. 37. Explain Page Replacement Algorithm. a) FIFO b) Optimal c)LRU 38. What is paging? Write the Structure of the page table. 39. What is Deadlock? Explain Deadlock characteristics. 40.What is deadlock? How is it prevented and detected. 41. Explain Deadlock avoidance problem. 42.Explain the method of recovery from Deadlock. 43.Explain the concept of a file and access methods. 44.Explain the structure of file and directory. 45.Explain file sharing and file system mouting. 46.Explain the method of free space management. 47. Explain the allocation methods. 19.UNIT WISE QUIZ QUESTIONS AND LONG ANSWER QUESTIONS Q.1Floating point representation is used to store (A) Boolean values (B) whole numbers (C) real integers (D) integers Ans: C Q.2 In computers, subtraction is generally carried out by (A) 9‘s complement (B) 10‘s complement (C) 1‘s complement (D) 2‘s complement Ans: D Q. 3 (2FAOC)16 is equivalent to (A) (195 084)10 (B) (001011111010 0000 1100)2 (C) Both (A) and (B) (D) None of these Ans: B Q.4 Which of the following is not a weighted code? (A) Decimal Number system (B) Excess 3-cod (C) Binary number System (D) None of these Ans: B Q.5 Von Neumann architecture is (A) SISD (B) SIMD (C) MIMD (D) MISD Ans: A Q.6 In signed-magnitude binary division, if the dividend is (11100)2 and divisor is (10011)2then the result is (A) (00100)2 (B) (10100)2 (C) (11001)2 (D) (01100)2 Ans: B Q.7 Logic X-OR operation of (4ACO)H & (B53F)H results (A) AACB (B) 0000 (C) FFFF (D) ABCD Ans: C Q.8When CPU is executing a Program that is part of theOperating System, it is said to be in (A)Interrupt mode (B)System mode (C)Half mode (D)Simplex mode Ans: B Q.9In computers, subtraction is carried out generally by (A)1's complement method (B)2's complement method (C)signed magnitude method (D)BCD subtraction method Ans: B Q.10The circuit converting binary data in to decimal is (A)Encoder (B)Multiplexer (C)Decoder (D)Code converter Ans: D Q.11Translation from symbolic program into Binary is done in (A) Two passes. (B) Directly (C) Three passes. (D) Four passes Ans: A Q.12 A floating point number that has a O in the MSB of mantissa is said to have (A) Overflow (B) Underflow (C) Important number (D) Undefined Ans: B Q.13 A binary digit is called a (A) Bit (B) Byte (C) Number (D) Character Ans: A Q14.(-27)10can be represented in a signed magnitude format andin a 1‘s complement format as (A)111011 & 100100 (B)100100 & 111011 (C)011011 & 100100 (D) 100100 & 011011 Ans:A Q15.The 2s compliment form (Use 6 bit word) of the number 1010 is (A) 111100. (B) 110110. (C) 110111. (D) 1011. Ans:B Q.15 In Reverse Polish notation, expression A*B+C*D is written as (A) AB*CD*+ (B) A*BCD*+ (C) AB*CD+* (D) A*B*CD+ Ans: A Q.16Assembly language (A) uses alphabetic codes in place of binary numbers used in machine language (B) is the easiest language to write programs (C) need not be translated into machine language Ans :a Q.17 Computers use addressing mode techniques for (A) giving programming versatility to the user by providing facilities as pointers to memory counters for loop control (B) to reduce no. of bits in the field of instruction (C) specifying rules for modifying or interpreting address field of the instruction (D) All the above Ans: D Q.18 _________ register keeps track of the instructions stored in program stored in memory. (A) AR (Address Register) (B) XR (Index Register) (C) PC (Program Counter) (D) AC (Accumulator) Ans: C Q.19 The addressing mode used in an instruction of the form ADD X Y, is (A) Absolute (B) indirect (C) index (D) none of these Ans: C Q.20 A Stack-organised Computer uses instruction of (A) Indirect addressing (B) Two-addressing (C) Zero addressing (D) Index addressing Ans: C Q.21 PSW is saved in stack when there is a (A)interrupt recognised (B)execution of RST instruction (C)Execution of CALL instruction (D)All of these Ans: A Q.22_________ register keeps tracks of the instructions stored in program stored in memory. (A) AR (Address Register) (B) XR (Index Register) (C) PC (Program Counter) (D) AC (Accumulator) Ans: C Q.23The instruction ‗ORG O‘ is a (A) Machine Instruction. (B) Pseudo instruction. (C) High level instruction. (D) Memory instruction. Ans: B Q.24The BSA instruction is (A)Branch and store accumulator (B)Branch and save return address (C)Branch and shift address (D)Branch and show accumulator Ans: B Q.25The load instruction is mostly used to designate a transfer from memory to a processor register known as (A) Accumulator (B) Instruction Register (C) Program counter (D) Memory address Register Ans: A Q26.Data input command is just the opposite of a (A) Test command (B) Control command (C) Data output (D) Data channel Ans: C Q.27MRI indicates (A)Memory Reference Information. (B)Memory Reference Instruction. (C)Memory Registers Instruction. (D)Memory Register information Ans: B Q.28 If the value V(x) of the target operand is contained in the address field itself, the addressing mode is (A)immediate. (B)direct. (C)indirect. (D) implied. Ans:B Q29.The instructions which copy information from one location to another either in the processor‘s internal register set or in the external main memory are called (A)Data transfer instructions. (B)Program control instructions. (C)Input-output instructions. (D)Logical instructions. Ans:A Q.30A group of bits that tell the computer to perform aspecific operation is known as (A) Instruction code (B) Micro-operation (C) Accumulator (D) Register Ans: A Q.31he communication between the components in a microcomputer takes place via the address and (A) I/O bus (B) Data bus (C) Address bus (D) Control lines Ans: B Q.32 A microprogram sequencer (A)generates the address of next micro instruction to be executed. (B)generates the control signals to execute a microinstruction. (C)sequentially averages all microinstructions in the control memory. (D)enables the efficient handling of a micro program subroutine. Ans: A Q33. Microinstructions are stored in control memory groups, with each group specifying a (A) Routine (B) Subroutine (C) Vector (D) Address Ans: A Q.34Status bit is also called (A) Binary bit (B) Flag bit (C) Signed bit (D) Unsigned bit Ans: B Q35.The maximum addressing capacity of a micro processor which uses 16 bit database & 32 bit address base is (A)64 K. (B)4 GB. (C)both (A)& (B) .(D)None of these. Ans:B Q36. A microprogram is sequencer perform the operation... A) read B) write C) read and write D) read and execute Ans :D Q37) The Purpose of Co-operating Process is __________. 1 Information Sharing 2 Convenience 3 Computation Speed-Up 4 All of the above Right Ans ) 4 Q38) The kernel of the operating system remains in the primary memory because ________. 1 It is mostly called (used) 2 It manages all interrupt calls 3 It controls all operations in process 4 It is low level Right Ans ) 1 Q39) The process related to process control, file management, device management, information about system and communication that is requested by any higher level language can be performed by __________. 1 Editors 2 Compilers 3 System Call 4 Caching Right Ans ) 3 Q40) The operating system of a computer serves as a software interface between the user and the ________. 1 Hardware 2 Peripheral 3 Memory 4 Screen Right Ans ) 1 Q41) Super computers typically employ _______. 1 Real time Operating system 2 Multiprocessors OS 3 desktop OS 4 None of the above Right Ans ) 2 Q42) A process that is based on IPC mechanism which executes on different systems and can communicate with other processes using message based communication, is called ________. 1 Local Procedure Call 2 Inter Process Communication 3 Remote Procedure Call 4 Remote Machine Invocation Right Ans ) 3 Q43) A process is 1 program in execution 2 a concurrent program 3 any sequential program 4 something which prevents deadlock Right Ans ) 1 Q44) Round robin scheduling is essentially the preemptive version of ________. 1 FIFO 2 Shortest job first 3 Shortes remaining 4 Longest time first Right Ans ) 1 Q45) A page fault occurs 1 when the page is not in the memory 2 when the page is in the memory 3 when the process enters the blocked state 4 when the process is in the ready state Right Ans ) 1 Q46) Which of the following will determine your choice of systems software for your computer ? 1 Is the applications software you want to use compatible with it ? 2 Is it expensive ? 3 Is it compatible with your hardware ? 4 Both 1 and 3 Right Ans ) 4 Q47) Let S and Q be two semaphores initialized to 1, where P0 and P1 processes the following statements wait(S);wait(Q); ---; signal(S);signal(Q) and wait(Q); wait(S);---;signal(Q);signal(S); respectively. The above situation depicts a _________ . 1 Semaphore 2 Deadlock 3 Signal 4 Interrupt Right Ans ) 2 Q48) What is a shell ? 1 It is a hardware component 2 It is a command interpreter 3 It is a part in compiler 4 It is a tool in CPU scheduling Right Ans ) 2 Q49) Routine is not loaded until it is called. All routines are kept on disk in a relocatable load format. The main program is loaded into memory & is executed. This type of loading is called _________ 1 Static loading 2 Dynamic loading 3 Dynamic linking 4 Overlays Right Ans ) 3 Q50) In the blocked state 1 the processes waiting for I/O are found 2 the process which is running is found 3 the processes waiting for the processor are found 4 none of the above Right Ans ) 1 Q51) What is the memory from 1K - 640K called ? 1 Extended Memory 2 Normal Memory 3 Low Memory 4 Conventional Memory Right Ans ) 4 Q52) Virtual memory is __________. 1 An extremely large main memory 2 An extremely large secondary memory 3 An illusion of extremely large main memory 4 A type of memory used in super computers. Right Ans ) 3 Q53) The process related to process control, file management, device management, information about system and communication that is requested by any higher level language can be performed by __________. 1 Editors 2 Compilers 3 System Call 4 Caching Right Ans ) 3 Q54) If the Disk head is located initially at 32, find the number of disk moves required with FCFS if the disk queue of I/O blocks requests are 98,37,14,124,65,67. 1 310 2 324 3 315 4 321 Right Ans ) 4 Q55) Multiprogramming systems ________. 1 Are easier to develop than single programming systems 2 Execute each job faster 3 Execute more jobs in the same time 4 Are used only on large main frame computers Right Ans ) 3 Q56) Which is not the state of the process ? 1 Blocked 2 Running 3 Ready 4 Privileged Right Ans ) 4 Q57) The solution to Critical Section Problem is : Mutual Exclusion, Progress and Bounded Waiting. 1 The statement is false 2 The statement is true. 3 The statement is contradictory. 4 None of the above Right Ans ) 2 Q58) The problem of thrashing is effected scientifically by ________. 1 Program structure 2 Program size 3 Primary storage size 4 None of the above Right Ans ) 1 Q59) The state of a process after it encounters an I/O instruction is __________. 1 Ready 2 Blocked/Waiting 3 Idle 4 Running Right Ans ) 2 Q60) The number of processes completed per unit time is known as __________. 1 Output 2 Throughput 3 Efficiency 4 Capacity Right Ans ) 2 Q61) _________ is the situation in which a process is waiting on another process,which is also waiting on another process ... which is waiting on the first process. None of the processes involved in this circular wait are making progress. 1 Deadlock 2 Starvation 3 Dormant 4 None of the above Right Ans ) 1 Q62) Which of the following file name extension suggests that the file is Backup copy of another file ? 1 TXT 2 COM 3 BAS 4 BAK Right Ans ) 4 Q63) Which technique was introduced because a single job could not keep both the CPU and the I/O devices busy? 1 Time-sharing 2 SPOOLing 3 Preemptive scheduling 4 Multiprogramming Right Ans ) 4 Q64) A critical region 1 is a piece of code which only one process executes at a time 2 is a region prone to deadlock 3 is a piece of code which only a finite number of processes execute 4 is found only in Windows NT operation system Right Ans ) 1 Q65) The mechanism that bring a page into memory only when it is needed is called _____________ 1 Segmentation 2 Fragmentation 3 Demand Paging 4 Page Replacement Right Ans ) 3 Q66) PCB = 1 Program Control Block 2 Process Control Block 3 Process Communication Block 4 None of the above Right Ans ) 2 Q67) FIFO scheduling is ________. 1 Preemptive Scheduling 2 Non Preemptive Scheduling 3 Deadline Scheduling 4 Fair share scheduling Right Ans ) 2 Q68) Switching the CPU to another Process requires to save state of the old process and loading new process state is called as __________. 1 Process Blocking 2 Context Switch 3 Time Sharing 4 None of the above Right Ans ) 2 Q69) Which directory implementation is used in most Operating System? 1 Single level directory structure 2 Two level directory structure 3 Tree directory structure 4 Acyclic directory structure Right Ans ) 3 Q70) The Banker¿s algorithm is used 1 to prevent deadlock in operating systems 2 to detect deadlock in operating systems 3 to rectify a deadlocked state 4 none of the above Right Ans ) 1 Q71) A thread 1 is a lightweight process where the context switching is low 2 is a lightweight process where the context switching is high 3 is used to speed up paging 4 none of the above Right Ans ) 1 Q72) ______ is a high level abstraction over Semaphore. 1 Shared memory 2 Message passing 3 Monitor 4 Mutual exclusion Right Ans ) 3 20.REFERENCES, JOURNALS, WEBSITES AND E-LINKS IF ANY WEBSITES: 1. https://www.cs.dal.ca/~mheywood/CSCI3121. 2. uic.edu.hk/~hpguo/teaching/spring2011/co/index.html 3. The Journal of Computer and System Sciences (JCSS) is a peerreviewed scientific journal in the field of computer science. JCSS is published by Elsevier,Gödel Prize.[1], 1967. 4. The Computing Research and Education Association of Australasia. July 2008. http://www.core.edu.au/journal%20rankings/Journal%20Rankings. html. Retrieved 22 August 2009.[dead link] REFERENCES 1.computer organization and architecture-William Stallings 6th Edition, Pearson