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A Stable System Clock Generator Using Reference Clock
Sampling
Aatmesh Shrivastava and Alicia Klinefelter
ECE 6332 – Fall 2010
University of Virginia
<as4xz, amk5vx>@virginia.edu
ABSTRACT
In this project carried out the design of an on-chip accurate system
clock using a frequency locked loop. The proposed design uses an
off-chip crystal oscillator as its reference clock which can be
turned off once the FLL is locked to the reference frequency. The
proposed scheme saves power that gets dissipated in the
generation of the clock by an order of magnitude. We also
implemented a temperature compensating scheme which would
not allow the frequency of the clock to drift.
(DAC) switch and a proportional to absolute temperature (PTAT)
current source. The system consumes less than 2uW of power and
achieves a frequency stability of +/-250ppm which is better than
[5] both in terms of energy with a stability comparable to a crystal
oscillator.
2. THE CLOCKING SCHEME
Figure 2 shows the proposed clocking circuit. It operates in three
phases.
done
1. INTRODUCTION
Crystal oscillators [1], have long been used to generate reference
clocks for almost all types of systems viz. microprocessors,
microcontrollers, peripheral control interfaces (PIC) etc. The
reference clock is usually multiplied many times using a phase
locked loop (PLL) to generate a system clock. The ability of
crystal oscillators to provide an extremely stable clock is the
primary reason for its prevalence. However, a crystal oscillator
consumes significant amounts of power to operate, which
increases exponentially with frequency Figure 1 shows the power
consumption of a crystal oscillator with respect to frequency.
Counter
ADC
Register
Block
DAC
done
Clock coming from
crystal or RF
source
F to V
Converter
I
1
_
PTAT
Op. Amp.
VCO
0
+
F to V
Converter
II
control
out
Figure 2. Proposed Clocking Circuit.
Figure 1. Power with Respect to Frequency in a Crystal
Oscillator.
In general, generating system clocks is a significant power
overhead and various techniques to reduce this power have been
studied in [2], [3]. This problem is accentuated further in
applications such as wireless sensor nodes (WSNs) which are now
operating on harvested energy [4]. Such systems operate at lower
frequencies with much reduced power. Therefore much emphasis
is placed on reducing power when designing clocking systems for
wireless sensor nodes [5]. There is also an opportunity to trade-off
clock stability with power.
We present a novel clocking scheme for low power systems such
as WSN with a 200KHz clock as an example. The proposed
scheme is implemented using a frequency locked loop (FLL) [6],
analog-to-digital converter (ADC), and digital-to-analog converter
Calibration Phase: This is the start-up phase of the circuit and
becomes operational when the done signal coming from the ADC
goes low, indicating the end of conversion. The clock then comes
to the first frequency to voltage converter (FVC) which is
implemented using a Djemouai FVC [6]. The source of clock can
be a crystal oscillator or an RF receiver or any other source. The
FVC-I produces a stable voltage proportional to the clock and this
becomes an input to the amplifier. The amplifier then controls the
voltage controlled oscillator (VCO) which in turn feeds FVC-II in
a negative feedback configuration. This configuration ensures that
VCO’s output clock is of the same frequency as of input clock.
The amplifier eventually settles to a stable output voltage for the
VCO.
Conversion Phase: Once the amplifier settles its output voltage, it
is fed to the ADC that converts it into a digital signal. This digital
signal is then used to regenerate the signal at the DAC.
Retention Phase: When conversion is complete done goes high,
and the VCO is fed by the DAC rather than amplifier. At this
point the amplifier, FVCs, counter and ADC are disabled. The
DAC controls the oscillation through the VCO. This is done to
reduce the power consumption.
A PTAT is used to control the frequency drift due to temperature.
3. DESIGN COMPONENTS
3.1 Frequency to Voltage converter
3.3 Voltage Controlled Oscillator
Figure 3 shows a Djemouai [6] frequency to voltage converter. It
uses a current source and works on the principle of capacitive
charge sharing.
Figure 5 shows the schematic of the VCO used in the design using
a current starved architecture. The oscillation frequency is
controlled by the value of the current source that is determined by
the gate to source voltage of transistor MN. This current is
mirrored in MP. In this way the architecture eliminates the
dependence of oscillation frequency on power supply and ensures
that the rising edge and falling edge in the VCO’s delay element is
controlled by the same current. This ensures a 50% duty cycle for
the VCO, a condition necessary to obtain the correct output
frequency. We use five delay elements in our VCO.
Figure 3. Frequency-to-Voltage Converter.
During the period when the clock is low, capacitor C1 gets
charged to voltage
VOUT=IsT/2*C=Is/2*f*C
…(i)
When clock goes high, charge is shared between C1 and C2.
Finally C1 is discharged to ground and this process repeats every
cycle. C2 is eventually charged to the max voltage, VOUT , which
is inversely proportional to the clock frequency given by (i).
Figure 3 shows the circuit diagram of the FVC, its functioning
and output.
3.2 OPAMP
In order to reduce the error between the VCO’s clock frequency
and reference clock frequency a very high gain operation, an
amplifier is needed for this system. Figure 4 shows the folded
cascade operational amplifier which was used because it gives
high gain and supports a wide common mode range. We achieve a
DC-gain of 100dB with a phase margin of 80o. A proper value of
Cp ensures the stability of the whole system.
Figure 5. Voltage Controlled Oscillator.
3.4 ADC
The three most commonly used ADC architectures are flash
(parallel), successive approximation (SAR), and sigma delta.
Since one of the goals is to reduce power, the flash architecture
was immediately discounted. The sigma-delta architecture was
considered due to its high-accuracy and high bit resolution.
Although low-power designs have been presented in [14], the
digital filtering and oversampling required makes the design both
complex and high-area. The SAR ADC is simpler in terms of
components required and the overall accuracy of the system is
determined by the accuracy of the DAC and the gain of the
comparator.
...
SAR Logic
DAC
_
analog
input
+
Figure 6: SAR ADC Block Diagram.
3.4.1.1 SAR Logic
Figure 4. Folded Cascode Opamp.
The SAR logic block runs the SAR algorithm for the system. This
algorithm is used to slowly converge on analog input voltage. The
ADC first assumes a voltage of half of the reference voltage
(binary 100…000). The SAR logic forces this value to the DAC
that turns it into an analog voltage. If the input voltage is greater
than this voltage then the output at the comparator will be a “1”,
else it will be a “0”. The SAR logic then works to set this bit to
the output of the comparator and then make an assumption about
the following bit. This new bit string with the newly determined
bit and new assumption gets passed to the DAC for the next
approximation. The algorithm completes after the LSB has been
determined.
3.4.1.2 DAC
This architecture often requires a sample-hold circuit to ensure
that the voltage is stable during the conversion cycle. One
substitution that is often used for this is to use a charge-scaling
capacitive DAC to replace this circuit [13]. This circuit requires a
reset signal to discharge the capacitors before conversion and also
has binary weight capacitors. As the resolution increases, the
capacitor size increases exponentially and this can cause
Vout
The system begins estimating with the MSB and moving towards
the estimation of the LSB. When the comparator output goes low,
it indicates an over-estimation and the current bit is then set to 0.
While the comparator stays high for a conversion stage, that bit
stays at 1. The accuracy of the system is determined by the ability
to accurately determine the least significant bits.
For a series of test voltages the ADC performed with no more
than a 2mV error of the expected bit values. The results of testing
can be seen in Table 1.
Table 1. Sample ADC Expected and Experimental Values.
1024C
512C
rst
2C
b9
b10
C
C
b1
b0
Vref
Figure 7: Charge Scaling Architecture for 10-bit DAC.
Analog
Voltage
Expected
Digital
Actual
Digital
0V
0000000000
0000000011
2mV
381 mV
0110000111
0110000111
381 mV
500 mV
1000000000
1000000000
500mV
712 mV
1011011001
1011010111
710 mV
1V
1111111111
1111111111
999mV
3.4.1.3 Comparator
Since the comparator would be comparing the output of the DAC
and the analog input voltage to make a bit decision, it was
important to choose a design that high gain and accurate. One
design that was small and intuitive was the design in Figure 3.
This design uses two NMOS differential stage amplifiers and one
PMOS differential stage amplifier (both with current mirror
loads). Since both of these have different input common-mode
ranges, different voltage values will not be amplified with the
same gain. The first comparator determines which op-amp to use
(P or N) and then allows the output of that op-amp to be the
output of the comparator to ensure equal gain to any input signal
in the range [0V, 1V]. This comparator operates with a reference
voltage of 500mV.
Actual
Analog
3.5 Digital-to-Analog Conversion
Although we had already designed a DAC for the ADC, this DAC
architecture was not ideal for converting the voltage stored in the
registers once the source had been turned off. The charge scaling
DAC has the problem of needing to be refreshed and reset often
for use. We designed another DAC that uses a similar voltage
division principle except using a resistive R-2R ladder network.
At each stage of the DAC the bits that are asserted determine what
fraction of the reference voltage appears at the output.
R
R
R
R
2R
Vout
2R
2R
2R
2R
3.4.1.4 Testing and Results
We tested the final ADC for a number of test cases: 0V, 381mV,
500mV, 712mV, and 1V. With ten bits it was easy to know what
was expected at the output. In Figure 8 it can be seen how the
system converges to the final value of 381mV.
b10
b9
b1
b0
Vref
Figure 9. R-2R Ladder DAC Architecture.
SAR ADC Converging Algorithm
1.2
Analog In
Comp. Out
DAC Out
4. SYSTEM LEVEL SIM RESULTS
1
AMP OUT
voltage (V)
0.8
FVC-I
0.6
FVC-II
0.4
0.2
Figure 10. a) Transient behavior b) steady state of VCO
0
0
0.2
0.4
0.6
time (ms)
0.8
1
1.2
-3
x 10
Figure 8: ADC Converging Input Voltage for Input of 381mV.
Figure 10 a) shows the output in a system level simulation by
hooking all the blocks together. It can be seen that output FVC-I
quickly settles to its DC voltage while FVC-II takes some time
before settles to it eventually settles to it DC voltage. Figure 10 b)
shows the clock output of VCO and the reference clock, which are
same.
5. TEMPERATURE COMPENSATION
The circuit is expected to operate in the retention phase most of
the time. In this phase oscillation is controlled by the DAC output
voltage which remains constant once it is calibrated. However we
do not expect temperature to be constant during operation. Due to
the variation in temperature, the output frequency of the VCO
drifts away from its calibrated point. It is therefore necessary to
compensate for this temperature variation.
The current drive of a MOS transistor typically reduces with
temperature when operated in strong inversion. In order to
compensate this behavior we use a current source which increases
with temperature PTAT [7].
can incorporate non-ideal behavior in the design. These are global
process variation and local mismatch.
6.1.1.1 Global Variation
The global process variation mainly impacts the temperature
compensation scheme of the design. The process can be strong or
weak because the contribution of current from the PTAT in the
ZTC current source would increase or decrease leading to the
current in the VCO to increase or decrease with temperature. In
order to address this issue we propose to calibrate the value of
resistor RB in the PTAT in Figure 11 based on global process
parameters.
6.1.1.2 Local Mismatch
The local mismatch will produce an offset and set an error in the
VCO clock frequency when compared to the reference clock. It is
not prudent to address the local mismatch issue at each block level
[6]. We propose to cancel the effect of local mismatch by
carefully programming the current source in FVC II Figure 2 and
Figure 3. By changing the value of the current source we create an
offset in opposite directions and cancel the offset created by local
mismatch.
7. SUMMARY
Figure 11. PTAT circuit and its output
Figure 11 shows the schematic of the circuit used in the design.
The circuit is very simple and can operate at very low quiescent
currents, which is the reason it was chosen. The output current of
this circuit is given by (ii) [7].
IB=IB0*{1+γ(T-T0)} ………………………..(ii)
By summing this current with the MOS transistor current, which
decreases with temperature, we obtain a zero temperature
coefficient (ZTC) current source.
We presented a fully integrated clocking scheme for low-power
application such as WSNs. The design was carried out in a 130nm
bulk CMOS process. Design addresses process, temperature,
voltage variation (PTV). It also takes into account the effect of
local mismatch. The system achieves a frequency stability of +/250 ppm and consumes <2uW power while supplying the clock.
8. ACKNOWLEDGMENTS
Our thanks to Professor Calhoun and Joe Ryan for providing
guidance and useful criticisms throughout the project.
9. REFERENCES
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Figure 12. a) ZTC current, 7b) VCO output at 0, 50 and 100oC
Figure 12 shows the obtained ZTC current and clock output at
different temperatures. The frequency of the clock changes by
from 200 KHz to 201 KHz over a temperature variation of 0 to
100oC which is equal to +/-250ppm.
6. ADDRESSING VARIABILITY
Temperature and power supply variation of the proposed scheme
are addressed through design architecture and are explained in the
preceding sections. However there are two more variations that
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