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Wires & wire delay
Lecture 9
Tuesday September 27, 2016
Outline
• Introduction
• Interconnect Modeling
– Wire Resistance
– Wire Capacitance
• Introducing a distributed wire RC p-model
• Estimating wire RC delay assuming a dominant
time constant
• Elmore delay model – a generalized model
• Handling wire branches
• Inserting repeaters to keep wire lengths short
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Introduction to Integrated Circuit Design
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Introduction
• Chips are mostly made of wires called interconnect
– In stick diagram, wires set size
– Transistors are little things under the wires
– Many layers of wires
Odd metal wires
– Speed
– Power
– Noise
• Alternating layers run orthogonally
September 2016
Introduction to Integrated Circuit Design
Even metal wires
• Wires are as important as transistors
3
Modern interconnect
Metal 6
Via 5-6
Metal 5
Metal 4
Metal 3
Metal 2
Metal 1
Via 1-2
Local Tungsten interconnect
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Choice of metals
• Until 180 nm generation, most wires were aluminum
• Contemporary processes normally use copper
– Cu atoms diffuse into silicon and damage FETs
– Must be surrounded by a diffusion barrier
Metal
Bulk resistivity (mW•cm)
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Titanium (Ti)
43.0
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Layer stack
• AMS 0.35 mm process has 3 metal layers
– M1 for within-cell routing
– M2/M3 for vertical/horizontal routing between cells
• Modern processes use 6-10+ metal layers
– M1: thin, narrow (< 1.5*minimum feature size)
• High density wiring in cells
– Mid layers: thick, wide
• Global interconnect
– Top layers: THICK, WIDE
• For VDD, GND, clk
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Sheet resistance
Just count number of
squares along wire
and multiply with RS
When W=L the
resistance is equal
to R0, the sheet
resistance (i.e. the
resistance of a
square wire)
R= L
t W
H
Sheet Resistance
R
Other books use RS
Ro0=/t
L
H
t
R1
W
All wires in a layer
have the same
thickness t
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W
R2
W
L
Introduction to Integrated Circuit Design
L
7
Wire geometry
Pitch = w + s
w
w>>t
t
Old technology
Modern technology
Today: pack in many skinny wires!
For long skinny wires resistance cannot be
neglected since cross sectional area shrinks
with feature size, wire length stays the same or
increases. Hence: we need a wire RC model
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Example
• Compute the sheet resistance of a 0.22 mm thick Cu wire
in a 65 nm process.
The resistivity of thin film Cu is 22 nW.m.
2.2 108 Ω  m
R 
 0.10 W/
6
0.22 10 m
• Find the total resistance if the wire is 0.125 mm wide and 1
mm long. (Ignore the barrier layer)
1000 m m
R   0.10 Ω/ 
 800 W
0.125 m m
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Wire delay scaling – Local wires
stays constant
Wire
length L,
width W
Wire
length L/S,
width W/S
R
 L/S
t W /S
• For local wire crossing the same amount of circuitry
– Resistance stays roughly constant
• Length decreases by same amount as width, height stays large
and/or change material to copper
– Capacitance decreases by scaling factor
C  WCox  L / S
• Cap/unit length stays constant, length decreases
• Wire delay tracks improvement in gate delay stays constant
From Mark Horowitz at Design Automation Conference 2000
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Introduction to Integrated Circuit Design
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From Mark Horowitz at Design Automation Conference 2000
Wire delay scaling – Global wires
stays constant
Wire
length L,
width W
Wire
length L,
width W/S

L
R
t W /S
• For global wire crossing the whole chip
– Resistance grows linearly (with scaling factor)
– Capacitance stays fixed
C  WCox  L
• Wire delay increases relative to gate delay
stays constant
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Modern Interconnect
No of nets
(Log Scale)
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Global Interconnect
SGlobal = SDie
Source: Intel
SLocal = STechnology
10
100
1,000
10,000
100,000
Length (u)
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Wire capacitance
Bottom plate and fringe capacitance
(a)
Wire has capacitance c per unit length
• to neighbors
• to layers above and below
Parallel plate capacitance equation
• C = eoxA/d
•
H
W - H/2
+
(b)
eox=ke0, k≈4 for SiO2, low-kappa k<3
Note: Cap is per unit length
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Introduction to Integrated Circuit Design
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Metal2 Capacitance Data
• Typical wires have ~ 0.2 fF/mm, i. e. 200 fF/mm
– Compare with 1.2 fF/mm for MOSFET gate cap
400
Data shown for s = 320, 480, 640 nm, and s = ∞
s
350
300
M1, M3 planes
Metal 3
s = 320
250
s = 480
s=
200
8
s = 640
h2
layer n+1
Ctop
Isolated
s = 320
150
t
layer n
s = 480
s = 640
100
s=
8
Ctotal (aF/mm)
w
h1
Cbot
Cadj
Metal 1
50
layer n-1
0
0
500
1000
1500
2000
w (nm)
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Wire RC delay
In any given technology
• wire RC increases as L2 with wire length L
• r is wire resistance per unit length
• c is wire resistance per unit length
R  RS
L
 rL
W
C  WCox  L  cL
2
RC = rcL
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Step-response of RC wire as a function
of time and space
2.5
x= L/10
2
voltage (V)
x = L/4
1.5
x = L/2
1
x= L
0.5
0
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0
0.5
1
1.5
2
2.5
3
time (nsec)
3.5
Introduction to Integrated Circuit Design
4
4.5
5
16
Wire delay example
• Estimate the delay of a 9X inverter driving a 4x inverter at
the end of the 1 mm wire! WN=0.78 mm. WP=2WN.
Assume
c=becomes
200 fF/mm,
r=800 W/mm from previous example
Without wire
wire,cap
delay
5 ps*(pinv+X4/X9)=5*(0.8+4/9)=
6.2 ps
9X driver inverter
4X receiver inverter
1 mm long, 125 nm wide Cu wire
9X
CG
4X
2.2 kW
1.4 fF
Reff
CD
2.6 fF
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Wire delay example
• Estimate the delay of a 9X inverter driving a 4x inverter at
the end of the 1 mm wire! WN=0.78 mm. WP=2WN.
Without wire, delay becomes 5 ps*(pinv+X4/X9)=5*(0.8+4/9)= 6.2 ps
With wire cap, electrical effort increases with 200 fF/(9*0.36 fF) = 62
Delay becomes ~316 ps!
9X driver inverter
4X receiver inverter
0.8 kW
9X
4X
Reff
2.2 kW
Rwire
1.4 fF
CG
CD
2.6 fF
100 fF
100 fF
What if wire resistance is added?
Delay increases further with 0.7*(0.8*101.4) = 56 ps to 372 ps
September 2016
Introduction to Integrated Circuit Design
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Wire delay example
• Estimate the delay of a 9X inverter driving a 4x inverter at
the end of the 1 mm wire! WN=0.78 mm. WP=2WN.
driver
inverter
1 mm long, 125 nm wide Cu wire
9X
receiver
inverter
4X
Wires are distributed systems
For with
analytical
solution:
Approximate
lumped
element models
use single
segment
p-model
In Spice simulations
a 3-segment
p-model
is accurate to 3%
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Elmore delay model
• Estimate the delay of a 9X inverter driving a 4x inverter at the
end of the 1 mm wire! WN=0.78 mm. WP=2WN.
• Use Elmore delay model to calculate RC constant for each R:
• Multiply each resistance with its downstream capacitance!
9X driver inverter
Reff
V0
p-wire model
4X receiver inverter
Rw
CD
Cw/2
CG
Cw/2
 1  Reff  CD  Cw  CG   Rw  Cw / 2  CG 
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Wire delay example
• Estimate the delay of a 9X inverter driving a 4x inverter at the
end of the 1 mm wire! WN=0.78 mm. WP=2WN.
• RC product = (2.2 kW)(204 fF) + (0.8 kW)(101.4 fF) = 530 ps
• Propagation delay = 0.7RC = 372 ps
2.2 kW
0.8 kW
Reff
Rwire
X9
September 2016
CD
2.6 fF
100 fF
CG
100 fF
Introduction to Integrated Circuit Design
1.4 fF
X4
21
Elmore delay model – from where?
• Simplify the two-stage RC circuit!
• Write nodal equations!
C1
V V V V
dV1
 sC1V1  in 1  1 2
dt
R1
R2
C2
R1
Vin
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R2
V1
V2
sC1
Introduction to Integrated Circuit Design
dV2
V V
 sC2V2  1 2
dt
R2
sC2
22
Elmore delay model – from where?
• Simplify the two-stage RC circuit!
• Write nodal equations!
1
1

sC


 1 R R
• Matrix form
1
2

R1
Vin
September 2016
R2
V1




1
R2

 Vin 
 V


  1    R1C1 

1   V2  
sC2 

0 

R2 

1
R2
V2
sC1
Introduction to Integrated Circuit Design
sC2
23
Elmore delay model – from where?
•
•
•
•
Simplify the two-stage RC circuit!
Write nodal equations!
1

s


R2C2
 V1  1 
Matrix form

 
Invert matrix for V1 and V2!  V2  D  1
R1
Vin
R2
V1
 R2C2

  Vin 
  R1C1 

1
1  
s

0 


R1C1 R2C1 
1
R2C1
V2
sC1
sC2
2
Characteristic equation: D=det M=0 R1R2C1C2 s  s  R1  C1  C2   R2C2   1  0
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Elmore delay model – from where?
Amplitude
• Exact solution is sum of two exponentials with time constants
1=1/s1 and 2=1/s2
• As you already know, poles s1 and s2 are often well separated!
• Hence, 1>>2 and dominating!
VOUT  VDD e  t /1
Bode plot
s1
Dominating frequency:
September 2016
s1 
s2
frequency
1
R1  C1  C2   R2C2
Introduction to Integrated Circuit Design
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Elmore delay model – from where?
• Approximate solution:
– exponential with dominating time constant 1
• Each resistance is multiplied with its downstream
capacitance!
 t / 1
R1
R2
V1
V2  VDD e
Vin
C1
C2
 1  R1  C1  C2   R2C2
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Approximative solution
with dominating time constant
One example:
R1=0.8R2, C1=1.2C2
t1=2.45, t2=0.31
Compare two-pole solution to dominating exponential
1
2_pole
Elmore
OUTPUT VOLTAGE
0.75
0.5
0.25
0
0
2
4
6
8
10
TIME
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Elmore delay model formulation 2
Alternate memory rule:
 1  R1C1   R1  R2  C2
R1
R2
V1
C1
V2
C2
This is another formulation of Elmore´s delay model:
Each capacitance is multiplied with its upstream resistance.
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Introduction to Integrated Circuit Design
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Ideal wire delay
• Wire delay increases as L2 with wire length!
• Keep wires short!
R1=0
Rwire
Cwire/2
V2
Cwire/2
Most
often(R11=0)
>>and
For an ideal voltage
source
C1dominating!
=C2=Cwire/2 we get wire delay
2 and
twire
September 2016
RwireCwire
rc 2


L
2
2
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Summary
• We have introduced a wire p-RC model
• We have analytically solved for delayed output
response
• We simplified using dominant time constant
• We arrived at Elmore´s wire delay model!
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Using Elmore delay model
• “What if I change driving capability of the X9 inverter, what
driving capability will minimize the propagation.”
• X9 RC product = (2.2 kW)(206 fF) + (0.8 kW)(103.2 fF) = 536 ps
• General RC product = Reff*(Cwire+2CG)+Rwire*(Cwire+2CG)/2
R
Cwire
wire
Reff CG
• New
RC product
= 0.17×(200+84)+0.8×(100+42)=34+14+80+34≈160
ps
Has minimum
when
Reff*Cwire=Rwire*CG, i.e. for Reff 
2.2 kW
0.17
kW
Reff
X118
X9
0.8 kW
Rwire
CD
42 fF
3.2
100 fF
CG
100 fF
slightly changed
capacitance values
42 fF
3.2
fF
X9
X118
Reff CG=7.2 ps, RwireCwire=160 ps → Reff =0.17 kW, CG=7.2/0.17= 42 fF
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Using Elmore delay model
• What if I cut wire in two pieces? Total RC goes from 160 ps to
136 ps
0.17 kW
0.4 kW
Reff
X118
Rwire
C
42 fF
CG
50 fF
50 fF
42 fF
X118
+
New RC product = 0.17×(100+84)+0.4×(50+42)=17+14+20+17≈78 ps
0.17 kW
Reff
X118
0.4 kW
Rwire
C
42 fF
50 fF
CG
50 fF
42 fF
X118
New RC product = 0.17×(100+84)+0.4×(50+42)=17+14+20+17≈78 ps
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Making Elmore delay model general
“input"
VIN
dV1 Vin  V1 V1  V2


dt
R1
R2
dV2 V1  V2 V2  Vout
R1
V1
C2


dt
R2
R3
dV V  V3
C1
R2
V2
C3 3  2
dt
R3
C1
C2
R3
C3
V3=VOUT
output
1. Write nodal equations for all nodes
2. Then multiply each nodal equation with
its upstream resistance from the node
to the voltage source
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Making Elmore delay model general
dV1
V1  V2
R1C1
 Vin  V1 
dt
R2 / R1
V V
dV
V V
 R1  R2  C2 2  V1  V2  1 2  2 out
dt
R2 / R1 R3 /  R1  R2 
dVout
V2  Vout
 V2  Vout 
 R1  R2  R3  C3
dt
R3 /  R1  R2 
 k
 dVk
 Vout  Vin
Add equations    Ri Ck
dt
k 1  i 1

3
1st order linear diff equation
 k
 dVout
R

  i Ck dt  Vout  Vin
k 1  i 1

3
Elmore time constant
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Handling branches
Theory behind rule of thumb for handling branches:
Add equation for node 4
dV4 V2  V4
C4

dt
R4
“input"
VIN
R1
R4
V1
C1
R2
Modify node equation for node 2
C4
V2
C2
dV2 V1  V2 V2  Vout V2  V4
C2



dt
R2
R3
R4
V4
R3
C3
V3=VOUT
output
V2  Vout
dV2
V1  V2
V2  V4
 V1  V2 


 R1  R2  C2
dt
R2 / R1 R3 /  R1  R2  R4 /  R1  R2 
dV4
V2  V4
R

R
C

 1 2 4
dt
R4 /  R1  R2 
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Three wire segments
R0
R2
R1
C1/2
C1/2
C2/2
R3
C2/2
C3/2
C3/2
Elmore´s delay formula: Each capacitance is multiplied by its upstream resistance!
C2  C3
C3
C1
C1  C2
  R0   R0  R1 
  R0  R1  R2 
  R0  R1  R2  R3 
2
2
2
2
September 2014
Introduction to Integrated Circuit Design
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Three wire segments with branches
Identify main path
September 2014
Introduction to Integrated Circuit Design
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Wire branches
Main path RC model; same as in previous example without branches
R0
R2
R1
C1/2
C1/2
C2/2
R3
C2/2
C3/2
C3/2
Elmore´s delay formula: As before, each capacitance is multiplied by its upstream resistance!
  R0
C  C3
C
C1
C  C2
  R0  R1  1
  R0  R1  R2  2
  R0  R1  R2  R3  3
2
2
2
2
Alternative way of writing the same Elmore wire delay
C
 C1

C

 C2  C3   R2  2  C3   R3 3
2
 2

 2

  R0  C1  C2  C3   R1 
September 2014
Introduction to Integrated Circuit Design
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Wire branches
Add branches to RC model!
R0
Cb1/2
Cb2/2
R1
R2
R3
Cb1/2
Cb2/2
Cb3/2
Cb3/2
Add delay due to branch capacitances
   R0  R1  Cb1   R0  R1  R2  Cb2   R0  R1  R2  R3  Cb3
Total delay is equal to sum of main path delay and branch contributions
September 2014
Introduction to Integrated Circuit Design
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Driving long wires with repeaters
• Since wire delay increases as L2 with wire length, it could be advantageous
to divide long wires into segments driven by repeaters
Repeater data: input and output cap Crep, effective resistance Rrep
Rw/m
Cw/2m
Cw/2m
Rw/m
Cw/2m
Cw/2m
Rw/m
Cw/2m
Cw/2m
• Determine
There
The
number
delay
is a critical
ofthe
of
m number
segments
wire length
ofcan
increase
segments
when
be written
linearly
repeaters
that minimizes
as m,
should
butdelay:
the
be considered
delay of each wire
segment decreases as 1/m2
Rrep Crep C
1 RwCw
Lw 
td
R
C
R
RC

w

m

w
w
L


2
opt
crit 
2R
C


0
td  m
2
R
C

m
R

rep
rep
rep rep

2 CRreprepCrep

mopt22 
rcrep
m
22mm 
m
m



September 2014
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How to size the repeater
Rw/m
rep
rep
Crep
Cw/2m
Crep
Cw/2m
C  R 
C 

td  Rrep  2Crep  w   w  Crep  w 
m m
2m 

Elmore model for segment delay:
RrepCrep is a constant! Two important terms for optimization: Rrep Cw  RwCrep
Minimum when
Rrep Crep
td
 Cw  Rw
0
Rrep
Rrep 2
Rrep Cw  RwCrep
Rrep Cw  Rrep Crep RwCw 
Optimum repeater strength
September 2014
Rrep
Rw

2mopt
Introduction to Integrated Circuit Design
RwCw
2mopt
41
Summing up the segment delays
• For m=mopt, we obtain the following wire delay

C  R 
C 

td  m  Rrep  2Crep  w   w  Crep  w    4 Rrep Crep RwCw
m m
2m  


September 2014
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Conclusion
• Importance of wire delay
• Introduced distributed wire RC p-model
• Discussed relevance of delay equations using a
dominant time constant model
• Using delay model to minimize wire delay
• Elmore delay model – a generalized model
• Mathematics behind Elmore model
• Handling branches
• Repeater insertion
September 2016
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