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ECE 274 - Digital Logic
5.6
Memory Components
Lecture 18
RAM/ROM/EPROM/EEPROM/FLASH
„
Register-transfer level
design instantiates datapath
components to create
datapath, controlled by a
controller
„
„
A few more components are
often used outside the
controller and datapath
MxN memory
„
„
M words
„
Lecture 18 – Memory
„
M words, N bits wide each
N-bits
wide each
Several varieties of
memory, which we now
introduce
M×N memory
1
2
Random Access Memory (RAM)
„
RAM – Readable and writable memory
„
„
32
4
Strange name – Created several decades ago to
contrast with sequentially-accessed storage like
tape drives
„
„
R_data
W_addr
R_addr
4
data
rw
1024x32
RAM
en
d0
R_en
r
d
a
addr(A-1)
e
clk
32
RAM typically larger than roughly 512 or 1024
words
RAM typically stores bits using a bit storage
approach that is more efficient than a flip flop
RAM typically implemented on a chip in a square
rather than rectangular shape – keeps longest
wires (hence delay) short
en
rw
data
10
bit storage
block
(aka “cell”)
word
enable
a0
a1 AxM
d1
decoder
a(A-1)
addr0
addr1
16×32
register file
RAM usually just one port; register file usually
two or more
wdata(N-1) wdata(N-2) wdata0
Let A = log2M
addr
Register file from Chpt. 4
RAM vs. register file
„
10
W_data
W_en
Logically same as register file – Memory with
address inputs, data inputs/outputs, and control
„
„
32
“Random access memory”
„
RAM Internal Structure
32
word
data cell
word word
enable enable
rw data
d(M-1)
to all cells
addr
rw
RAM cell
rdata(N-1) rdata(N-2) rdata0
1024× 32
RAM
en
Similar internal structure as register file
„
„
RAM block symbol
„
„
Decoder enables appropriate word based on address
inputs
rw controls whether cell is written or read
Let’s see what’s inside each RAM cell
3
4
d0
addr
1024x32
RAM
addr
rw
en
addr0
addr1
addr(A-1)
clk
en
rw
„
„
„
d(M-1)
1024x32
RAM
rdata(N-2)
addr(A-1)
en
rw
0
word
enable
rdata0
„
“Static” RAM cell
„
SRAM cell
data
1
„
data’
0
„
a
1
„
0
That loop is where a bit stays stored
data is the bit to be stored in this cell
data’ enters on other side
„
„
Example shows a “1” being written into cell
1
word
enable
„
data
1
word
enable
d
0
data’
cell
d’
0
wdata(N-2) wdata0
bit storage
block ,,
(aka cell )
word
enable
a0
a1 A ⋅ M
d1
decoder
a(A-1)
e
word
data cell
word word
enable enable
rw data
d(M-1)
to all cells
rdata(N-1)
rdata(N-2)
rdata0
SRAM cell
data
1
Reading this cell
d
„
addr0
addr1
clk
to all cells
When 1, the data bit value enters the loop
„
d0
addr
en
a
wdata(N-1)
Let A = log2 M
data
rw
data cell
word enable input comes from decoder
When 0, value d loops around inverters
„
d’
word word
enable enable
rw data
6 transistors (recall inverter is 2 transistors)
Writing this cell
„
10
cell
d
“Static” RAM cell
„
32
data’
word
rdata(N-1)
„
bit storage
block ,,
(aka cell )
word
enable
a0
a1 A ⋅ M
d1
decoder
a(A-1)
e
data
addr
data
Static RAM (SRAM)
SRAM cell
wdata(N-2) wdata0
,,
10
wdata(N-1)
Let A = log2 M
,,
Static RAM (SRAM)
32
Somewhat trickier
When rw set to read, the RAM logic sets
both data and data’ to 1
The stored bit d will pull either the left line
or the right bit down slightly below 1
“Sense amplifiers” detect which side is
slightly pulled down
data’
1
d
1
0
a
word
enable
1
1
<1
To sense amplifiers
The electrical description of SRAM is really
beyond our scope – just general idea here,
mainly to contrast with DRAM...
a
5
6
Dynamic RAM (DRAM)
data
d0
addr
1024x32
RAM
rw
addr
10
en
addr0
addr1
addr(A-1)
„
bit storage
block ,,
(aka cell )
word
enable
rdata(N-1)
rdata(N-2)
„
„
„
Must “refresh” regularly, by reading d and
then writing it right back
„
„
cell
word
enable
„
(a)
data
„
Slowest
„
But very compact
SRAM
DRAM
And refreshing takes time
Size comparison for same
number of bits (not to scale)
Use register file for small items,
SRAM for large items, and DRAM
for huge items
„
enable
discharges
d
Fast
More compact than register file
„
„
register
file
DRAM
d
capacitor
slowly
discharging
MxN Memory
implemented as a:
Fastest
But biggest size
SRAM
„
data
Write: Transistor conducts, data voltage
level gets stored on top plate of capacitor
Read: Just look at value of d
Problem: Capacitor discharges over time
„
„
DRAM cell
rdata0
1 transistor (rather than 6)
Relies on large capacitor to store bit
„
„
data cell
word word
enable enable
rw data
to all cells
“Dynamic” RAM cell
Register file
„
word
d(M-1)
e
en
rw
Comparing Memory Types
wdata(N-2) wdata0
a0
a1 A ⋅ M
d1
decoder
a(A-1)
clk
„
wdata(N-1)
Let A = log2 M
,,
32
(b)
Note: DRAM’s big capacitor
requires a special chip design
process, so DRAM is often a
separate chip
7
8
Reading and Writing a RAM
13
500
999
rw
9
Z
addr
500
data
1 means write
rw
en
„
„
500
microphone
„
ad_buf
12
digital-toanalog
converter
Ra Rrw Ren
processor
wire
da_ld
access
time
„
(b)
Behavior
„
Put address on addr lines, data on data lines, set rw=1, en=1
„
„
„
In short – keep inputs stable before and after a clock edge
speaker
Record: Digitize sound, store as series of 4096 12-bit digital values in
RAM
„
Set addr and en lines, but put nothing (Z) on data lines, set rw=0
Data will appear on data lines
Don’t forget to obey setup and hold times
„
16
analog-todigital
converter
ad_ld
Reading
„
„
wire
Z
RAM[9]
RAM[13]
now equals 500 now equals 999
Writing
„
valid setup
time
valid
hold
time
setup
time
en
9
data
rw
addr
4096⋅ 16
RAM
clk
3
data
2
1
RAM Example: Digital Sound Recorder
addr
clk
We’ll use a 4096x16 RAM (12-bit wide RAM not common)
Play back later
Common behavior in telephone answering machine, toys, voice recorders
To record, processor should read a-to-d, store read values into
successive RAM words
„
To play, processor should read successive RAM words and enable d-to-a
9
10
RAM Example: Digital Sound Recorder
„
RTL design of processor
„
„
„
Create high-level state
machine
Begin with the record
behavior
Keep local register a
„
„
Stores current address,
ranges from 0 to 4095 (thus
need 12 bits)
Create state machine that
counts from 0 to 4095 using
a
„
For each a
„
Read analog-to-digital
conv.
„
„
ad_ld=1, ad_buf=1
RAM Example: Digital Sound Recorder
4096x16
RAM
„
„
16
analog-todigital
converter
ad_buf
ad_ld
12
digital-toanalog
converter
Ra Rw Ren
processor
„
da_ld
For each a
„
„
Record behavior
Local register: a (12 bits)
a<4095
S
a=0
T
ad_ld=1
ad_buf=1
Ra=a
Rrw=1
Ren=1
a
„
U
a=a+1
a=4095
Read RAM
Write to digital-to-analog
conv.
4096x16
RAM
data bus
16
analog-todigital
converter
ad_buf
ad_ld
12
digital-toanalog
converter
Ra Rw Ren
processor
Note: Must write d-to-a one
cycle after reading RAM, when
the read data is available on
the data bus
Play behavior
V
W
The record and play state
machines would be parts of a
larger state machine controlled
by signals that determine
when to record or play
a=0
ad_buf=0
Ra=a
Rrw=0
Ren=1
„
Write to RAM at address a
„
Now create play behavior
Use local register a again,
create state machine that
counts from 0 to 4095 again
da_ld
Local register: a (12 bits)
a<4095
a
X
da_ld=1
a=a+1
a=4095
Ra=a, Rrw=1, Ren=1
11
12
Read-Only Memory – ROM
„
Memory that can only be read from, not
written to
„
„
„
data
data
10
10
addr 1024x32
ROM
en
addr
Data lines are output only
No need for rw input
1024× 32
RAM
rw
en
Let A = log2M
„
„
„
Compact: May be smaller
Nonvolatile: Saves bits even if power
supply is turned off
Speed: May be faster (especially than
DRAM)
Low power: Doesn’t need power supply to
save bits, so can extend battery life
addr0
addr1
RAM block symbol
r
d
a
addr(A-1)
32
data
10
addr
clk
bit storage
block
(aka “cell”)
word
enable
a0
a1 AxM
d1
decoder
a(A-1)
e
word
data
word word
enable enable
data
d(M-1)
en
1024x32
ROM
en
Choose ROM over RAM if stored data won’t
change (or won’t change often)
„
d0
ROM block symbol
Advantages over RAM
„
„
Read-Only Memory – ROM
32
32
ROM cell
rdata(N-1) rdata(N-2) rdata0
ROM block symbol
„
For example, a table of Celsius to
Fahrenheit conversions in a digital
thermometer
Internal logical structure similar to RAM, without the data
input lines
13
14
„
„
Storing bits in a ROM known as
„
Several methods
Let A = log2 M
addr
d0
addr0
addr1
addr(A-1)
e
Bits are hardwired as 0s or 1s
during chip manufacturing
„
„
„
2-bit word on right stores “10”
word enable (from decoder)
simply passes the hardwired value
through transistor
cell
word word
enable enable
data
data(N-1)
1
Fuse-Based Programmable
ROM
data
en
Mask-programmed ROM
„
word
d(M-1)
programming
„
bit storage
block
,,
(a cell )
word
enable
a0
a1 A ⋅ M
d1
decoder
a(A-1)
data(N-2)
data line
„
„
data0
0
data line
cell
„
word
enable
„
„
d0
Each cell has a fuse
A special device, known as a
programmer, blows certain fuses
(using higher-than-normal voltage)
„
cell
Let A = log2 M
addr
If a ROM can only be read,
how are the stored bits stored
in the first place?
,,
„
ROM Types
Those cells will be read as 0s
(involving some special electronics)
Cells with unblown fuses will be read
as 1s
2-bit word on right stores “10”
bit storage
block
,,
(a cell )
word
enable
,,
ROM Types
a0
a1 A ⋅ M
d1
decoder
a(A-1)
addr0
addr1
addr(A-1)
e
word
data
cell
word word
enable enable
data
d(M-1)
en
data(N-1)
1
data(N-2)
data line
data0
1
cell
a
word
enable
fuse
Also known as One-Time
blown fuse
Programmable (OTP) ROM
Notice how compact, and fast,
this memory would be
15
16
ROM Types
ROM Types
Erasable Programmable ROM
(EPROM)
„
„
„
„
Electrons become trapped in the gate
Only done for cells that should store 0
Other cells (without electrons trapped in
gate) will be 1
addr
Uses “floating-gate transistor” in each
cell
Special programmer device uses higherthan-normal voltage to cause electrons
to tunnel into the gate
d0
bit storage
block
,,
(a cell )
word
enable
a0
a1 A ⋅ M
d1
decoder
a(A-1)
e
word
cell
word word
enable enable
data
d(M-1)
data(N-1)
data(N-2)
„
„
data line
data line
cell
cell
1
„
„
0
a
r
„
„
2-bit word on right stores “10”
Details beyond our scope – just general
idea is necessary here
Like EEPROM, but all words (or large blocks of
words) can be erased simultaneously
Become common relatively recently (late 1990s)
r
o
t
n
ti
g
t
eÐeÐ
„
t
„
a
g
trapped electrons
a
r
Both types are in-system programmable
„
„
„
17
t
e
t
data
10
addr
a
g
Can be programmed with new stored bits while in
the system in which the ROM operates
Gives trapped electrons energy to escape
Requires chip package to have window
„
32
n
ti
g
To erase, shine ultraviolet light onto chip
„
Uses floating-gate transistor, electronic programming
to trap electrons in certain cells
But erasing done electronically, not using UV light
Erasing done one word at a time
Flash memory
r
o
word
enable
Similar to EPROM
„
data0
t
e
„
Electronically-Erasable Programmable ROM
(EEPROM)
„
data
en
floating-gate
transistor
„
„
Let A = log2 M
addr0
addr1
addr(A-1)
,,
„
data line
cell
Requires bi-directional data lines, and write control
input
Also need busy output to indicate that erasing is in
progress – erasing takes some time
en
1024x32
EEPROM
write
busy
18
ROM Example: Talking Doll
a
d
“Hello there!”
4096x16 ROM
Local register: a (12 bits)
speaker
4096x16 ROM
v
“Hello there!”
a=0
a<4095
S
T
a
d
16
16
a
digital-toanalog
converter
Ra Ren
processor
ROM Example: Talking Doll
“Hello there!” audio
divided into 4096
samples, stored
in ROM
vibration
Ra Ren
sensor
processor
da_ld
Ra=a
Ren=1
digital-toanalog
converter
a
U
v’
da_ld=1
a=a+1
a=4095
da_ld
v
v
„
Doll plays prerecorded message, trigger by vibration
„
Message must be stored without power supply Æ Use a ROM, not a RAM,
because ROM is nonvolatile
„
„
„
High-level state machine
„
And because message will never change, use a mask-programmed ROM or
OTP ROM
Processor should wait for vibration (v=1), then read words 0 to 4095
from the ROM, writing each to the d-to-a
„
Create state machine that waits for v=1, and then counts from 0
to 4095 using a local register a
For each a, read ROM, write to digital-to-analog converter
19
20
ROM Example: Digital Telephone Answering
ROM Example: Digital Telephone Answering
Machine Using a Flash Memory
„
Want to record the outgoing
announcement
„
„
„
When rec=1, record
digitized sound in locations
0 to 4095
When play=1, play those
stored sounds to digital-toanalog converter
What type of memory?
„
„
„
Machine Using a Flash Memory
„
4096x16 Flash
“We’re not home.”
analog-todigital
converter
ad_buf
„
12
ad_ld
Should store without power
supply – ROM, not RAM
Should be in-system
programmable – EEPROM
or Flash, not EPROM, OTP
ROM, or mask-programmed
ROM
Will always erase entire
memory when
reprogramming – Flash
better than EEPROM
Ra Rrw Ren er
processor
bu
digital-toanalog
converter
da_ld
rec
record play
microphone
speaker
„
RAM is readable and writable
ROM is read-only
a
Also, number of writes may be limited (perhaps a few million times)
Non-volatile RAMs: Can save their data without the power supply
„
„
One type: Built-in battery, may work for up to 10 years
Another type: Includes ROM backup for RAM – controller writes RAM contents
to ROM before turning off
New memory technologies evolving that merge RAM and ROM
benefits
„
e.g., MRAM
Bottom line
„
n
e
analog-todigital
converter
Lot of choices available to designer, must find best fit with design goals
23
16
ad_buf
12
ad_ld
Ra Rrw Ren er
processor
bu
digital-toanalog
converter
da_ld
rec
record
play
microphone
S
a=0
er=1
speaker
Local register: a (13 bits)
bu
a<4096
T bu’ U
er=0
ad_ld=1
ad_buf=1
Ra=a
Rrw=1
Ren=1
a=a+1
a
V
a=4096
22
RAM
NVRAM
And, some RAMs act almost like ROMs
„
„
Flash
EEPROM
Essentially means that writes are slow
„
„
ROM
EEPROM and Flash are in-system programmable
„
„
w
r
rec
But some ROMs act almost like RAMs
„
Execute loop that sets
local register a from 0 to
4095, reading analogto-digital converter and
writing to flash for each
a
We said that
„
Wait for flash to finish
erasing by waiting for
4096x16 Flash
a
d
bu=0
„
Blurring of Distinction Between ROM
and RAM
„
Once rec=1, begin
erasing flash by setting
er=1
16
21
„
High-level state machine
„
sy
u
b