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From Spin Torque Random Access Memory to Spintronic Memristor Xiaobin Wang Seagate Technology Contents Spin Torque Random Access Memory: dynamics characterization, device scale down challenges and opportunities Spin Torque Memristor: concept, device and application examples X. Wang − 2 Spin Torque Random Access Memory (SPRAM) Working Principle Top electrode Magnetic tunneling junction (MTJ) MTJ Reference layer Bottom electrode . Select Transistor (1) Tunneling insulating barrier Free layer Integrate magnetic tunneling junction (MTJ) with CMOS Reading through magneto-resistance principle Writing through spin torque excitation X. Wang − 3 SPRAM Switching Behavior 1 I RH 6 MTJ coupled with CMOS 2 RAP 4 5 RL - 0 3 + V Resistance (Ohm) MTJ static picture Ref: Y. Chen, X. Wang, H. Li, D. Dimitar, H. Liu, International Symposium on Quality Electronic Design, 2008. MTJ switching asymmetry Spin torque switching asymmetry for a field balanced MTJ stack Reference: X. Wang, W. Zhu, D. Dimitrov, Phys. Rev. B, 79, 104408, 2009. X. Wang − 4 Magnetic field (Oe) SPRAM System Dynamical Approach: Quantum-Micromagnetic-SPICE Macroscopic magnetic (size, Ms, etc) Dynamical approach Dynamic Magnetization 25 20 MTJ electronic spin transport (band structure, tunneling) 15 15 10 10 5 CMOS I-V curve, equivalent capacitors,etc 5 Ref: X. Wang, Y. Chen, H. Li, D. Dimitar, H. Liu, IEEE Tran. On Magn., 44(11), 2470, 2008 Dynamic CMOS circuit VDD BL I M + I GD = I DB + I T CGD CDB WL CSB CGS CGB SL dV I GD = C GD ⋅ − dt dV I DB = C DB ⋅ dt I M ⋅ R(t ) = VDD − V (BL → SL )or I M ⋅ R(t ) = −V (SL → BL ) Reference: X. Wang, W. Zhu, D. Dimitrov, Phys. Rev. B, 79, 104408, 2009. Quantum electronic spin transport X. Wang − 5 Challenge for SPRAM to Scale Down 150 CMOS driving current (uA) Field driving: switching field scales up with 1/volume or 1/surface dimension 140 130 120 110 100 22nm x 75nm CMOS 22nm x 45nm MTJ, 13.2F2 90 80 70 1500 Spin torque driving: switching current density scales up with 1/volume or 1/surface dimension 22nm 22 nm x 100nm C x 45 n m MT MOS J, 17 . 2 4F 22nm x 45nm CMOS 22nm x 22nm MTJ, 9F2 2000 2500 3000 MTJ Resistance (Ohm) As magnetic device scales down, with CMOS driving stength decreasing, achieving fast nanosecond time scale magnetization switching and maintaining thermal stability at years time scale become a challenge. X. Wang − 6 Challenge for SPRAM to Scale Down Variation of single device different switching Spin torque MRAM device to device variations reduce sensing and writing margins As device scales down, increased variability is another challenge. X. Wang − 7 Current Reduction Through Magnetization Dynamics critical switching current ∝ M s2Vα η ( Dz − D y )( Dz − Dx ) Dx , D y : demag factors in - plane, Dz : demag factor out - plane Stable energy in equilibrium : M s2V ( D y − Dx ) Dz >> Dx, Dy, different scaling behavior of MTJ writing current magnitude and thermal stability energy Geometric wise: thin film for TMR etc. Magnetization dynamics wise: Symmetric magnetization motion: Dz =Dy Road leads to same scaling of switching current and thermal stability energy X. Wang − 8 Current Reduction Through Magnetization Dynamics RF frequency time varying polarization angle s ion t u ol e dir n tio a z i lar o p nt a t ns on solution ti c e ir d n o ti Co a riz varying pola e m ti l a m ti p O Hard magnetic layer to keep thermal stability Normalized magnetization Mz/Ms on cti Composite material stack Soft magnetic layer to decrease switching field/current magnitude 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 x 10-8 Time (sec) X. Wang − 9 Current Reduction Through Electronic and Spin Transport Across Interface More opaque barrier, less magnetization precessing induced spin pumping, effective damping reduction MTJ with spin moment conservation layer between free layer and top cap layer Increase insulating layer thickness only, RA increases 5 times, critical switching voltage only increases 2.5 times 150 130 1.0 110 90 0.5 Jc(MA/cm^2) MR(%) Ref: X. Wang, W. Zhu, Y. Zheng, Z. Gao, H. Xi, INTERMAG 2009 70 50 30 10 -10 -30 -50 Double AP->P Single0.0 Double P->AP Double -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -0.5 -1.0 0.000001 0.0001 0.01 1 tp(s) J(MA/cm^2) Dual tunneling barrier, critical switching current down to 0.6MA/cm2, quantum confinement effects ? Ref: Y. Zheng, W. Zhu, X. Wang, Z. Gao, D. Wang, D. Dimitrov et. al. submitted to Appli. Phys. Letters X. Wang − 10 Ω) MTJ Resistance (Ω Variation Controlling at Device Level 2800 2600 2400 2200 2000 1800 1600 1400 1200 1000 -1000 40ns pulse DC extrapolation RH destructive RL -500 0 IR Sensing Current (µ µ A) 500 1000 Unique Device characters leads to new sensing scheme Self-reference sensing non-destructive Ref. Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu and T. Zhang, Design, Automation & Test in Europe Conference and Exhibition, 2010. X. Wang − 11 Variation Controlling at System Level Reduce switching current requirement by intentionally move away from worst case scenario design a smaller-than-worst-case transistor sizing approach. For 256Mb SPRAM design at 45nm node, under a normalized write current threshold deviation of 20%, the overall memory die size can be reduced by more than 20% compared with the conventional worst-case transistor sizing design. Ref: W. Xu, Y. Chen, X. Wang, and T. Zhang, 46th Design Automation Conference, 2009. X. Wang − 12 Heat Asssited Solutions Surface anti-ferromagnetic coupled (AFC) magnetic layer with relatively low Curier temperature: At room temperature, the AFC coupling provides surface anisotropy to maintain thermal stability of the square magnetic element. During the writing process, the joule heating of spin torque current raises temperature of AFC surface magnetic layer above Curier temperature and the AFC induced surface anisotropy disappears. The element can be switched at low threshold current. 500 1.00 6 nsec 10 nsec 300 Cell size (um2) I (µA) 400 64Mb Required heating current 200 256Mb 0.10 65nm, 6nsec 65nm, 10nsec 1Gb 100 0.01 0 0 20 40 60 80 D (nm) 100 120 140 40nm, 6nsec 40nm, 10nsec RA = 12.5 Ωµm2 0 20 40 60 80 100 120 140 D (nm) Write current decreases with decreasing memory element dimension D. Meanwhile, the MTJ resistance increases with decreasing memory element dimension. For a given technology node, an optimal memory cell size can be found due to the tradeoff between critical switching current and MTJ resistance Ref: H. Xi, J. Sreicklin, H. Li, Y. Chen, X. Wang, and Y. Zheng, Z. Gao, M. Tang, IEEE Trans. Magn, 46,no. 3, 860, 2010 X. Wang − 13 MTJ Memristor and Mutibit Data Storage and Logic 00 demonstrated multi-bit MTJ devices 01 10 Ref: X. Lou, Z. Gao, D. Dimitrov, and M. Tang, Appli. Phys. Letters, 93, 242502, 2008 11 From nonlinear resistor point of view: reversible branch: 11 to 10, 00 to 01 Irreversible branch: 00 to 10 MTJ Memristor and Mutibit Data Storage and Logic Switching current (uA) 1400 1200 From memristor point of view: 1000 800 600 400 e re o m 200 0 0 0.5 te a g lo n 1 nd a pe a h ds fac r u ss s e l switch 00->01 1.5 2 Switching from 00 to 10 and from 00 to 01 are all possible by adjusting pulse width rea a e Different slope, switching depends upon integration of current, not current magnitude ! switch 00->10 2.5 3 x 10 8 Inverse of pulse width (sec-1) Ref. X. Wang, Y. Chen, Design, Automation & Test in Europe Conference and Exhibition, 2010. X. Wang − 15 Memristor as Fourth Circuit Element Resistor Memristor What makes memristor different from an ordinary constant resistor or even a current or voltage dependent nonlinear resistor: memristance is a function of charge, which depends upon the hysteretic behavior of the current (or voltage) profile. V ϕ = ∫ Vdt capacitor Leon O. Chua, Memristor-the missing circuit element, IEEE Trans. Circuit Theory, vol. 18, no. 5, 1971 Chua (1971) proposed memristor for logic completeness of circuit element q q = ∫ Idt What makes memristor different from a capacitor or inductor is the ability to accumulate current or voltage information at X. Wang − 16 constant voltage or current. Memristance in Resistive Memory Stack low resistance state high resistance state measured simulated 1) Nano-scale two terminal device as two connecting resistors (doped region and undoped region) 2) Bias electric current drives the front of the doped region 1) J. M. Tour and T. He, Nature 453, 42, (2008). 2) D. B. Strukov; G. S. Snider; D. R. Stewart and R. S. Williams, Nature, 453, 80, (2008) X. Wang − 17 Spintronic Memristor Through Spin Torque Induced Magnetization Motion GMR/TMR device: resistance depends upon magnetization state Spintronic memristor: resistance depends upon the integral effects of its current profile. Spin Torque device: current electronic spin changes the magnetization state of the device. The magnetization state of the device depends upon the cumulative effects of electron spin excitations. X. Wang, Y. Chen. H. Xi, H. Li, D. Dimitrov: IEEE electronic device letters vol. 30, no. 3, pp.294, 2009. X. Wang − 18 Domain Wall Memristor and Temperature Sensor interactions between macroscopic coherent magnetic structures and random fluctuations Nano-scale feature size, low cost, and mature integration technology with the CMOS process. Targeting the highly integrated on-chip thermal detection applications X. Wang, Y. Chen, Y. Gu, H. Li: IEEE electronic device letters vol. 31, no. 1, pp.20, 2010. X. Wang − 19 Memristor for Power Management The ability to accumulate current/voltage through constant current and/or voltage driving strength: power monitor device ∫ ∫ E = VIdt = V Idt Negative feedback: power control device Ref. X. Wang, Y. Chen, Design, Automation & Test in Europe Conference and Exhibition, 2010. X. Wang − 20 Memristor for Data Security Question: Administrator and user. Design a scheme to fight against following action: after reading the stored data information, the user tries to restore the device state to the same state as before reading, so that administrator could not find whether the data has been accessed. Solution depends upon whether the user is given the limited or the same authority on device writing and reading compared to that of the administrator. For the case of user with limited reading and/or writing authority, data information security task can be achieved more easily. For limited writing authority case, user may not be able to restore the device to the state set by the administrator before. For reading limited case, the user may not know the state of the device set by the administrator. A solution giving user and administrator the same authority on reading and writing: 1) Writing process: administrator sets high resistance state (0) fully saturated and low resistance state (1) partially saturated. 2) Reading process: two constant voltage pulses excite device a few times (order of 10). One pulse pushes domain wall toward high resistance end and the other pulse tries to push domain wall toward low resistance end. Final domain wall settled position 0.8 0.7 0.6 0.5 0.4 0.3 0.2 Administrator reads the data using pulses with a particular second pulse driving strength. 0.1 3) The device reports two values for reading: 1) final state of 00.8 1 1.2 1.4 1.6 1.8 2 2.2 the device close to high or low resistance state (High or Low) and 2) whether the device resistance has been significantly Second pulse magnitude changed during reading (Yes or No). Ref. X. Wang, Y. Chen, X. Wang − 21 Design, Automation & Test in Europe Conference and Exhibition, 2010. Path to Future: Potentials GMR with spin valve structure Physics process is clear and scaling behavior is well understood: controllable and tunable device TMR with tunneling structure Easily integration on top of CMOS New geometry structures New material Y. V. Pershin and M. Di Ventra, Phys. Rev. B, 78, 113309, 2008 Spin blockade, half-metallic material X. Wang − 22 Path to Future……. nano-scale, ultra-fast……. variability, memory effects……. analogue/digit mixture fuzzy, neural system …… deterministic, precise digital control X. Wang − 23 ……..