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Design of Low Phase Noise LC VCO for UHF RFID Reader
Proceedings of the 15th Asia-Pacific Conference on Communications (APCC 2009)-098
RFID Reader Design of Low Phase Noise LC VCO for UHF
Yunfang Zhou? Zhiqun Cheng *, Kaihong Fu, Jin Li, Xiaopeng Zhou
Key Lab of the RF Circuit and System, Ministry of Education, Hangzhou Dianzi
University, Hangzhou 310018 China
Abstract—A low phase noise CMOS LC VCO (Voltage controlled oscillator) for UHF RFID
(Radio Frequency Identification) reader is designed. The quadrature output
differential
signal
is
achieved
through
Source-Coupled-Logic
frequency
divider-by-two circuit. The circuit is implemented with the SMIC 0.18um MOS
technology and the simulator of Cadence SpectreRF. The simulation results show that
the frequency range of VCO is from 1620MHz to 2020MHz before frequency divider and
phase noise of -127.5dBc/Hz at 1MHz offset at oscillation frequency of 1.8GHz. The
frequency
rang
of
VCO
is
from
810MHz
to
1010MHz
after
frequency
dhttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bivider by two and the
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phase noise of -133.5dBc/Hz @1MHz offset at the frequency of 900MHzˊ
Index Terms—RFID reader?LC VCO?Low phase noise?Quadrature output
I. INTRODUCTION
adio frequency identification application is growing fast in many areas, such as
antifraud systems, supply chain
managements, and object tracking systems.
Ultra-high frequency RF ID systems operate in the Industrial Scientific Medical (ISM)
bands between 860 and 960 MHz. They have much longer read range of 3m to 10m for a
passive tag. Due to the stringent spectrum mask requirement for the transmitter and
good
sensitivity for the receiver, the design of
frequency synthesizer for lower
phase noise and low spur levels becomes more critical for RFID reader [1]-[3]. Voltage
controlled oscillator (VCO) is the essential building block of frequency synthesizers.
The
VCO
performance
in
terms
of
phase
noise
http://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7brang
and
tuning
determine
basic
performance characteristic of a frequency synthesizer. In this paper, a 1.8 GHz LO
signal is generated by an integrated LC VCO in the frequency synthesizer and then
the 900 MHz differential I/Q LO signals are obtained by using a divide-by-two circuit.
The wide tuning rang and low phase noise performance of VCO with switched capacitor
array and noise filtering technique is simultaneously achieved.
R
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Fig. 1. System structure of frequency synthesizer
of the frequency synthesizer. A 1.8 GHz LO signal is generated by an integrated VCO
in the PLL and then the 900 MHz differential output is filtered by loop filter and
applied to the VCO. An 8/9 dual modulus prescaler, PS counters, and the third-order
sigma-delta modulator are used in the feedback path of the frequency synthesizer.
A 1.8 GHz LO signal is generated by an integrated VCO in the PLL and then the 900
MHz dhttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bifferential output
is filtered by loop filter and applied to II. CIRCUIT DESIGN
the VCO. An 8/9 dual modulus prescaler, PS counters, and the
A. Structure of frequency synthesizer third-order sigma-delta modulator are used in
the feedback A frequency synthesizer based on a fractional-N PLL is path of the
frequency synthesizer. A 1.8 GHz LO signal is designed as depicted in Fig.1. The
synthesizer uses off-chip generated by an integrated VCO in the PLL and then the 900
crystal and has the 500 kHz channel spacing. The crystal is MHz differential output
is filtered by loop filter and applied to divided by three with a reference divider
to create the the VCO. An 8/9 dual modulus prescaler, PS counters, and the reference
for the phase frequency detector (PFD). The output third-order sigma-delta modulator
are used in the feedback signal of the PFD drives a charge pump. The charge pump path
of
the
frequency
synthesizer.http://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7b A 1.8 GHz
LO signal is output is filtered by loop filter and applied to the VCO. An 8/9 generated
by an integrated VCO in the PLL and then the 900 dual modulus prescaler, PS
programmable counters, and the
MHz differential I/Q LO signals are obtained by a divide-by-third-order sigma-delta
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modulator is used in the feedback path two circuit.
Manuscript received May 9, 2009. Corresponding author: Zhiqun Cheng (e-mail:
[email protected]).
This work was supported by National Natural Science Foundation of China (Grant NO
60776052)
Digital Object Identifier inserted by IEEE
B. Low Phase Noise VCO Design
The semi-empirical model proposed in [4], known also as the Leeson’s phase noise
model, is based on a linear time invariant system assumption for tuned tank
oscillators:
Design of Low Phase Noise LC VCO for UHF RFID Reader
Fig. 3. Tuning curve http://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bof
the VCO
Fig. 2. Schematics of the VCO
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?°2FKT?§ωVCO·??Δωf3??°
$Δω=10?lg? 1??
(1) ? ¨???1
Δ???°°?Psignal??2QΔ????
where ωVCO is the VCO center frequency, Δω is the offset frequency, Q is the overall
LC tank quality factor, Psignal is the power of oscillation signal, F is empirical
parameter (often called the “device excess noise factor”). Because the F is an
unspecified noise factor, the equation (1) is not flexible. J.Rael proposes a
normalized noise factor F based on the physical mechanisms of phase noise in the
differential LC oscillator [5].
F
Fig. 4. Phase noise filtering result
The VCO topology, as shown in Fig. 2, uses the complementary cross-coupled transistor.
Using long channel NMOS tail current source, good common mode matching between the
VCO
and
divide-by-two
circuit
is
eashttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bily got without an
additional dc level shifted circuit. Cross coupled transistor Mn1 and Mn2, Mp1 and
Mp2 offer a small signal negative differential conductance that compensate the loss
of the resonance tank. A big capacitor C3 is paralleled with the tail current source
transistor Mt2 to short noise frequencies around 2?0 to ground. To raise the impedance,
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an inductor L1 is inserted between the current source and the tail. The inductance
is chosen to resonate at 2?0 in parallel with C1 at the common sources of the
differential pair. L2 and C2 also resonate at 2?0 to prevent Mp1 and Mp2 in triode
form adding loss to the resonator tank [6].
In order to achieve a large frequency range while keeping a relatively low tuning
sensitivity, the LC tank combines a switched capacitor array with a small varactor
[7]. The targeted frequency range is split into 16 sub-bands by means of a 4-bit
binary-weighted
array
of
switched
MIM
cahttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bpacitors. One of the
coarse tuning cells is depicted in Fig2. Two inverts and resistors are added to provide
a high DC voltage to the drain and source of Ms1 when the B0 is low. Providing a DC
bias to the drain and source of Ms1 not only ensures the quality factor of the
coarse-tuning cell, but also it helps lower junction capacitance Cgs and Cgd to
improve the tuning ratio.
=1
4γRI8
γgmbias
(2)
9V0
is the bias current, γ is the channel noise Where I
coefficient of the FET (equal to 2/3 for long channel FET, and larger than that for
shorter channels), gmbiasis the transconductance of the current-source FET. The
expression in (2) describes three noise contributions, respectively, from the tank
resistance, the differential-pair FETs, and from the tail current source. In most
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oscillators the third term in equation (2) accounts for about 75% to the
thttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7botal noise factor F.
This is because the high frequency tail current noise at twice the oscillation
frequency is down-converted into phase noise by the hard switching the tail current
source transistor. Although clearly improvement of phase noise performance by
removing the tail current source, the VCO becomes more sensitive to the
power supply noise, temperature and technology.
Proceedings of the 15th Asia-Pacific Conference on Communications (APCC 2009)-098
Fig.6 Representation of source-coupled latch as a fully differential amplifier and
the 2:1 divider as an oscillator
Fig. 5. Frequency divider by two (a) structure (b) schematics
factor of the coarse-tuning cell, but also it helps lower the junction capacitance
Cgs and Cgd to improve the tuning ratio. In summary, three important parameters govern
the
design
of
this
coarse-tuning
cell:
quhttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bality factor, tuning
range, and sensitivity. To increase the quality factor, a large transistor Ms1 is
used. However, it reduces the tuning ratio and makes the coarse tuning cell more
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sensitive. Therefore, some optimization is done through simulation [8].
The VCO tuning range is illustrated in Fig.3, showing all 16 overlapping frequency
sub bands. The measured frequency range is 1.62–2.02 GHz with an average tuning
sensitivity (Kvco) of 45 MHz/V.
The simulation results of phase noise are shown in Fig.4. The solid line represents
the phase noise of VCO with the noise filtering technique and the dashed one represents
the phase noise of VCO without the noise filtering technique. The VCO with the noise
filtering technique (solid line) shows a measured phase noise of–127.5dBc/Hz at 1MHz
offset while without one (dashed one) shows a measured phase noise of –121.6dBc/Hz
at
1MHz
offset
at
carrier
frequency
of
1.8GHz.
Ihttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bt is clear that the
phase noise performance of the VCO is clearly improved with the help of filtering
technique.
Fig. 7. Quadrature output of divider-by two
The differential nature reduces the switching noise and provides a sufficient noise
margin. The topology of the divide-by-two circuit is illustrated in Fig.5 (b). The
2:1 divider implemented with SCL can operate in one of two modes. The first mode is
the standard digital operation of latching, while the second is an injection-locked
mode [9-10].
The latching mode of operation occurs when the input clock signals have a large voltage
swing. Here, M1 M2 and M5 M6 act as an evaluation stage when the latch is transparent,
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and regenerative pair M3 M4 and M7 M8 act as a hold stage when the latch is opaque.
For CLK is high, the master is transparent and the slave is opaque, with I
taking
the
value
of
D
and
Db.
For
CLK
is
and Ilow,
http://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bthe master is opaque and
the slave is transparent, and nodes I
and I- are passed to the output Q
and Q-.
Thus, for every clock pulse, the output is toggled, resulting in a divide-by-two
operation.
To understand the second mode of injection locking, the oscillation of the 2:1 divider
with no input present must first be understood. When the CLK and
are equal at their
common mode value, both the master and slave latches are
C. Divide-by-Two Circuit semi-transparent, allowing signals to propagate through
both
latches. As shown in Fig.6, the source-coupled latch can be
Fig.5 (a) shows the block diagram of 2:1 Source Coupled represented as a fully
differential amplifier. So the master-Logic (SCL) static frequency divider. The
divider-by-two
slave D-type flip-flop circuit can be represented as a two stage circuit is based
on
the
classical
master-slave
D-type
flip-flop.
oscillator.://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7br
Design of Low Phase Noise LC VCO for UHF RFID Reader
ring
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Fig. 8. Phase noise simulation of the VCO associate with divider-by two
For this case, M9 and M10 become current sources. Cross-coupled transistor M3 and
M4 can be represented as negative resistance with the value of 1/g34, where 1/g34
is the transconductance of M3. The PMOS load can be modeled as a conductance gp and
the CL represents the total capacitance at the output nodes. The small signal loop
gain (H) of the 2:1 divider can be shown to be as follows:
H
Just like a two stage ring oscillator, the phase shift through each differential
amplifier should be 900. So as depicted in Fig.7, the frequency divider with a VCO
can generates two quadrature signals.
The phase noise simulation of the combination VCO and Divider-by-two circuit is
depicted
in
Fig.8.
The
combination
(solid
line)
gives
a
shttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bimulated phase noise
of–133.5dBc/Hz at 1MHz offset with a 6dB improvement.
The VCO layout, as depicted in Fig.9, is drawn with center-symmetry. The metal line
between key signals should as short as possible to reduce the parasitical capacitance.
The total chip area including pad is 0.9*0.8mm2.
III. CONCLUSION
The LC VCO with carrier frequency of 1.8GHz is successfully designed in this paper.
The low phase noise and tuning range from 1620 to 2020 MHz are simultaneously achieved.
The phase noise performance of the VCO is clearly improved with the help of filtering
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technique and digital controlled switched capacitor array. The quadrature output
signals of the divider-by-two circuit, which can cover the frequency range of UHF
RFID, are achieved and inherit the good phase noise performance of VCO.
Fig. 9. Layout of the VCO
REFERENCES
[1]
S.
Chiu,
I.
Kipnis,
Mhttp://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7b. Loyer, et al. “A 900
MHz UHF RFID Reader
Transceiver IC,” IEEE J. Solid-State Circuits, vol. 42, pp. 2822-2833, DEC 2007.
[2] P.B Khannur, X.S Chen, D.L Yan, et al. “A Universal UHF RFID
Reader IC in 0.18-um CMOS Technology,” IEEE J.Solid-State Circuits, vol. 43, pp.
1146-1155, May 2008.
[3] W. Wang, S. Lou and K. Chui,et al, “A Single-Chip UHF RFID Reader
in 0.18um CMOS,” IEEE 2007 Custom Integrated Circuits Conference, pp.111-114, 2007
[4] D.B Leeson, “A simple model of feedback oscillator noise spectrum”,
Proc IEEE, Vol 54, pp.329-330, Feb. 1966.
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[5] J.J Rael. and A.A Abidi, “Physical processes of phase noise in
differential LC oscillators”, Proceeding of Custom Integrated Circuits Conference,
Oralndo, FL, pp. 569-572, 2000.
[6] E Hegazi and A.A Abidi, “A filtering technique to lower LC oscillator
phase
noise”,
IEEE
Solid-http://www.mianfeiwendang.com/doc/e90271ff84277d7884744b7bState
J.
Circuits,
vol.36, pp.1921-1930, Dec.2001.
[7] E Hegazi, and A.A. Abidi, “Varactor Characteristics, Oscillator Tuning
Curves, and AM–FM Conversion”, IEEE J. Solid-State Circuits, vol.38, pp.1033-1039,
JUNE 2003
[8] Henrik Sjoland, “Improved Switched Tuning of Differential CMOS
VCOs”,IEEE Trans on Circuits and Systems—II: Analog And Digital Signal Processing,
Vol.49, pp.352-355 , MAY. 2002
[9] Cao Changhua and K.O Kenneth, “A Power Efficient 26-GHz 32:1
Static Frequency Divider in 130-nm Bulk CMOS”, IEEE Microwave and Wireless
components Letters, Vol.36, pp.721-723, Nov. 2005.
[10] H.M Wang, “A 1.8V 3mW 16.8GHz frequency divider in 0.25um
CMOS”, IEEE International Solid-State Circuit Conference, pp.196-197, Feb. 2000.
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=?(
gm1
2
(3)
gp?g34 jωCL
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