Download Title (Example: design and simulation of a full adder)

Title (Example: design and simulation of a full adder)
(a design report for ECEN4375/5375)
by
NAME
DATE
Checklist (do not include in your report)
Spell check – add often used technical terms to your dictionary
Center figures, scale as needed, rotate as last resort
Include captions below the figures
Figure quality: Make sure the text on the figures is legible, avoid the dark
backgrounds generated by PSPICE, the gray default background generated
by EXCEL.
Transfer the data to a spreadsheet and overlay curves rather than having a
lot of figures with a single curve.
Remove EXCEL defaults such as border, title and background on graphs
Set up your own default EXCEL graph template with desired font and
appearance for a uniform look of all figures
Turn off the fill feature in CLEWIN and use crosshatching on your layout
for optimal “readability”
Rename/add headings in this document as needed
Discuss items that lead up to your conclusion throughout the report
Discuss your test strategy, # probes needed, parallel vs. serial testing
Compare DC simulation with DC test. Overlay on one graph
Discuss design trade-offs
If your report is longer than 25 pages, reduce the size if possible by
eliminating redundancy, combine multiple curves on one graph, scale the
figure size without sacrificing content.
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Outline
Title (Example: design and simulation of a full adder) ...................................................... 1
Outline............................................................................................................................. 3
1. Introduction ............................................................................................................. 4
2. Circuit description ................................................................................................... 4
3. Circuit simulation.................................................................................................... 4
4. Worst case analysis ................................................................................................. 6
5. Circuit Layout ......................................................................................................... 6
6. Circuit Fabrication .................................................................................................. 7
7. Device Testing ........................................................................................................ 8
8. Circuit Testing ........................................................................................................ 9
9. Possible improvements ........................................................................................... 9
10.
Conclusion ........................................................................................................ 10
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1. Introduction
Summarize briefly the purpose you had in mind, the function of your circuit as related to
this purpose, the approach you chose to design the circuit, the verification of your initial
circuit design using a PSPICE simulation and the layout of the circuit. For instance:
The purpose of my project is to design a reasonable operational amplifier using a pMOS
device technology. The design consists of two differential stages, a source follower and a
push-pull output buffer. A DC and AC simulation of the amplifier was performed using
PSPICE. Since the amplifier contains a total of 18 transistors, the circuit was split into the
first two differential amplifiers stages and the source follower and output buffer. Each of
those was simulated separately. He circuit was then laid out within the area provided by
first drawing a stick diagram and the creating the final layout using MAGIC.
2. Circuit description
In this section, further describe the desired functionality of your circuit, the details of the
circuit design, the conversion to a pMOS circuit (if applicable), the choice of W/L ratios
for the individual transistors, the choice of using resistors instead of enhancement loads
(if applicable). Also describe any alternate circuits you might have considered, any
problems you faced and how you solved them.
Provide a circuit diagram as a figure in the text (not attached at the end) and provide a
figure caption.
VDD
1:1
1:2
1:2
1:2
1:2
1:1
16:1
1:2
Vin1 Vin2
4:1
16:1
4:1
4:1
Vout
4:1
8:1
4:1
8:1
8:1
16:1
16:1
Ground
Figure 1. Circuit diagram of an operational amplifier with inputs Vin1 and Vin2 and
output Vout. W/L ratios are provided next to each transistor
3. Circuit simulation
Provide a description of the circuit you simulated. Provide either the node list and model
description of the PSPICE input file.
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opamp circuit
Ri1 1 2 1k
Ri2 3 4 1k
Q1 7 2 5 NPN
Q2 8 4 5 NPN
Vin1 1 0 0V
Vin2 3 0 0V
Rc1 12 7 4k
Rc2 12 8 4k
Q3 5 6 14 NPN
Ra 12 6 100k
Rb 6 13 10k
Re3 14 13 1k
Vcc 12 0 15V
Vee 0 13 15V
Q4 10 8 9 PNP
Re4 12 9 1k
Rc4 10 13 5k
Q5 12 10 11 NPN
Q6 13 10 11 PNP
RL 11 0 1k
.MODEL NPN NPN(BF=200)
.MODEL PNP PNP(BF=200)
.DC Vin1 -0.1 0.1 .005
*.TRAN 5N 300N
.PROBE
.END
Table 1.
PSPICE input as used for the simulation of the operational amplifier.
or an equivalent schematic description including the model description. Note that the
example above does not correspond to the circuit of figure 1, while yours should.
Provide a limited but sufficient set of graphs to prove that your circuit operates properly.
Use the same simulations as you handed in as part of the simulation report (unless they
have been corrected/improved since).
Provide a caption for each figure and refer to each figure within the text.
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Output voltage (V)
15.00
10.00
5.00
0.00
-5.00
-10.00
-15.00
-150.0
-100.0
-50.0
0.0
50.0
100.0
150.0
Input voltage (mV)
Figure 2. Transfer characteristic of the operational amplifier showing cross-over
distortion and saturation.
Hint: you can get the numeric data from PSPICE by using the .PRINT command and
import them into your favorite spreadsheet or plotting program.
Select only relevant simulation results and combine multiple traces into a single graph.
This reduces the number of graphs and makes the report more readable.
4. Worst case analysis
Provide and discuss the simulation using a threshold voltage of –5V. Mention how the
change in threshold affected the circuit operation. Also describe what you did to make the
circuit operation with this modified threshold. Provide a selected number of graphs as
evidence.
5. Circuit Layout
Briefly describe the layout process. Focus on how you converted your circuit diagram
into a stick diagram and provide the final stick diagram.
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VDD
VDD
Vin1
Vout
Vin1V
Vout
in2
Ground
Ground
Vin2
Figure 3. Stick diagram of the operational amplifier with contact pad configuration.
Briefly describe the layout and provide a picture of the layout.
6. Circuit Fabrication
Briefly describe the circuit fabrication process. Focus on issues, which affect or could
affect your circuit. How good was the yield of every fabrication step?
Provide a picture of your finished circuit.
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Figure 4. Micrograph of the completed operational amplifier.
7. Device Testing
First answer the Lab #7 questions below and provide the measured data. If you switched
to some other wafer after the first week, explain why and what wafer you used for each
measurement. If you did not do a certain measurement explain the circumstances.
7.a
Provide the data measured on the transmission line structure by plotting the
measured resistance multiplied with the width (20 micron) as a function of the
contact spacing (10, 20, 40 and 80) micron. Extract the sheet resistance, Rs, (= the
slope) and the contact resistance, Rc, (half the Y-axis intercept, in units of Ohmcm). Calculate the contact resistivity, c, from Rc  Rs  c
7.b What is the thickness of the gate, "diffusion" and field oxide as measured with the
ellipsometer? What are the thicknesses of the gate oxide and "diffusion" oxide as
obtained from the C-V measurements? What values are the most accurate and why?
7.c
What is the doping concentration, the threshold voltage and the flatband voltage as
obtained from the C-V measurement? Carefully scrutinize the minimum capacitance
the C-V system used to calculate the doping concentration and adjust the value if
necessary. As additional information, keep in mind that the sheet resistance (as
measured with the M-gage) of the starting wafers was 100 - 200 Ohm per square.
The wafers are 14 mils thick. What doping concentration would you expect from
this M-gage measurement?
7.d List the measured values of the output conductance, the threshold voltage and the
slope on the |ID| versus VG curve of the larger driver transistor. Calculate the
surface mobility based on your measurements. What value did you use for the W/L
ratio of the transistor? How does your calculated value compare to the bulk mobility
expected from the substrate doping concentration? Calculate the transconductance
for the gate and drain voltage at which the output conductance was measured (take
the drain voltage to be halfway between the two values used to draw the straight
line). Calculate the ratio between the transconductance and output conductance at
that bias point.
Plot the slope as a function of the gatelength for the 10, 15, and 20 m gatelength
devices. Do the data point follow the expected trend? Plot the threshold voltage
versus gate length. Explain the observed behavior.
7.e
Attach the transfer characteristics of the inverter you measured. Compare the
measured and calculated values of the maximum output voltage and the linear slope
of the curve. Use the measured threshold voltage of the transistors when calculating
the maximum output voltage.
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Provide the eye diagrams and identify the logic "0" and logic "1" voltages at -10, 15 and -20V power supply voltage. Determine the noise margins at each power
supply voltage.
7.f
Describe the measured p-n diode characteristics. Provide the extracted parameters.
How do these compare to the expected values?
In addition, list the measured device parameters and compare them with the nominal
values. Describe how the information was obtained and provide the experimental data
when possible. Extract the SPICE parameters from your measurement data.
Summarize the data in a table, following the example below:
Parameter
expected
actual
Threshold voltage
Hole mobility
-1.9 V
100 cm2/V-s
-3.5 V
105 cm2/V-s
Gate capacitance
80 nm
89 nm
Gate capacitance
Doping density
80 nm
2 x 1015 cm-3
93 nm
4.2 x 1015 cm-3
Table 1.
Value obtained
from
Transfer curve
Calculated from K
and Cox
Ellipsometer
measurement
C-V measurement
C-V measurement
Nominal and measured parameters used in SPICE simulations.
8. Circuit Testing
Describe the testing of your circuit. Provide your testing strategy and how you intended
to reconcile the test results with your simulations. What would be a successful test of
your circuit? Make sure you treat your circuit as an analog circuit even if it is a digital
circuit. Identify logic high and low levels and discuss whether your circuit can readily be
combined with other circuits on the same wafer.
Provide measured data with figure captions. Explain the individual measurements and
what you conclude from them.
How did your circuit perform compared to your simulations? If the difference is large,
redo your simulation using the measured values for the threshold voltage, oxide thickness
and doping densities. Do only those simulations, which you can directly compare to
measured data. Comment on the remaining differences, the degree of agreement and the
possible refinements, which would lead to even better agreement.
9. Possible improvements
Describe how you could further improve your circuit design. Possible improvements
include circuit modifications, layout modifications resulting in a smaller circuit. Provide
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specific improvements (for instance: by changing the W/L ratio of transistor #7 to 64:8 I
increased the output voltage swing to 16 V as illustrated with the following simulation)
rather than generalities.
10.
Conclusion
A conclusion describes the end result, namely your finished product. This differs from a
summary, which primarily lists the activities leading to the final result. For instance:
A pMOS operational amplifier was successfully designed, simulated and laid out using 8
m minimum feature size and 4 m minimum overlap. The amplifier has an open loop
voltage gain of 300, a common mode rejection of 10 and an open loop bandwidth of 15
MHz. The maximum output voltage swing is 15 V peak-to-peak for a power supply
voltage of –25 V. The circuit was designed for a power supply voltage of –15 Volt,
assuming a threshold voltage of –1.9 V. The circuit was also simulated with a threshold
voltage of –5 V. A power supply voltage of –25 V was needed to obtain a functional
circuit with this threshold voltage.
Fabrication yielded a total number of 30 circuits without visual defects. 23 circuits were
lost due to scratches and over etching of the metal. The wafer changed color after the
deglaze and drive-in due to the removal of the glaze and subsequent dry oxidation. Some
resist was left on the wafer prior to the metal anneal resulting in a yellow color on part of
the wafer.
Testing of individual transistors revealed a threshold of –6 V. While this threshold
voltage was higher than expected, the threshold voltage was reasonably uniform for all
transistors measured (a total of 9 were measured). Therefore the decision was made to
test the circuit on my wafer. This decision turned out to be a big mistake. Not only was
the threshold high, the leakage current of the diodes was particularly poor (>300 nA) so
that my circuits showed erratic behavior: floating nodes would have arbitrary voltages
while light would cause irreproducible results.
After switching to Justin’s wafer, I managed to operate my circuit successfully. The
output voltages were lower than expected, but I obtained an open loop voltage gain of
210 and a 13 V output voltage swing when operating at a power supply voltage of –25V.
Make sure you include specific information in your conclusion. Also any conclusion
must be back up by further data somewhere in the report.
11.
Final Conclusion
FINAL conclusion: In your opinion and considering your experience in the lab, what
would be the largest circuit, which could be successfully fabricated during the course of
this lab? Suppose all students would work together on a single larger design, how
complex could it be (number of transistors and/or logic gates) and still have a chance to
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work? What would be the limiting factor: fabrication yield, design time, fabrication time,
testing time, etc… and why?
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