Download Leakage Biased PMOS Sleep Switch Dynamic Circuits

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006
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Leakage Biased pMOS Sleep Switch
Dynamic Circuits
Zhiyu Liu, Member, IEEE, and Volkan Kursun, Member, IEEE
Abstract—In this brief, a low-overhead circuit technique is
proposed to simultaneously reduce subthreshold and gate-oxide
leakage currents in domino logic circuits. pMOS sleep transistors
and a dual threshold voltage CMOS technology are utilized to
place an idle domino logic circuit into a low leakage state. A sleep
transistor added to the dynamic node strongly turns off all of the
high threshold voltage transistors. Similarly, a sleep switch added
to the output inverter exploits the initially high subthreshold and
gate-oxide leakage currents for placing a circuit into an ultimately
low leakage state. The proposed circuit technique lowers the
total leakage power by 56.1% to 97.6% as compared to standard
dual threshold voltage domino logic circuits. Similarly, a 4.6% to
50.6% reduction in total leakage power is observed as compared
to a previously published sleep switch scheme in a 45-nm CMOS
technology.
Index Terms—Domino logic, dual threshold voltage, gate-oxide
tunneling, sleep mode, subthreshold leakage current.
I. INTRODUCTION
EATURE size scaling in MOSFETs requires reducing the
supply and threshold voltages. Lowering of threshold voltages leads to an exponential increase in subthreshold leakage
current. Several circuit techniques based on multiple threshold
voltage (multiple- ) CMOS technologies are described in the
literature for reducing the subthreshold leakage current [1]–[6],
[9]. However, the effect of these multiple- CMOS circuit techniques on the gate-oxide leakage current characteristics has not
been explored until recently.
is caused by the direct
The gate-oxide leakage current
tunneling of electrons and holes through the gate insulator. The
tunneling probability of carriers increases dramatically with the
in each new technology
scaling of gate-oxide thickness
generation [11]. Gate dielectric tunneling has become a primary
leakage mechanism. Particularly, at low die temperatures during
long idle periods, most of the power consumption could occur
due to gate-oxide leakage. New circuit techniques aimed at reducing the subthreshold and gate-oxide leakage currents are,
therefore, highly desirable.
In this brief, a new circuit technique is proposed to reduce the
subthreshold and gate-oxide leakage currents in domino logic
circuits. pMOS sleep transistors are utilized along with a dual
threshold voltage (dual- ) CMOS technology to place the dynamic and output nodes of an idle domino logic circuit into a low
F
Manuscript received December 26, 2005. This work was supported in part by
a grant from the Wisconsin Alumni Research Foundation (WARF). This paper
was recommended by Associate Editor L. Lavagno.
The authors are with the Department of Electrical and Computer Engineering,
University of Wisconsin—Madison, Madison, WI 53706-1691 USA.
Digital Object Identifier 10.1109/TCSII.2006.882206
TABLE I
NORMALIZED SUBTHRESHOLD AND GATE-OXIDE LEAKAGE CURRENTS OF
LOW-V AND HIGH-V TRANSISTORS AT TWO DIFFERENT DIE TEMPERATURES
3 Transistor width
0:22 V. jHigh 0 V
0 and jV j = V
= 1 m. Transistor length = 45 nm. jLow 0 V j =
j = 0:35 V. V = 0:8 V. I
: V
=
.I
: jV j = jV j = jV j = V . For
each temperature, currents are normalized to the subthreshold leakage current
produced by the high-V pMOS transistor.
voltage state for simultaneously suppressing the subthreshold
and gate-oxide leakage currents. The proposed technique reduces the total leakage power by 56.1% to 97.6% as compared
to the standard dual- domino logic circuits.
This brief is organized as follows. The leakage current characteristics of domino circuits are described in Section II. The
new circuit technique to reduce the total leakage power is presented in Section III. Simulation results are given in Section IV.
Some conclusions are offered in Section V.
II. LEAKAGE CURRENT CHARACTERISTICS OF
DYNAMIC CMOS CIRCUITS
The leakage current characteristics of dynamic CMOS circuits are explored in this section. The subthreshold and gateoxide leakage currents produced by nMOS and pMOS transistors are compared in Section II-A. The leakage current characteristics of previously published sleep switch dual- domino
logic circuit techniques are discussed in Sections II-B and II-C.
A. Comparison of Gate Oxide and Subthreshold Leakage
Currents
A comparison of the normalized subthreshold and gate-oxide
leakage currents of low threshold voltage (low- ) and high
threshold voltage (high- ) transistors in a 45-nm dualCMOS technology is listed in Table I. The data are measured at
the upper and lower extremes of a typical temperature spectrum
of high-performance microprocessor dies.
produced by a low- nMOS transistor is 47 and
The
produced by a low- pMOS tran30 higher than the
sistor at 110 C and 25 C, respectively, as listed in Table I. In
a technology utilizing silicon dioxide as the gate dielectric material, the tunneling barrier for holes is significantly higher than
for a pMOS device
the tunneling barrier for electrons. The
is, therefore, lower as compared to an nMOS device with the
same physical dimensions (width, length, and ) and the same
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006
voltage difference across the gate insulator. Relatively higher
gate tunneling barrier for the holes is exploited in this brief to
reduce the gate-oxide leakage current overhead of the proposed
sleep switch circuit technique. Only pMOS sleep transistors are
employed to place a domino logic circuit into a low leakage
state.
B. Dual-
Domino Logic
transistors for subthreshold leakage
Employing dualcurrent reduction in domino logic circuits was first proposed
in [3]. Gating all of the inputs of the first stage of a domino
pipeline is proposed in [3] to place the idle domino circuits into
a low leakage state. Additional gates are employed at each input
of the first-stage domino gate in a multiple-stage domino logic
circuit with this technique. The clock is gated high, turning off
the high- precharge transistor when a domino logic circuit
is idle. The sleep signal transitions to high, activating the
pull-down network transistors regardless of the actual input
vector. The dynamic nodes of the first-stage domino gates are
discharged. After forcing the first-stage domino gates to evaluate and charge the outputs, the domino gates of the subsequent
stages in the pipeline also evaluate and charge the outputs.
The sleeping process is similar to dominos tipping over with
each stage triggering the next into a sleep state. After the node
voltages settle, all of the high- transistors are cut off, thereby
reducing the subthreshold leakage current as compared to a
low- circuit.
Similar subthreshold leakage current reduction techniques
based on discharging and charging the dynamic and output
nodes, respectively, of all the domino gates in a dynamic
circuit have been proposed in [2]–[5] and [9]. The high output
of an idle domino gate, however, places the fan-out domino
circuits into the highest gate-oxide leakage current state. The
techniques proposed in [2]–[5] and [9], therefore, increase the
gate-oxide leakage current while reducing the subthreshold
leakage current. In sub-65-nm CMOS technologies, a significant increase in gate-oxide leakage current could negate the
subthreshold leakage current reduction provided by these techniques, thereby increasing the total leakage energy consumed
by an idle domino circuit.
C. NMOS Sleep Switch Dual-
Domino Logic
For an idle dual- domino gate with high input vector, the
bulk of the gate tunneling current is produced by the lownMOS transistors in the pull-down network. Alternatively, the
subthreshold leakage current is produced by the high- tranof a low- nMOS transistors. As listed in Table I, the
of a
sistor is 4.7 and 159.1 higher than the
high- pMOS transistor at high and low die temperatures, reof a low- nMOS transistor
spectively. Similarly, the
of a highis 4.3 and 198.9 higher than the
nMOS transistor at high and low die temperatures, respectively.
Gate tunneling is, therefore, the dominant leakage mechanism
in a dual- domino gate (at both low and high die temperatures)
provided that the inputs are maintained high in the idle mode.
In addition to setting the dynamic node voltage low to reduce
the subthreshold leakage current, the output node of a domino
logic circuit should also be placed into a low voltage state to
Fig. 1. A k -input nMOS sleep switch dual-V domino OR gate in the sleep
mode. Gate-oxide leakage currents produced by the sleep transistors are illustrated with arrows. High-V transistors are represented by a thick line in the
channel region. L: Low voltage. H: High voltage.
suppress the gate-oxide leakage currents in the fan-out gates.
A technique to force the dynamic and output nodes of a domino
logic circuit into a low voltage state in standby mode is proposed
in [10]. Two high- nMOS sleep transistors (N1 and N2) are
placed at the dynamic and output nodes, as illustrated in Fig. 1.
In the standby mode, the clock is gated high. The sleep signal
is set high, turning on N1 and N2. The dynamic and output nodes
are discharged through N1 and N2, respectively. P3 is cut off
to avoid a static dc current path through P4 and N2. After the
dynamic and output nodes are discharged, the two nMOS sleep
transistors (N1 and N2) are in the maximum gate-oxide leakage
current state (see Fig. 1). Sleep transistors (N1, N2, and P3) are
required within every domino gate in a dynamic circuit designed
with the technique presented in [10]. The gate-oxide leakage
current overhead of nMOS sleep transistors, therefore, imposes
a serious limitation to the leakage current reduction that can be
provided with this technique.
III. LEAKAGE BIASED SLEEP SWITCH DUAL-
DOMINO LOGIC
A new circuit technique with enhanced effectiveness to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits is proposed in this brief. Only
P-type sleep transistors are employed to reduce the gate-oxide
leakage current overhead of the new sleep switch circuit technique. The proposed circuit technique is illustrated in Fig. 2.
A low- pMOS sleep transistor (P1) is added to the dynamic
node. A high- pMOS sleep transistor (P2) is also employed
to cut off the pull-up path of the output inverter during the sleep
mode.
In the active mode, the sleep signal is set high. P1 is cut off,
and P2 (driven by the inverted sleep signal) is turned on. The
domino gate operates similar to a standard dual- domino circuit. In the standby mode, the clock is gated high, turning off the
high- pull-up transistor. The sleep signal is set low, turning on
P1. P2 is cut off by the inverted sleep signal.
Two scenarios of entering the sleep mode must be considered with the proposed circuit technique. With the first possible
initial condition, the dynamic node is charged, and the output
node is discharged before entering the idle mode. After entering
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006
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Fig. 4. Delay of entering deep sleep with the second initial condition.
Fig. 2. A k -bit leakage biased dual-V domino multiplexer with low-V (P1)
and high-V (P2) pMOS sleep transistors. High-V transistors are represented
by a thick line in the channel region.
fan-out gates. The delay for entering a deep sleep mode with
this initial condition is longer than the sleep delay considered in
the previous paragraph since the output node is discharged by
leakage currents rather than an active sleep switch. Entering the
low leakage deep sleep mode with this initial condition takes
117–226 ns, as shown in Fig. 4.
IV. SIMULATION RESULTS
Fig. 3. Delay of entering deep sleep with the first initial condition.
the idle mode and turning on the sleep transistor, the dynamic
node is discharged to the threshold voltage of the low- pMOS
. The dynamic node is eventually dissleep transistor
by the high
charged to a steady-state voltage less than
subthreshold leakage currents of the low- nMOS transistors
in the pull-down network. The output node is already low before entering the idle mode with this scenario. Since the highsleep transistor P2 is cut off, the output node is maintained at
a low voltage during the idle mode. Entering the low leakage
deep sleep mode with this initial condition takes 2.5–8.5 ns depending on the type of circuit, as shown in Fig. 3 for three-stage
circuits (each gate drives a fan-out of four) in a 45-nm CMOS
technology.
With the second possible initial condition, the dynamic node
is discharged, and the output node is charged before entering the
idle mode. The dynamic node is maintained at a low voltage by
the activated low- pMOS sleep transistor and the subthreshold
leakage current produced by the pull-down network transistors.
The output node is discharged to a low steady-state voltage by
the subthreshold leakage current of the low- nMOS transistor
in the output inverter and the gate-oxide leakage current of the
BSIM4 device models are used in this brief for the accurate
estimation of gate-oxide leakage current [8]. The following circuits are simulated in a 45-nm CMOS technology (
V,
V, and
V): two-input domino AND gate (AND2), two-input, fourinput, and eight-input domino OR gates (OR2, OR4, and OR8, respectively), and a 16-bit domino multiplexer (MUX16). All of
the circuits (other than MUX16) are composed of three stages.
Each gate drives a fan-out of four. The domino gates in the
first stage are footed, while the gates in the second and third
stages are footless. All of the circuits are designed with the
following three techniques: 1) standard dual- domino (dual
); 2) the technique presented in [10] (dual- nMOS), and the
leakage biased sleep switch circuit technique proposed in this
brief (dual- LB). A 3-GHz clock is applied to the circuits. To
have a reasonable comparison, the circuits are sized to have a
similar worst-case propagation delay with each technique. Sleep
mode data are measured at 110 C and 25 C assuming short and
long idle periods, respectively. Active mode data are measured
at a worst-case temperature of 110 C.
A. Circuit Area and Active Mode Power Consumption
The layouts of the circuits are drawn assuming MOSIS deep
sub-micrometer design rules [12]. As shown in Fig. 2, a highpMOS transistor (P2) is placed in series with a low- pMOS
transistor of the output inverter in dual- LB circuits. The
physical size of pMOS transistors in the output inverters of
dual- LB circuits must be increased to provide an evaluation
delay similar to standard dual- circuits. Furthermore, an extra
pMOS sleep switch (P1) is added to the dynamic node. The
areas of the dual- LB circuits are, therefore, increased by
up to 77% (OR2) as compared to the standard dual- circuits
based on layout area comparison.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006
Fig. 5. Comparison of the active mode power consumption with the three
domino circuit techniques. For each circuit, power consumption is normalized
to the power consumed by the standard dual-V technique.
The active power consumption of domino circuits is shown
in Fig. 5. In dual- nMOS and dual- LB circuits, two pMOS
transistors are placed in series in the pull-up path of the output
inverter. Furthermore, P2 has a high . The driving capability
of the output inverter is, therefore, degraded. The physical size
of dual- LB and dual- nMOS circuits is increased to provide a propagation delay similar to standard dual- circuits.
Furthermore, the parasitic capacitance at the dynamic node is
increased due to the additional parasitic capacitance introduced
by the sleep transistor. Therefore, as shown in Fig. 5, the active
mode power consumption of the dual- LB and dual- nMOS
circuits is slightly higher than standard dual- circuits.
The dual- LB technique increases the active mode power
consumption by 1% (MUX16) to 3% (AND2) as compared to the
standard dual- domino logic circuits. Similarly, the dualnMOS technique increases the active mode power consumption by 1% (OR4) to 5% (AND2) as compared to the standard
dual- domino circuits. For a higher fan-in, the power overhead
of dual- LB and dual- nMOS techniques becomes smaller
since the parasitic capacitance introduced by the sleep transistors becomes less important as compared to the parasitic capacitance of pull-down network transistors. The difference between
the active power consumption of dual- LB and dual- nMOS
techniques is less than 2%.
B. Leakage Power Consumption at 110 C
In this section, the circuits are assumed to be operating at a
worst-case high temperature of 110 C before the beginning of
the idle mode. Furthermore, it is assumed that the idle mode is
short. The total leakage power consumption of the domino circuits at 110 C (assuming the die temperature does not significantly change during the short idle period) is shown in Fig. 6.
As described in Section III, the dynamic and output nodes of
an idle dual- LB circuit are eventually discharged to a low
voltage level by the initially high subthreshold and gate-oxide
leakage currents. Entering the deep sleep mode with the first
and second possible initial states at the beginning of the idle
mode takes less than 8.5 and 226 ns, respectively, for different
three-stage test circuits, as explained in Section III. Steady-state
dynamic and output node voltages in dual- LB domino circuits are well below
, as listed in Table II.
Fig. 6. Comparison of total leakage power consumed by domino circuits with
the three circuit techniques at 110 C. For each circuit, leakage power is normalized to the leakage power of standard dual-V technique with low inputs.
TABLE II
STEADY-STATE DYNAMIC AND OUTPUT NODE VOLTAGES IN
DUAL-V LB CIRCUITS
The subthreshold leakage current produced by a standard
domino logic circuit strongly depends on the dynamic and
output node voltages [6]. Two input conditions are simulated to
evaluate the leakage current in the sleep mode with the standard
dual- technique. The first condition assumes that all of the
inputs applied to the first-stage gates are low (low output node
voltage state). The second condition assumes that all of the
inputs applied to the first-stage gates are high (high output node
voltage state).
For an idle dual- domino gate, a high input vector turns
off the high- transistors, thereby reducing the subthreshold
leakage current. However, a high input vector also places the
pull-down network into the maximum gate tunneling current
of nMOS transistors is higher than the
state. Since the
of high- transistors at 110 C (see Table I), the
gate tunneling currents produced by the pull-down network transistors dominate the total leakage power consumption of an idle
dual- domino gate driven with high inputs even at this worstcase high temperature.
The dual- LB and dual- nMOS circuit techniques discharge the dynamic and output nodes of an idle domino gate,
thereby significantly reducing the subthreshold and gate-oxide
leakage currents as compared to the standard dual- domino
circuits. In a dual- nMOS gate, however, two nMOS sleep
transistors are employed at the dynamic and output nodes. After
the dynamic and output nodes are discharged by activating these
sleep transistors, both nMOS sleep transistors operate at the
maximum gate-oxide leakage current state throughout the idle
. Alternatively, in a dual- LB gate,
mode
only one pMOS sleep transistor is employed at the dynamic
node. Removing the sleep transistor at the output node reduces
the leakage and active mode power overhead of the dual- LB
technique. Furthermore, after P1 is activated, and the dynamic
node is discharged, the voltage difference across the gate-oxide
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006
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by effectively eliminating the gate-oxide leakage current overhead introduced by sleep transistors.
V. CONCLUSION
Fig. 7. Comparison of total leakage power consumed by domino circuits with
the three circuit techniques at 25 C. For each circuit, leakage power is normalized to the leakage power of standard dual-V technique with low inputs.
layer of P1 is maintained at approximately 0 V throughout the
. The dual- LB technique, thereidle mode
fore, eliminates the gate-oxide leakage current overhead of sleep
transistors.
The dual- LB technique reduces the total leakage power
by 56.1% (OR2) to 85.3% (MUX16) as compared to the standard
dual- circuits with a high input vector, as shown in Fig. 6.
Standard dual- circuits consume more leakage power with a
low input vector since the subthreshold leakage current is produced by the low- transistors when the inputs are low. The
dual- LB technique reduces the total leakage power by 90%
(AND2) to 97.6% (OR8) as compared to standard dual- circuits
with a low input vector. The dual- LB technique also reduces
the leakage power consumption by 4.6% (MUX16) to 20% (OR8)
as compared to the dual- nMOS technique due to the high gate
tunneling current overhead of the nMOS sleep switches with the
dual- nMOS technique.
C. Leakage Power Consumption at 25 C
In this section, the idle mode is assumed to be long. The die
temperature is assumed to be cooled to the ambient room temperature during long idle periods. The total leakage power consumption of the domino circuits at 25 C is compared in Fig. 7.
At room temperature, gate tunneling is the dominant leakage
mechanism (see Table I). Contrary to the previous low leakage
circuit techniques [2]–[5], maintaining the inputs low is preferable for reducing the total leakage power consumption of the
standard dual- domino circuits (except OR2) in this deeply
scaled nanometer CMOS technology [11].
The dual- LB technique reduces the total leakage power
by 87.8% (MUX16) to 96.7% (OR8) as compared to the standard
dual- circuits driven with low inputs, as shown in Fig. 7. For a
higher fan-in, the leakage power savings provided by the dualLB technique is enhanced (OR2: 92.9% versus OR8: 96.7%).
Standard dual- circuits consume more leakage power with a
high input vector due to the significant gate-oxide leakage current produced by nMOS transistors in the pull-down network
when the inputs are high. The dual- LB technique reduces
the total leakage power by 92% (OR2) to 97.2% (OR8) as compared to the standard dual- circuits driven with high inputs.
The dual- LB technique also reduces the total leakage power
by 22.8% to 50.6% as compared to the dual- nMOS technique
In sub-65-nm CMOS technologies, the subthreshold and
gate dielectric leakage currents need to be suppressed to reduce
the standby power consumption. A circuit technique based on
PMOS-only sleep transistors and a dual- CMOS technology
is presented in this brief for simultaneously reducing the
subthreshold and gate-oxide leakage currents in domino logic
circuits.
The proposed circuit technique based on pMOS sleep transistors exploits the initially high subthreshold and gate-oxide
leakage currents for placing an idle domino logic circuit into an
ultimately low leakage state. The dynamic node in a domino
logic gate is discharged through a pMOS sleep transistor in
the idle mode. The output node is also discharged by the initially high leakage currents of the output inverter and the fan-out
gates. Placing the dynamic node into a low voltage state reduces
the subthreshold leakage current by strongly turning off all of
the high threshold voltage transistors. Furthermore, placing the
output node into a low voltage state suppresses the gate dielectric tunneling currents in the fan-out gates.
The circuit technique reduces the total leakage power by
56.1% to 97.6% as compared to the standard dual- domino
circuits in sleep mode. Furthermore, by employing PMOS-only
sleep transistors, the presented circuit technique reduces the
total leakage power by 4.6% to 50.6% as compared to a previously published leakage reduction technique based on nMOS
sleep switches.
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