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A concept for power cycling the electronics of CALICE Peter Göttlicher, DESY-FEB Heidelberg September 15th, 2011 Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 1 Outline Motivation for power cycling Building blocks for power cycling Alternatives Consequences for power supplies Summary Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 2 Motivation Motivation: Power Cycling to avoid active Cooling Details see: P.Göttlicher, TWEPP-07, Prague, proceedings Page 296 𝜕𝑇 𝜕𝑡 Mechanical design constraint: - No cooling within calorimeter to keep homogeneity and simplicity - Cooling only at service end 1 𝑝𝑜𝑤𝑒𝑟 ℎ𝑒𝑎𝑡 𝑐𝑎𝑝./𝑎𝑟𝑒𝑎 𝑎𝑟𝑒𝑎 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛𝑖𝑐𝑠 𝜕2𝑇 + ℎ𝑒𝑎𝑡 𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑣𝑖𝑡𝑦 2 𝜕𝑧 = 40µW/channel Simplified model: - - No heat transfer radial “bad due to sandwich” Octagon as cylinder: No heat transfer in f Symmetry at IP-plane Temperature increase [K] 0.3 Solution: Parabel + Fourier terms 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 z = Position along beam axis [m] Very slow, but for long times Need Power cycling To keep heat up below 0.50C Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 3 Building blocks Building Blocks for the Power System 4. Power supply DAQ is Optical: No issue for EMI 1. Planes with scintillators and SiPM’s, ASIC’s and PCB’s 3. cable 5. Definition of GNDElectronics and GNDPE 2. End of layer electronics Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 4 Building blocks ASIC for fast SiPM Signals consuming Low Power L. Raux et al., SPIROC Measurement: Silicon Photomultiplier Integrated Readout Chips for ILC, Proc. 2008 IEEE Nuclear Science Symposium (NSS08) Algorithm for power cycling: The ASIC switches the current of the functional blocks OFF. ASIC gets supplied all the time with voltage. PCB electronics and instruments stabilize the voltage Functional tasks of the ASIC: Amp. Function switched ON SiPM 0.5% needed Digital data transfer ADC ASIC: SPIROC-2b RAM Bunches from collider (ILC/CLIC): A train every 200ms Fast amplifiers: 1ms ADC’s 3.2ms Common analogue parts, e.g. DAC’s, C-pipeline Digital control: 150ms >20µs ON before train 1µs Time Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 5 Building blocks ASIC as current switch Measured currents at the GND-supply of ASIC 10mA/pin ≜ GND pin (1 of 2) of ASIC Inductive current probes Slow probe 0.25 – 50MHz Tantal capacitor Bandpass: Slow: Fast: 30MHz-3GHz High pass of probe Measurements: - - Setup: ASIC+ capacitors on a PCB - Expectation is ~40mA/ASIC, summed over all pins Expected waveform, Amplitude is arb. units. 0 Measurement influence I-distribution to pins 30mA/pin ≜ System has to deal with: EMI: electromagnetic interference - Wide frequencies 5Hz to few 100MHz - Huge currents 2.2A for a layer, 3.4kA for AHCAL-barrel 200 600 [ns] time GND pin (1 of 2) of ASIC Voltage pin (1 of 3) for preamplifier Fast probe -20 400 0 time 20 40 60 [ns] Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 6 Building blocks Electro Magnetic Interference in a Power Cycled System Reference ground: return reference Safety. PE - Need good definition - Any induced/applied current produces voltage drops - Separation between reference / power return / safety or controlling currents and keeping currents within “own” volume and instrumentation Capacitive coupling To do: - Keep common mode voltage stable - Guide induces currents to source - Keep GND-reference closer than foreigns Current loops To do: - Controlling return currents - Keeping loops small - Avoid overlapping with foreign components. Guideline: Avoiding emission avoids in most cases picking up of noise Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 7 Building blocks Keeping the high Frequencies local: PCB itself Simulation model: “two diomensional delay line” 36 x 36 cm PCB with scintillators, SiPM’s LED 144mA switched current 1cm x 1cm Part of a thin cassette between absorber layer of HCAL Layer structure of PCB: GND d PCB= 50-60µm Vsupply GND By that one get - a thin PCB and also - A good high frequency capacitor 60pF/cm2 - Layout with short distance to via maintain the performance. Capacitor well known: 𝐴𝑟𝑒𝑎𝑒𝑙𝑒𝑚𝑒𝑛𝑡 𝐶𝑒𝑙𝑒𝑚𝑒𝑛𝑡 = 𝜀0 𝜀𝑟 𝑇ℎ𝑖𝑐𝑘𝑛𝑒𝑠𝑠𝑃𝐶𝐵−𝑙𝑎𝑦𝑒𝑟 One-dimensional delay well known 𝑡𝑖𝑚𝑒𝑒𝑙𝑒𝑚𝑒𝑛𝑡 = 𝑐 𝜀𝑟 𝑙𝑒𝑛𝑔𝑡ℎ𝑒𝑙𝑒𝑚𝑒𝑛𝑡 Inductivity: 𝐿𝑒𝑙𝑒𝑚𝑒𝑛𝑡 = 𝑡𝑖𝑚𝑒𝑒𝑙𝑒𝑚𝑒𝑛𝑡 2 /𝐶𝑒𝑙𝑒𝑚𝑒𝑛𝑡 Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 8 Building blocks Voltage for ASIC stabilized by local discrete Capacitors Capacitors mounted to the 36x36cm2 PCB Trust in simulation: - <1.5GHz=(1/10) granularity - No resistive behavior of ASIC is included. That over estimates the resonances at high frequencies Result: - Locally good for > 10kHz - Additional effort < 10kHz Impedance Z=|U|/|I| Oscillations are dumped for wide frequency range with phase ±900 Simulation of voltage induced by current 100 W Ceramics X7R 10 W 1W 0.1 W 00.1 W 900 U to I phase shift ASIC is supported over wide frequency range with Z< 0.1W 144mA generates <20mV Coil like 00 Capacitor like -900 1GHz 1MHz Frequency PCB-layer Dominated by: Tantal ceramic 1kHz Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 9 Building blocks Low frequency charge storage for < 10kHz At end of layer, there is a bit of - space - cooling C2 C3 Concept: - Charge for the train stored in a capacitor C2 - Voltage drop allowed ~ 0.6V - Fast voltage regulator ≫ 10𝑘𝐻𝑧, ≪ 10𝜇𝑠 - Charge for faster reaction is within the distributed capacitors + C3 C2 = 3.4mF bank of few Tantal a voltage regulator with external FET > 2A C3+distributed = 2mF Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 10 Building blocks Voltage at ASIC: Measurement Reduced test setup: Control board, 1 interconnect, 1 board Control electronics for layer Voltage step: - Measured 4mV, 400ns - Extrapolate to full system < 80mV at far end OK for operation, over-,undervoltage, time, … Induces current into GNDPE, if step is on GNDelectronics < 2 mA per layer Supply voltage of ASIC (AC-component) [mV] 2m2/Layer 1.3mm distance Stainless steel absorber = GNDPE C=13nF GNDelectronics 4mV Default setup Power on Command, step in IASIC Time [ns] OK, even with extrapolation to 1500 layers low? Investigations of reason and improvements possible, to be watched Peter Göttlicher | CALICE | Heidelberg, September 15 2011 | Page 11 th Building blocks Connection of GNDElectronics and GNDPE Control electronics for layer Definition of GND-point: - good for keeping sensitive SiPM’s stable - single connection to reduce currents in GNDPE system 2m2/Layer 1.3mm distance Stainless steel absorber = GNDPE C=13nF GNDelectronics Parasitic: Single PE: 105-106e- SiPM scintillator highest freqencies: The SiPM should not pickup noise from a floating PE-system: - amplifier_auto-trigger Connect as close as possible from GNDElectronics to GNDPE - power switching Low Impedance connection and not large wire loops Option as long as it is near by more connections within cassette, but risk of currents in the PE-system Mechanical easy accessible is the point as the end of layer at the DIF Nearest accessible point, at the layer (>100MHz) rely on: CLAYER_to_PE Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 12 Building blocks Integrating to Infrastructure C-,C+ 70pF/m from cable to support 𝜏 = 𝑅𝐶 50m cable, 1mm2, on a cable support Current induced into GNDPE Current per layer nA 0 𝜏 = 100𝑚𝑠 -40 𝜏 = 10𝑚𝑠 -80 𝜏 = 1𝑚𝑠 -120 -160 Ideal No parasitics no parameter spread C+=C- Simulation of cable 𝜏 = 0.1𝑚𝑠 0 1 2 3 time 4 5 [ms] 6 Impact of cable ASIC as switched current sink is a combination of choices: - Input filter: R=10W, C=1mF reasonable mechanical size EMI better t=100ms - Power supply behavior here neglected capacitance to PE, might be 2 order of magnitude larger than cable! Here: ideal V-source - Mechanical integration and galvanic isolation per (group or) layer and pair of wires for it With 1500 layers of AHCAL: IPE=120mA Really small, Ideal! No parasitic, C+=C-! Don’t be too reluctant in EMI-rules Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 13 Building blocks Current in Supply Cable Reduced test setup: Control board, 1 interconnect, 1 board, Short cable to laboratory supply Current per 1/18 layer in supply cable [mA] Control electronics for layer Preamplifiers ON ADC’s ON Work bench settings Without input filter with input filter t=10ms Input filter important to Frequencies are low lower amplitude fluctuations and remaining frequencies within cable Important: EMI-crosstalk to others Electronics like to have larger t to smoothen further Mechanics easier in service-hall Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 14 Cabling a multi layer calorimeter: Six such cables would allow 48 layers - Individual connected and galvanic isolation outside ILD or as compromise filter with ferrits - Additional covers, tubes for flammability? Special production: wires/cable optimized - On picture 4 x 0.5mm2 : 12V (LED) just from DESY-stock 6V ASIC, FPGA, … GND Bias (120V) 2 Locally 0.5mm would be fine For 50m 1mm2 or more would be better Issue is less than a factor 2 in cross section! - It is work to manufacture! But feasible for 1500 layers! - How many wire per cable? Small total cross section or good bending? An idea but not the only and not work through! Option ?: Less power supply channels Group of Components on board DIF wires DIF Split point of wire steel Two layers grouped: Still easy low-L access to GNDPE Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 15 Alternatives: Star grounding Frequency dependent: PE is whole metal structure of ILD Power routing has to be parallel to GND rooting with low L and R>L*w But points are not points, they have a size Loop 1 Large loops Large Inductance: Antenna SiPM surrounding is worsened Transformers to own and foreign Connectors Has to withstand group current Parasitic current from loop 1: Worsened for: - Common return paths to own and foreign Cross talks and pickup noise - It will not stay locally for low frequencies Also to ILD magnet: Quench or fast discharge not yet studied, but larger loops are worse: Resistance needed? Nowadays: Systems have noise from switching power and faster digital edges It’s a system issue and therefore tends to appear late completeness of ILD and risk at all modifications Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 16 Consequences per power supply Multichannel systems are available with basic features - With galvanic isolation per channel - Low ripple: 5-10(20) mVpp Their development was (partially) driven by research WIENER, CAEN, ISEG, and ?????? Comparison of AHCAL needs to a WIENER system To be done? Longer scale or next steps: Adaptation/development: - Research center/industry? - Can lower power be converted to more channels? … if 1 to 1in power : More than 400 channels per crate Getting fast running: - Selecting a system and buy - Programming for combined power supply and DIF/uC MPOD just because other project AHCAL: (not final, not optimized/fully understood) - Single chan., - Group of three voltages allowed - 6V/1-2A, 12V/0.1A, 120V/5mA at DIF - 50W per channel - Constant V with -- Up to now: constant voltage with over current trip over current trip is studied Option: Constant current or impedance controlled, if performance gets better - Just 80chan/crate, - 1500 layers …. 4500 voltages but each 50W. see option to group 2 layers - 5-10mVpp - Low ripple/noise because sensitive ILD-detector - Floating to PE, limited to ±24V? - Small coupling to GNDPE, but good EMI compared: 50m cable on PE: 3.5nF. - Cope with fluctuation current: typical: 800mA/layer, 2ms Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 17 Summary Power cycling allows to reduce heat by factor 100! Coherent fast switching ON/OFF of high current: CALICE-AHCAL: 2.2A*layers : 3.4kA for the barrel 5Hz to few 100MHz System aspects at local design…. Not only power-pulsing also EMI - Local defined return-paths for current - Local charge storage for wide frequency range that keeps - the impedance small - the currents leaving a defined volume small with slow rise times System aspects within the infrastructure Lower frequency part handled by cables and power supply Good integration of power supplies and cables. Simulation leaves many parasitic/accuracy effects out Underestimates the high frequency EMI-disturbance …. Experiments, concepts to be better than simulation promises Experimental setups and integration into ILD to be continued Peter Göttlicher | CALICE | Heidelberg, September 15th 2011 | Page 18