Download LCA-XXX-CCD-REB

[[Document
Number]]
Power-up and shutdown procedures for REBs and CCDs
Document No.
Page 1 of 8
Status
[[Document Number]]
Author(s)
[[Document Type]]
Draft
C. Juramy
[[Author 3]]
[[Author 2]]
[[Author 4]]
Subsystem
[[Subsystem]]
Document Title
Power-up and shutdown procedures for REBs and CCDs
1
Change History Log
Revision
Effective Date
Description of Changes
Draft
2
Contents
1
2
3
4
5
6
Change History Log .............................................................................................................................................................. 1
Contents ................................................................................................................................................................................ 1
List of Tables ........................................................................................................................................................................ 1
Purpose and Scope ................................................................................................................................................................ 2
Applicable Documents and Reference Documents ............................................................................................................... 2
Definitions ............................................................................................................................................................................ 2
6.1 Acronyms ....................................................................................................................................................................... 2
6.2 Definitions...................................................................................................................................................................... 3
7 CCD safety requirements ...................................................................................................................................................... 3
7.1 Voltage limits ................................................................................................................................................................. 3
7.2 Power-on and shutdown ................................................................................................................................................. 4
8 Electronics safety requirements ............................................................................................................................................ 5
9 Safe power-up sequence........................................................................................................................................................ 5
9.1 Unipolar operation (E2V) .............................................................................................................................................. 5
9.2 Bipolar operation (ITL CCD)......................................................................................................................................... 6
10 Safe shutdown sequence ...................................................................................................................................................... 7
10.1 Controlled shutdown .................................................................................................................................................... 7
10.2 Power failure ................................................................................................................................................................ 7
10.3 Communications failure ............................................................................................................................................... 7
3
List of Tables
Table 1: Acronyms ...................................................................................................................................................................... 2
Table 2: Definitions ..................................................................................................................................................................... 3
Table 3: Vendors Biases and Clocks recommendations (in Volts) for the various CCD considered for LSST........................... 4
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.
[[Document
Number]]
4
Power-up and shutdown procedures for REBs and CCDs
Page 2 of 8
Purpose and Scope
The goal of this document is to gather requirements for the safe power-up and shutdown of both the
CCDs themselves and the Electronics Board connected to them. We want to point out some useful
elements in the design of the Electronics Board, drawing mainly on the current design of the WGREB,
and to derive requirements for the correct operation of the CCD electronics. This should be available to
the designers of the electronics boards and to the software engineers programming the camera
operations. We should in particular make clear which safety features must be guaranteed by hardware
and which will have to be implemented in the software.
We will consider a number of cases in this document: CCDs from the two vendors (E2V and ITL) with
their different voltages, whether we use the CABAC chip only for clocks (as CABAC1 is used in
practice) or for biases also (hopefully the way CABAC2 will be used).
5
Applicable Documents and Reference Documents
The following documents are applicable and form a part of this design document:
Ref #
Document Number and Title
[5]
LCA-10927 “Sensor Safety & CABAC”
The following documents are cited for reference only, and do NOT form a part of this design document:
Ref #
Document Number and Title
[2]
ITL STA 3800B CCD : Operating parameters (ITL doc number : ITL1647)
[3]
ITL : Response to SLAC RFP101613
[3]
LSST CCD 250 Development : Test Plan
[]
LCA-11548 CABAC2 Implementation
[]
LCA-10820 WGREB Schematic
6
Definitions
6.1
Acronyms
Table 1: Acronyms
Acronym
Definition
REB
Raft Electronics Board
WGREB
Wavefront Guider REB
CCD
Charge-Coupled Device
CABAC
Clock And Biases ASIC for CCD
OD
Output Drain: the voltage sent to every CCD channel on the drain of the output transistor.
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.
[[Document
Number]]
Power-up and shutdown procedures for REBs and CCDs
Page 3 of 8
OS
Output Source: the source side of the output transistor of the CCD, where the CCD signal
comes out.
RD
Reset Drain: the voltage sent to the drain of the reset transistor of the CCD outputs.
GD / SV
Guard Drain (E2V) or Scupper Voltage (ITL): voltage sent to the guard ring running around the
CCD.
OG
Output Gate: electrode at the last step in the serial register before the CCD output node.
Voltage should be in the same range as the serial clock rails. Counter-intuitively, it has no direct
relation to OD and OS.
FS
Front Substrate: substrate voltage on the front side of the CCD, where all clocks and amplifiers
are implanted. In this document, connected to electronic ground.
BS / BSS
Back Substrate: strongly negative voltage sent to the CCD back side.
CS
Current Source: current load at the CCD outputs.
6.2
Definitions
Table 2: Definitions
Term
Definition
DC outputs
All DC outputs required by the CCD and provided by the Electronics Board: ODs, RD,
GD, OG (not BS).
Drains
All drain voltages: ODs, RD, GD. All must be above the CCD front substrate at any time.
Electronics Board
REB or WGREB
VddOD
Power supply rail for the high-voltage DC outputs, supplied either to CABAC or to
discrete amplifiers. In the second case, this can be the value of the ODs.
7
CCD safety requirements
CCD safety is ensured by providing voltages within the right range and in the right order.
7.1
Voltage limits
Some conditions on voltages are common to both types of CCD considered for LSST: the Drains must
always be higher than the Front Substrate (in the cases we consider here, FS is connected to the
Electronics Board ground), OG must be in the same range as the clocks. As long as the power supplies
are correct, these conditions can be guaranteed by adding the appropriate diodes on the board, to
constrain the Drains between FS and VddOD and OG between the clock rail supplies.
E2V 250
Min.
Nom.
Max.
BS: Back Substrate
0.1
-70
-100(?)
FS: Front Substrate
0
0
GD: Guard Diode
0.2
30
30.5
OD: Output Drain
0.2
30
30.5
Other
Biases
0.5
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.
[[Document
Number]]
Power-up and shutdown procedures for REBs and CCDs
OG: Output Gate
0
3
5
RD: Reset Drain
0.2
18
20
Page 4 of 8
OD-RD < 20V
Clocks
RG: Reset Gate
0
0;12
12
Ix: Image Clocks
0
0;11
11
Rx: Register Clocks
0.5
0.5;10
10
ITL/STA 3800B
Min.
Nom.
Max.
Absolute
Min.
Absolute
Max.
BS : Back Substrate
-70
-50
0
-
-
FS : Front Substrate
-
0
-
-
SC: Scupper Voltage
-
+20
-
-0.3
+35
OD: Output Drain
+24
+26
+30
-0.3
+35
OG: Output Gate
-2
+1
+2.0
-20
+20
RD: Reset Drain
+14
+16
+18
-0.3
+35
Biases
-
Clocks
RG: Reset Gate
-5
-5;+5
+12
-20
+20
Px: Parallels Clocks
-12
-9;+3
+6
-20
+20
Rx: Serial Clocks
-8
-5,+5
+8
-20
+20
Table 3: Vendors Biases and Clocks recommendations (in Volts) for the various CCD considered
for LSST.
7.2
Power-on and shutdown
For both types of CCDs, the main safety requirement is that BS must be activated after the other DC
voltages, in particular the Drains, and must be de-activated before the others. On the WGREB, this is
controlled by an output of the FPGA that must be activated manually when the drains are at the correct
value. With a CABAC providing the biases, this can be controlled both by readback of the programmed
value and through the internal multiplexer. With external biases there is currently no control mechanism.
The power-on sequence established from earlier discussions is (source ?):
1) Drains first, with RD before OD or at the same time, to ensure that OD remains below RD+20V.
2) OG
3) Clocks
4) BS
The power-down sequence is the exact reverse.
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.
[[Document
Number]]
8
Power-up and shutdown procedures for REBs and CCDs
Page 5 of 8
Electronics safety requirements
Here we do not discuss protection of electronics against accidental events, such as ESD, but during
routine operations. The need for protection of electronics regards the CABAC chip, which has some
conditions that must be respected to avoid damaging the chip.
The CABAC supply voltages must respect these conditions:
– FVDD40 is always the highest voltage applied on CABAC
– Vsub (chip substrate) is always the lowest voltage on CABAC
– VDD_CK_U (upper clock rail) is greater than VDD_CK_L (lower clock rail) for all three clock
rails (serial, parallel, Reset Gate)
To help protect CABAC, there are diodes on the WGREB between each low clock rail and Vsub, and
between the high and low clock rails.
To respect these conditions during power-on and shutdown of CABAC, a sequence is proposed for
power-on:
1) FVDD40 & VddOD (bias supply)
2) Vsub
3) All FVDD & BVDD (low voltage supplies)
4) VDD_CK_U & VDD_CK_L
The delay between steps can be as low as a few milliseconds, and should not exceed a few seconds. The
shutdown sequence is again the same in reverse order.
The WGREB has also diodes to protect the rest of the components from unexpected values (>5V or
below GND) in the multiplexer outputs of the CABAC.
9
Safe power-up sequence
The power-up sequence of the system should ideally be separated in two sequences: first powering up
the Electronics Board, to put it in a ready state, without affecting the CCD; then powering up the CCD
with the recommended sequence. Conversely, powering down should be separated into powering down
of the CCD, followed by the Electronics Board. In particular, this allows to power down the CCD
temporarily (i.e., in a lab setting, when it is exposed to ambient light), while leaving the electronics
ready.
9.1
Unipolar operation (E2V)
In this configuration, all voltages are positive, except possibly a small negative voltage on one clock rail
in a particular mode (which should be applied to CABAC Vsub and the appropriate clock rail at that
point, not at any other moment).
This is what we have currently as a power-on sequence for the WGREB, if using CABAC1 only for
clocks:
1) Power on RCM translation board and FPGA. Reset communications. Put default state at 0 for all
clocks (so that the clocks stay at the low clock rails when they are powered on).
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.
[[Document
Number]]
Power-up and shutdown procedures for REBs and CCDs
Page 6 of 8
2) Power on simultaneously all WGREB power supplies (CABAC1 only sees the clock rail supply
instead of VddOD, so a relatively low voltage – this is specifically required by CABAC1 and
should not be an issue in CABAC2).
3) Enable low voltage power supplies to CABAC.
4) Set clock rail DACs (in WGREB the parallel clock rails are provided directly, and should be
powered on here).
5) Disable CABAC1 safeties and program an intermediate bias value – higher than 0, lower than the
clock rail (specific to CABAC1).
Then for the CCD power-up:
1) Set drains, activating all simultaneously.
2) Set OG.
3) Set clock currents in CABAC.
4) Set currents on CS. There is currently no recommendation that I know of as to when we should do
this.
5) Load sequencer, or if done before, reload only the default state. This can put some clocks to their
high rails.
6) Enable and power on BS.
Rather than discussing the use of CABAC1 for biases, this would be the Electronics Board power-on
sequence using a working CABAC2 for biases and clocks:
1) Power on RCM translation board and FPGA. Reset communications. Put default state at 0 for all
clocks.
2) Power on Electronics Board power supplies: VddOD, board supplies, clock rails supplies (but the
clock rails are not set yet). Vsub should be 0V at this point, and all supplies positive.
3) Power on / enable low voltage power supplies to CABAC. CABAC2 biases start at Vsub = 0V at
power-on (this was not the case for CABAC0), so the CCD is safe.
4) Set clock rail DACs (and power on the parallel clock rails if they are provided directly).
Items 2), 3), and 4) should be executed within seconds of each other, preferably under one second.
Then for the CCD power-up, the only things that change is the fact that we can check every DC output
before proceeding to the next step, and the first step:
1) Set drains, using two steps to avoid large differentials between OD and RD (we can only program
one CABAC2 parameter at a time). Check.
9.2
Bipolar operation (ITL CCD)
Note that we do not consider here the case where the front substrate of the CCD is shifted instead and
the electronics operate in unipolar mode. This latter mode of operation is not recommended by the
vendor, and it presents some major safety issues that make it a completely separate case.
The difficulty in bipolar operation is in powering up the Electronics Board while keeping the CCD
inputs at 0. If we are using the CABAC only for clocks on WGREB, this is the power-on sequence we
should be using for the Electronics Board:
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.
[[Document
Number]]
Power-up and shutdown procedures for REBs and CCDs
Page 7 of 8
1) Power on RCM translation board and FPGA. Reset communications. Set the default state for
clocks, depending on the choice made in step 4).
2) Power on Electronics Board power supplies: VddOD, Vsub, board supplies, clock rails supplies
(not parallel clock rails).
3) Enable low voltage power supplies to CABAC.
4) Set clock rail DACs (and power on parallel clock rails) so that for each type of clock either the
low clock rail or the high clock rail is at 0V, while the other is at its final value.
5) Disable CABAC1 safeties and program an intermediate bias value (specific to CABAC1).
If using CABAC2 for biases, we can follow the same sequence, with 5) being the programming of all
DC outputs to 0. Then we have to rely on the protection diodes to keep the drains above FS in the time
between Vsub being turned on and the CABAC DC outputs being programmed. We need to know that
this does not damage the CABAC.
The CCD power-up sequences are almost the same as in unipolar operations, but the ‘clock’ step (step 3)
above) includes putting all clock rails at their operational values.
To avoid changing the clock rails in the middle of the sequence, we could consider an alternative
sequence that mixes Electronics Board power-on and CCD power-on. However it would be not
advisable when using CABAC, even only for the clocks, as the clock rails would then be provided only
after the DC outputs to the CCD have been set. This would however be a possible sequence with a
COTS-only solution.
10
10.1
Safe shutdown sequence
Controlled shutdown
Usually the reverse of the power-on sequences.
10.2
Power failure
BS is shutdown by FPGA enable ?
CABAC: should shutdown all supplies if one fails.
10.3
Communications failure
Currently a drop in communication with the acquisition system requires a reboot of the FPGA on the
REB, by shutting down its power supply. This is a problem because we cannot communicate to the
CABACs and DACs for a clean shutdown. Powering down from the power supplies is the only solution.
If using CABAC for biases, the sequence should be: dropping BS, then the clock rails supplies, then the
low voltages including the FPGA, and finally the high-voltage bias supply VddOD. This should shut
down clocks first on the CCD, with the biases following the CABAC shutdown. Vsub is an issue if it
was negative: if we shut it after the low voltages, there is a transitory moment where we rely on the
diodes to keep the Drains above FS. Otherwise, if we shut it down at the same time as the clocks, we
have a transitory spike in values on the biases, again limited by diodes to VddOD (and to 0 for OG).
Otherwise, if using CABAC only for clocks, the sequence should be: BS, then the FPGA (to disable
CABAC low voltages), then the clock rails (to finish shutting down CABAC and shut down clocks to
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.
[[Document
Number]]
Power-up and shutdown procedures for REBs and CCDs
Page 8 of 8
the CCD), then the other low voltages and VddOD together (to shut down biases to the CCD). This
relies on the FPGA and other low voltages being separate, to maintain bias outputs at first.
Hard copies of this document are for REFERENCE ONLY
and should not be considered the latest revision beyond the date of printing.
See https://www.lsstcorp.org/docushare for the most recent revision and approval information.