Download Evolutionary Optimization of Combinational Digital

EVOLUTIONARY OPTIMIZATION OF
COMBINATIONAL DIGITAL CIRCUITS
WITH CURRENT-MODE GATES WITH
RESPECT TO TRANSISTOR COUNT
Adam SŁOWIK1 , Michał BIAŁKO2 , Oleg MASLENNIKOW3
1,2,3
Department of Electronics and Computer Science,
Technical University of Koszalin, Koszalin, Poland
E-mail: 1 [email protected], 2 [email protected],
3
[email protected]
Abstract
In the paper, an evolutionary method for minimization of transistor number in combinational digital circuits, realized using current-mode gates,
is presented. In applied evolutionary algorithm multiple-layer chromosomes, increasing a circuit optimization efficiency, are introduced. The
results, obtained using described here method, are compared with results
obtained using the Karnaugh-Maps, and logical function minimization
methods used in algebra of current-mode gates. In most cases described
method leads to better results.
Keywords: artificial intelligence, evolutionary algorithm, current-mode
gates, design, optimization, digital circuit
1
Introduction - properties of current-mode gates
The main property of newly introduced current-mode gates [1] is a constant
current consumption (from the power supply source) during "low" and "high"
state of the gates, resulting in much lower distortions of analog circuits in
mixed analog-digital circuits. Four types of current-mode gates for realizations
of more complex digital circuits are introduced: an inverter, an anti-inverter, a
doubled-inverter, and an anti-doubled-inverter. Symbols and functions realized
by these gates, are shown in Figure 1 [2].
Figure 1. Symbols of current-mode gates and their functions: inverter (a), antiinverter (b), doubled-inverter (c), anti-doubled-inverter (d), structure of multipleoutput current-mode gate (e)
A current-mode technics enables to realize multiple-output gates which
have modular structure. Such gates are composed of input sub-circuit (comparator K composed of 4 MOS transistors) and one or more output sub-circuits
of an inverter type I (composed of 3 MOS transistors) or an anti-inverter
type AI (composed of 2 MOS transistors). An example of 4-output gate with
four different output types composed of 20 transistors, is shown in Figure 1e.
Practically realized current-mode gates have low impedance inputs and high
impedance outputs, allowing simple realization of algebraic addition (summing up output currents from different gates in a single input node). During
design process of current-mode logic combinational digital circuits, different
methods, used in voltage-mode logic, are applied such as: Karnaugh-Maps
[11], Quine-McCluskey [12, 13] to obtain circuit fulfilling required "truth table". Then, the current-mode circuit is optimized with respect to minimal number of gates or transistors, depending on chosen optimization criterion [2, 3,
4, 5]. In this paper a method for optimization of current-mode combinational
digital circuits is presented. The method named MLCEA-CML (Multi Layer
Chromosome Evolutionary Algorithm - Current Mode Logic), is based on previously introduced MLCEA method [7] suitable for voltage-mode digital circuits. Since current-mode logic gates and combinational circuits are rather
new techniques, therefore there is no descriptions of evolutionary optimization
methods for such circuits, and described here method is the first attempt in this
field.
2
2.1
MLCEA-CML Method
Representation of Individuals (Chromosomes)
To create an initial population for evolutionary algorithm [8, 9, 10] a gate
pattern, shown in Figure 2a, is created. This pattern is composed of t currentmode gates, each having single inputs and p outputs. The goal of the algorithm
is to find in the pattern such a set of gates, and connections between them, that
fulfills the constraints posed by the truth table of the required circuit. Additionally, the circuit should have the lowest possible number of transistors. In
the presented algorithm multiple-layer chromosomes [7] are introduced, which
make optimization more effective. The structure of chromosomes and data
coding are shown in Figure 2b. The first k columns of the chromosome represent subsequent circuit inputs. In the first row of these columns in the place
"circuit input no. x", the number of the gate to which input the given circuit
input is to be connected, is written down; in the p+1 row, the number "7" representing the circuit inputs, is written down, whereas genes in the rest rows are
filled with "0", representing a lack of connection. The last f columns represent
subsequent outputs of considered circuit. In the p+1 row of these columns the
number "8" representing the circuit output, is written down, whereas the rest of
rows are filled with "0" (lack of connection). Each column of the chromosome,
marked from k+1 up to k+t (t - number of gates in the pattern) corresponds to
selected gate of the pattern; the rows from 1 up to p (p - number of gate outputs) correspond to gate outputs, and the rows from p+1 up to p+p represent
the types of these outputs, as is explained in Figure 1. In the chromosome,
in the place "gate output no. x" the gate number or circuit output number is
written down to which this "gate output no. x" is to be connected (circuit outputs are marked by negative number; e.g. "-1" corresponds to circuit output
no. 1); whereas, in the place "type of output no. x" one of digits (from 1 to 6)
is inserted, which represent (see Figure 1): "1"-inverter, "2"-anti-inverter, "3"doubled-inverter, "4"-anti-doubled-inverter, "5"-open circuit, "6"-short-circuit
of the first gate output with its input (the rest of outputs are open circuits). For
example, in Figure 3 a digital circuit composed of single and double output
current-mode gates, fulfilling the "truth table" for circuit no. 1 from Table 1, is
shown; the gate pattern, corresponding to this circuit is shown in Figure 4, and
corresponding to it the multiple-layer chromosome is shown in Figure 5.
Figure 2. Structure of circuit coding: pattern (a), chromosome (b)
Figure 3. Example of digital circuit
Figure 4. Corresponding to circuit (from Figure 3) pattern of gates
Figure 5. Multiple-layer chromosome representing pattern of gates from Figure 4
The circuit of Figure 3 is composed of 9 gates (t=9) having maximal number of outputs 2 (p=2), has 3 inputs (k=3), and 1 output (f =1). Therefore,
the pattern has 3 inputs, 9 places for gates of different types (with single or
doubled outputs) and 1 output; whereas, the data structure for evolutionary algorithm is in the form of multiple-layer chromosome which has 2p=4 layers
with k+t+f =13 gates in each layer.
2.2
Description of Evolutionary Algorithm
At the beginning of the operation of algorithm an initial random population
of chromosomes is created (the chromosomes should represent circuits without
feedback). Next, in the place of randomly chosen chromosome, the solution
(accepted circuit configuration fulfilling given truth table) obtained using typical design methods, is inserted. Then, the fitness of each chromosome to the
objective function is evaluated; the objective function FC1 is defined as follows:
v · j when O(ci ) Ci
(1)
f ci =
0
when O(ci ) = Ci
I
f ci = 0
NT
when i=1
I
I
(2)
FC1 =
NT + w + i=1 f ci when i=1 f ci > 0
where: v-positive real number (in experiments v=10), ci -vector containing ith
combination of input signals (truth table), O(ci )-vector of circuit response for
ci at the circuit input, Ci -vector containing proper circuit response (truth table), j-number of differences on particular positions in vectors O(ci ) and Ci ,
NT-number of transistors, I-number of signal vectors in the truth table, wpenalty value (in experiments w=105 ). The function FC1 is minimized during
the algorithm operation. After evaluation of individuals, an elitist selection is
performed, and then, crossing-over and mutation are performed, and operation
is repeated. Then, convergence of the algorithm is checked (lack of changes of
the best solution through k generations).
2.3
Genetic Operators
Introduced cross-over and mutation operators operate on 2p-layer chromosome. The single-point cross-over "cuts" the chromosome through all 2p layers
in a single randomly chosen point; then the cut parts of two randomly selected
chromosomes are exchanged. Such a cross-over of 2p layer chromosomes creates new child-individuals (new circuits) with gates having unchanged output
structure. The mutation operator acts only on genes representing circuit inputs
(k columns) and gates (t columns) of the pattern. In the case when to mutation
the gene, representing the circuit input, has been selected, then the number
from the range [1, t] has been randomly selected and substituted to this gene;
this operation corresponds to change of connection of particular circuit input
to different gate. In the case, when to mutation the gene corresponding to particular gate, and located in the layer of the range [1, p], has been selected, then
new gate output connections to the other gate input in the pattern or to the circuit output are randomly chosen; however, when the gene located in the layer
of the range [p+1, 2p] has been selected, then the type of the gate output is
changed (random choice of number of the range [1, 6]).
3
Description of Experiments
During experiments the algorithm parameters were as follows: population
size = 100, crossover probability = 0.5, mutation probability = 0.05. Considered four circuits were composed of two-output current-mode gates. In Table
1, and Table 2 the truth tables (taken from [7]) for each designed circuit are
presented. Circuit No. 1 have three inputs and single output, Circuit No. 2
have four inputs and single output, Circuit No. 3 have four inputs and single output, and Circuit No. 4 have four inputs and 3 outputs. Symbol "In"
represent inputs, and symbol "O" corresponds to circuit outputs.
Table 1. Truth tables of designed circuits no. 1, and no. 2
Circuit no.
In
X Y Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
O
F
0
0
0
1
0
1
1
0
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Circuit no. 2
In
O
W X Y F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
Table 2. Truth tables of designed circuits no. 3, and no. 4
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Circuit no. 3
In
O
B C D F
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Circuit no. 4
In
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X2
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
O
X1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
X0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
In Table 3 results of optimization of considered circuits are presented; the
results concern number of gates (NG) and number of transistors (NT) required
for particular circuit realization during design and optimization performed using different methods: Karnaugh Maps (KM), human design (HD) using Karnaugh Maps and minimization of logic functions in a current-mode algebra [3,
4, 5, 6], and using described MLCEA-CML evolutionary algorithm (MCML).
Table 3. Comparison of optimization results for considered circuits
Method
KM
HD
MCML
Circuit No. 1
NG
NT
9
99
5
45
5
45
Circuit No. 2
NG
NT
26
305
14
165
9
100
Circuit No. 3
NG
NT
13
145
13
145
6
62
Circuit No. 4
NG
NT
39
465
27
311
11
128
4
Conclusions
The results presented in Table 3 show, that the circuits optimized using
described here MLCEA-CML (MCML) algorithm require equal or less number
of gates and transistors compared to human design methods. The benefit of
using evolutionary algorithm is more visible for more complicated circuits; for
simple Circuit No. 1 the number of gates and transistors is equal for HD and
MCML methods, however for more complicated Circuits No. 3 and No. 4 the
number of gates and transistors is more than two times lower for evolutionary
method.
Acknowledgments
This work was supported by the Polish Ministry of Scientific Research and
Information Technology (MNiI) under Grant No. 3 T11B 025 29.
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