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Implementation of Ternary Logic Circuits Ashutosh Kumar Singh PG Student, Noida Institute Of Engineering & Technology, Greater Noida,U.P, India. 1 [email protected] Deepak Bhardwaj Assistant Professor, Noida Institute Of Engineering & Technology, Greater Noida,U.P, India. 2 [email protected], Abstract- In this paper logic circuit designs using the circuit model of three state gate field effect transistors are discussed. One intermediate state between the two normal stable ON and OFF states is produced by change in the threshold voltage over this range. A simplified circuit model that accounts for this intermediate state is developed and interesting logic is implemented. The design of various two input three state gates including NAND and NOR like operations and this application in combinational circuit like full adder is discussed. The number of bit handling capacity of device will be increased by increasing no of states . This will help to handle more no of bits at a time with less circuit developments. Index Terms – VLSI, Ternary logic, Integrated circuits, Handling capacity I. INTRODUCTION According to Moore’s law, the transistor density in the integrated circuits doubles after every 2 years. There are two approaches to follow Moore’s law: one is to decrease the dimensions of the electronic devices and the other one is to increase the bit- handling capacity per device. As the different dimensions of the device decrease, other issues like gate leakage current [1]–[3], ON–OFF ratio as well as the noise margin, and so on also degrade. So the second approach, that is, to increase the bit-handling capacity per transistor, becomes more important to achieve Moore’s law. Multivalued logic (MVL) has the following advantages. 1) In MVL, each wire can transmit more MVL information than a binary element. As a result, the number of connections inside the chip can be reduced. 2) In MVL, the complexity of circuits may be decreased. 3) The ON- and OFF-chip connections can be reduced to help alleviate the pin-out difficulties that arise with increasingly larger chips. \ V. K. Pandey Dr.(Professor), Noida Institute Of Engineering & Technology, Greater Noida,U.P, India 3 [email protected] 4) The speed of serial information transmission will be faster since the transmitted information per unit time is increased. However, theory also predicts several disadvantages of using MVL circuits. 1) For fixed values of the highest and the lowest voltages, the tolerances of the MVL circuits with more logic levels will be more critical than the binary circuits. 2) To realize low-output impedance, additional sources of power are necessary to produce the intermediate voltage outputs. 3) The process technology for the MVL circuit may be more complicated because the elements in a circuit must deal with multivalued signals. MVL can be implemented using different kinds of devices like resonant tunneling diodes [4]–[6], resonant tunneling transistors [7]–[9], modulationdoped FETs [10]–[12], high electron mobility transistors [13]–[15], carbon nano tube field effect transistors (CNTFETs), single electron transistors (SETs), and so on. Among these semiconductor devices, CNTFET and SET are the most promising devices to implement the MVL in future. A conventional metal-oxide-semiconductor field effect transistor (MOSFET) conducts when the applied gate voltage is more than the threshold voltage of the device. Therefore, a MOSFET acts as a switch which cannot conduct below its threshold voltage and conducts beyond its threshold voltage. This paper discus the quantum dot gate FET (QDGFET) that produces three states in its transfer characteristic: OFF, ON and a low current saturation state known as intermediate state ("i") because of the presence of quantum dots in the gate region. The complementary function shows the use of QDGFETs in a three-state single-input function. In order to build more useful circuits with three states or ternary logic, it is necessary to construct a set of twoinput gate functions. With the binary logic, the basic two-input functions are AND and OR. With the ternary logic, we can build analogs of ANDs and Ors that have slightly different meanings. Kleene developed a set of functions for the three-valued logic that has been termed Kleene’s logic. This logic has three states: True (T), False (F), and Undefined (U). Kleene also defined the functions A ˆ B and A ˇ B as shown in Table I. Therefore, F corresponds to state 0, U corresponds to state 1, and T corresponds to state 2. In this case, undefined is a distinct third state or the intermediate state. TABLE I KLEENE’S LOGIC A F F F U U U T T T B F U T F U T F U T AˆB F F F F U U F U T AˇB F U T U U T T T T Fig.1. PSPICE Schematic of STI This paper is organized as follows. The inversion operation, ternary logic NAND and NOR are discussed in Sections II, III and IV respectively. Section V discuss ternary logic full adder which is followed by the conclusion in Section VI. II Fig.2. Input Output waveform of Ternary Inverter INVERSION OPERATION A ternary inversion is an operation with one input and three outputs. The implementation of ternary inverters requires three inverters: negative ternary inverter (NTI), STI, and positive ternary inverter (PTI) [10]. The truth table for these three inverters is shown in Table I. TABLE I TERNARY INVERTER TRUTH TABLE INPUT STI PTI NTI 0 2 2 2 1 1 2 0 2 0 0 0 The PSPICE schematic STI is shown in Fig.1. This circuit is the same as a conventional CMOS inverter. In this circuit, when the input is 0, the M15 is in the ON state and the M14 is in the OFF state, which makes the output 2. When the input is 2, the M15 is ON and the M14 is OFF, which make the output 0. When Vin is equal to 1, both transistors are in the intermediate mode, thus making both of them behave like a resistor. III TERNARY LOGIC NAND The NAND PSPICE schematic using Ternary logic is shown in Fig.3. The circuit is similar to the conventional CMOS NAND gate The circuit operation can be explained as follows. When either of the inputs is 0, the output is 2 because at least one of the PTI is ON, thus providing a path to Vdd and at least one of the NTI is OFF, thus cutting off a path to the ground. When both of the inputs are 2, the output is 0 because both NTIs are ON, thus providing a path to the ground. This behavior is identical to that of a conventional CMOS NAND gate. The ternary NAND truth table is shown in Table II. On the other hand, for the undefined output cases in Table II the behavior of the QDGFET NAND gate is shown. When A = 1 and B = 1, all four MOSFETs are in the intermediate region. Both PTIs are operating in saturation and it can also be determined that the B NTI is in the linear region and the A NTI is in the saturation region. TABLE II TERNARY NAND TRUTH TABLE A 0 0 0 1 1 1 2 2 2 B 0 1 2 0 1 2 0 1 2 NAND OUTPUT 2 2 2 2 1 1 2 1 0 Fig.4. Input Output Waveform of Ternary NAND IV TERNARY LOGIC NOR The NOR PSPICE schematic using ternary logic is shown in Fig.5. The circuit is similar to the conventional CMOS NOR gate. The circuit operation can be explained as follows. When either of the inputs is 2, the output is 0 because at least one of the NTI is ON, thus providing a path to the ground and at least one of the PTI is OFF, thus cutting off a path to Vdd. When both of the inputs are 0, the output is 2 because both PTIs are ON thus providing a path to Vdd. This behavior is identical to that of a conventional CMOS NOR gate. The ternary NOR truth table is shown in Table III. TABLE III TERNARY NOR TRUTH TABLE Fig.3. PSPICE Schematic of Ternary NAND A B NOR OUTPUT 0 0 2 0 1 1 0 2 0 1 0 1 1 1 1 1 2 0 2 0 0 2 1 0 2 2 0 following half adder adds the sum output from the previous half adder with the carry input (Cin) and generates one sum bit and one carry bit in its output. The final carry bit (Cout) is generated by the OR operation between the two carry bits generated from the two stages (first half adder and the second half adder). Fig.8 shows the input output waveforms of the designed ternary full adder circuit. Table IV shows the corresponding truth table. TABLE IV TERNARY FULL ADDER TRUTH TABLE Fig.5. PSPICE Schematic of Ternary NOR Fig.6. Input Output Waveform of Ternary NOR V TERNARY FULL ADDER A ternary full adder adds two ternary numbers and accounts for values carried in as well as out. A 1-bit full adder adds three 1-bit numbers, often written as A, B, and Cin, A and B are the operands, and Cin is a bit carried in. The circuit produces a 2-bit output sum typically represented by the signals Cout and S. A ternary full adder can be implemented by cascading two ternary half adder circuits. Fig.7 shows the ternary full adder block diagram based on two ternary half adders. Here the first half adder adds 2 bits. The A B CIN SUM CARRY 0 0 0 0 0 0 0 1 1 0 0 0 2 2 0 0 1 0 1 0 0 1 1 2 0 0 1 2 0 1 0 2 0 2 0 0 2 1 0 1 0 2 2 1 1 1 0 0 1 0 1 0 1 2 0 1 0 2 0 1 1 1 0 2 0 1 1 1 0 1 1 1 2 1 1 1 2 0 0 1 1 2 1 1 1 1 2 2 2 1 2 0 0 2 0 2 0 1 0 1 2 0 2 1 1 2 1 0 0 1 2 1 1 1 1 2 1 2 2 1 2 2 0 1 1 2 2 1 2 1 2 2 2 0 2 Fig.7. PSPICE Schematic of Ternary Full Adder [1] Balla P. C. and Antoniou A., 1984, Low power dissipation MOS ternary logic family, IEEE J. Solid-State Circuits, vol. 19, no. 5, pp. 739–749. [2] F. Capasso and R. A. Kiehl, 1985, Resonant tunneling transistor with quantum well base and high-energy injection: A new negative differential resistance device, J. Appl. Phys., vol. 58, no. 3, pp. 1366–1368. [3] A. C. Seabaugh, W. R. Frensley, J. N. Randall, M. A. Reed, D. L. Farrington, and R. J. Matyi, 1989, Pseudomorphic bipolar quantum resonant tunneling transistor, IEEE Transactions Electron Devices, vol. 36, no. 10, pp. 2328–2334. [4] W. Kruppa and J. B. Boos, 1992, Observation of DC and microwave negative differential resistance in InAlAs/InGaAS/InP HEMTs, Electron. Lett., vol. 28, no. 3, pp. 267–269. [5] H. C. Lin, 1994, Resonant tunneling diodes for multi-valued digital applications, Proc. 24th IEEE Int. Symp. Multiple-Valued Logic , pp. 188–195. [6] T. Waho, 1995, Resonant tunneling transistor and its application to multiple-valued logic circuits, Proc. 25th Int. Symp. Multiple-Valued Logic, pp. 130–138. [7] D. Bimberg, M. Grundmann, N. N. Ledentsov, S. S. Ruvimov, P. Werner, U. Richter, J. Heydenreich, V. M. Ustinov, P. S. Kop’ev, and Z. I. Alferov, 1995, Self-organization processes in MBE-grown quantum dot structures, Thin Solid Films, vol. 267, nos. 1–2, pp. 32–36. [8] Takao Waho, Kevin J. Chen, and Masafumi Yamamoto, 1998, Resonant-Tunneling Diode and HEMT Logic Circuits with Multiple Thresholds and Multilevel Output, IEEE Journal of Solid State Circuits, vol. 33, no. 2. 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