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International Journal of Electrical, Electronics and Computer Systems (IJEECS)
________________________________________________________________________________________________
Performance analysis of Multi Walled Carbon Nanotube interconnect
for future VLSI applications
1
Mohit, 2Mayank Kumar Rai
Electronics and Communication Dept.
Thapar University Patiala, India
Email: [email protected], [email protected]
Abstract—This paper compares the performance in terms
of delay and power of Multi Walled Carbon Nanotubes
(MWCNT)based interconnects at 22nm technology node.
Similar analysis is carried out for copper based
interconnect and results are compared with MWCNT at
different interconnect lengths. This analysis shows that due
to low resistance and inductance MWCNT bundle
interconnect is of lower delay and power than copper
interconnect. Results further reveal that the MWCNT
gives noticeable improvement in delay for semi global and
global length of interconnect.
Index Terms—CNT,VLSI,MWCNT, interconnect, scaling.
I. INTRODUCTION
With the scaling of technology the feature size is
decreasing and along with it the width of interconnects
is also decreasing. This causes performance degradation
in copper as we move further in deep-submicron level
due to electro-migration and grain boundary effect. Thus
to maintain the speed of interconnects with the
increasing speed of transistors in the IC, a substitute has
to be used for copper. Carbon nanotubes are one such
potential substitute for copper as has been proposed by
some researchers [1].
Carbon nanotubes (CNTs) are graphene sheets rolled up
into hollow cylinders [2]. CNTs exhibit extraordinary
strength and unique electrical properties and are good
conductors of heat. These can be classified as single
walledcarbon nanotubes (SWCNTs) and multi-walled
carbon nanotubes (MWCNTs). SWCNT has only one
shell with diameter ranging from 0.33 to 5.0nm and
lengths from 2 to10nm, whereas MWCNT has several
concentric shells with diameter ranging from several
nanometers to tens of nanometers and length of several
microns. Each shell of MWCNT can have different
chirality depending on the direction they are rolled up,
which implies that the shells in MWCNT are metallic or
semiconducting [3].
Until recently MWCNTs had not been reported to
exhibit conductance values comparable to SWCNT,
thus, were considered to less desirable than SWCNTs
for interconnect applications. This can be attributed to
the fact that in the early experiments, only the outermost
shell in MWCNTs was contacted with metal, whereas
the inner shells were isolated from the contact, and
therefore had little effect on the conductance [4].
Multi-walled CNTs have large diameter of shells due to
which the shells are conducting even if they are
semiconducting because at room temperature the energy
gap between the Fermi level and Conduction band edge
(EC) is smaller than 0.0258 eV. Moreover, due to large
density of states in large diameter shells, this energy gap
is very small even if it exceeds 0.0258 eV. The electrons
in these sub-bands have reasonable probability (fi) to
appear at Ef following the Fermi-Dirac distribution
function. As the MWCNT have many large diameter
shells, they can have large number of conducting
channels [4],[8],[9].
The purpose of this paper is to analyze how the
performance of MWCNT varies with length of
interconnect. This paper is organized in five sections.
CNT equivalent circuits and impedance parameters are
described and discussed in section II. Impedance
parameters and analyzed in section III. SPICE
simulation results are presented and analyzed in section
IV. Finally conclusions are drawn in section V.
II. IMPEDANCE PARAMETERS
The impedance parameters of MWCNT interconnect are
calculated by first calculating the impedance parameters
for an individual shell of an isolated MWCNT, then for
an isolated MWCNT and then for the MWCNT bundle.
A MWCNT bundle is formed by combination of parallel
MWCNTs.
A. Isolated MWCNT shell
An isolated MWCNT at a height ‘y’ above the ground
plane is shown in Fig. 1.Equivalent distributed circuit
model of an individual shell where Rmc is the imperfect
contact resistance, RQ is the quantum contact resistance,
RS is the scattering-induced resistance, LK and LM are the
kinetic and magnetic inductances, respectively, and
________________________________________________________________________________________________
ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014
5
International Journal of Electrical, Electronics and Computer Systems (IJEECS)
________________________________________________________________________________________________
CQand CE are the quantum and electrostatic
capacitances, respectively is shown in Fig. 2. The
impedance parameters of a bundle can be obtained from
the mathematical expressions given in the literature [5].
B. Isolated MWCNT[4]
The number of shells p for a MWCNT with outermost
diameter Dmax and innermost shell diameter Dmin is
formulated as:
p = 1 + inter [
Dmax − Dmin
]
2d
(1)
where d=0.34nm.
The kinetic inductance per unit length per shell is given
by:
The diameter of i’th shell of MWCNT is given by:
Di = Dmax − 2d(i − 1)
(2)
The number of conducting channels of the i’th shell is
given by:
Nshell (Di ) = aDi + b
(4)
The magnetic inductance of a nanotube present at a
distance yfrom the ground plane per unit length of i’th
shell is given by:
µ
y
log( )
The kinetic inductance per channel is given by:
Lk channel
h
= 2
4e vf
CQ channel =
4e2
hvf
(8)
The quantum capacitance per unit length per shell is
given by:
(5)
Di
(7)
The quantum capacitance present due to electrostatic
energy stored in CNT when it carries a current per
channel is given by:
The mean free path of the i’th shell is given by [6]:
2π
Lk channel
aDi + b
(3)
where a=0.0612nm and b=0.425.
Lm =
Lk shell =
The effective inductance LEFF of the MWCNT
interconnect can be obtained from the series-parallel
combination of the kinetic inductance and magnetic
inductance elements.
-1
λo = 1000Di
Figure 3. Equivalent distributed circuit model of
MWCNT with p shells [8].
CQ shell = CQ channel (aDi + b)
(6)
(9)
The electrostatic capacitance present between the
ground plane and the outermost shell is given by:
2πϵ
CE =
log (
y
Dmax
)
(10)
The shell to shell capacitance is given by:
Cs =
Figure 1. An isolated MWCNT above a ground plane
[4].
2πϵ
ln(Dout − Din)
(11)
The net effective capacitance Ceff can be obtained by the
parallel and series combinations of quantum
capacitance, shell to shell coupling capacitances and
electrostatic capacitances of individual shells.
The resistance per unit length for the i’th shell can be
obtained using Eq. (12), where h is the Planck’s
constant, λ0is the mean free path of electron in the shell,
Nshellis the number of conducting channels of the shell.
RS =
h
2e2 N
1
( )
shell λ0
(12)
C. MWCNT bundle
Figure 2. Equivalent circuit of an isolated MWCNT
shell [8].
The number of MWCNTs in a bundle of width ‘w’ and
height ‘y’ is given by
wy
nCNT =
(13)
Dmax ∗ Dmax
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ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014
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International Journal of Electrical, Electronics and Computer Systems (IJEECS)
________________________________________________________________________________________________
R CNT
nCNT
(14)
The net effective capacitance of the MWCNT bundle
can be obtained from the Eq.
Cbundle = nCNT ∗ Ceff
(15)
The net effective inductance of the MWCNT bundle can
be obtained from the Eq.
LCNT =
LEFF
nCNT
(16)
Table I shows the data used for the calculations of
MWCNT impedance parameters. For the sake of
comparison the impedance parameters of copper
interconnect are also determined.
III. IMPEDANCE ANALYSIS
The resistance, inductance and capacitance of the
MWCNT interconnect increase as the length of the
interconnect increases. Similar effect occurs in copper.
This leads to the increase in propagation delay of
interconnect with increase in length of interconnect. The
impedance parameters of interconnect affect its delay and
power dissipation. Thus the variation in length of
interconnect affects the performance of interconnect.
TABLE I. SIMULATION PARAMETERS
Parameters
Width(nm)
A/R
ILD
Thickness(nm)
KILD
Global
32
3
Semi global & local
22
2
76.8
39.6
2.05
2.05
IV. INFLUENCE OF LINE LENGTH ON
DELAY AND POWER DISSIPATION
The equivalent circuit of interconnect formed by CNT
bundle is used to SPICE-simulate signal propagation
down the MWCNT interconnect for 22nm technology
node at different lengths. The clock speed is 100MHz.
Simulation is carried out for copper interconnects for
same technology and lengths at the same clock speed.
For the sake of comparison the load capacitance is kept
same for both the cases. Optimum number of repeaters
has been found out to get the optimum performance for
both MWCNT and copper. Optimum driver size of
repeaters is also found to get optimum performance for
both MWCNT and copper. Length of interconnect is
varied in the range of both semi global and global levels.
A. Propagation Delay
The 90% delay has been extracted for both MWCNT and
copper interconnects using SPICE simulation results.
Predictive Technology Model (PTM) has been used for
CMOS driver [7]. Copper interconnect propagation delay
B. Power dissipation
The ratio of power dissipation in MWCNT and copper
interconnects at different line lengths has been illustrated
in Fig.5. It has been seen that the MWCNT is of lower
power dissipation for all semi global and global length
interconnect. Result also reveals that the ratio increases
with increase in interconnect length.
C. Figures and Tables
Fig. 6 shows Power Delay product PDP as a function of
line length. It is observed that PDP decreases nominally
because the decrease in propagation delay is little but
more dominating than increase in power dissipation.
This is attributed to the fact that decrease in resistance is
more prominent than increase in capacitance.
V. CONCLUSION
The performance of MWCNT interconnect is examined
in this paper. SPICE simulation is used to compare the
performance in terms of delay and power dissipation of
MWCNT interconnect with that of copper interconnect.
Results show that MWCNT gives better performance
compared to copper for semi global and global lengths of
interconnects.
0.7
Delay Ratio (MWCNT/Cu)
R eff =
is used to normalize corresponding MWCNT delays.
This ratio will be referred to as normalized delay from
now on. The variation of this normalized delay with line
length is shown in Fig. 4. It is observed that the
normalized delay decreases with increase in interconnect
length. This is due to the lower value of MWCNT
resistance and inductance compared to copper
counterpart.
0.6
0.5
0.4
0.3
0.2
0.1
6E-16
-0.1
Length of interconnect (µm)
Figure 4. Variation in delay ratio as a function of line
length.
Power Ratio (MWCNT/Cu)
The net effective resistance of MWCNT bundle is given
by:
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400um 500um 600um 700um 800um 900um 1000um
Length of interconnect (µm)
Fig. 5. Variation in power dissipation as a function of
line length.
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ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014
7
International Journal of Electrical, Electronics and Computer Systems (IJEECS)
________________________________________________________________________________________________
multi-walled carbon nanotube interconnects,” IEEE
Trans. Electron Devices, vol. 55, no. 6, pp. 13281337, June 2008.
0.4
0.35
0.3
[5] P. J. Burke, “Luttinger Liquid theory as a model of
Gigahertz electrical properties of CNTs,” IEEE
Trans. Nanotechnology, vol 1, ed 3, pp. 129-144,
2002.
PDP
0.25
0.2
0.15
0.1
0.05
0
400um 500um 600um 700um 800um 900um 1000um
Length of interconnect
Fig. 6. PDP as a function of line length.
REFERENCES
[1] M. K. Rai and S. Sarkar, Chapter 2, “Carbon Nano
Tube as VLSI interconnect,” Electronic Property of
Carbon Nano Tube, June 2011.
[2] M. K. Rai and S. Sarkar, “Influence of tube
diameter on carbon nano tube interconnect delay
and power output,” PSS A 208, pp. 735-739,
January 2011.
[3] N. Srivastava and K. Banerjee, “Performance
analysis of CNT interconnects for VLSI
applications,” IEEE/ACM Intl. conf. on
ICCAD,pp.383–390, 2005.
[6] H. Li, C. Xu, N. Srivastava and K. Banerjee,
“Carbon Nanomaterials for next generation
interconnects and Passives: Physics, Status and
Prospects,” IEEE Trans. Electron Devices, vol. 56,
no. 9, Septermber 2009.
[7] Predictive Technology Model [Online] Available:
www.eas.asu.edu/~ptm/
[8] N. Srivastava and K. Banerjee, “A comparative
scaling analysis of metallic and carbon nanotube
interconnections
for
nanometer
scale
VLSItechnologies,” in Proc. 21st Int. VLSI
Multilevel Interconnect Conf.Sep. 2004, pp. 393–
398.
[9]
[4] H. Li, W. Y. Yin, K. Banerjee and J. F. Mao,
“Circuit modelling and performance analysis of

A. Naeemi, J. D. Meindl, “Performance Modeling
for Single- and Multiwall Carbon Nanotubes as
Signal and Power Interconnects in Gigascale
Systems,” IEEE Trans on Electron Devices, vol.
55, no. 10, October 2008.
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