Download Digital Logic Gates

‫درس مدارهاي‬
‫منطقي ديجيتال‬
‫مرجع‪ :‬مدارهاي منطقي ديجيتال‬
‫نوشته‪ :‬مانو‪ --‬مترجم‪:‬دكتر سپيدنام‬
‫سيستم ده دهي اعداد )‪:(Decimal‬‬
‫‪ ‬آشنايي پيچيدگي را پنهان مي کند؟‬
‫‪‬ده رقم ‪0..9‬‬
‫‪‬موقعيت ‪ ،‬وزن تعيين مي کند‪:‬‬
‫‪... 10 4 103 10 2 101 10 0‬‬
‫‪1 7 3‬‬
‫‪0‬‬
‫‪ 1  10  7  10  3  10‬‬
‫‪ 100  70  3‬‬
‫‪ 173‬‬
‫‪1‬‬
‫‪2‬‬
‫سيستم دودويي‬
‫اعداد)‪:(binary‬‬
‫‪‬آسان براي کامپيوتر ها‪ ,‬ناملموس براي‬
‫ما‬
‫‪‬از ارقام دودويي))‪ ،(binary digits (bits‬به جاي‬
‫ارقام ده دهي استفاده مي کند‪.‬‬
‫‪ n‬بيت داده شده مي تواند نشانگر ‪2^n‬‬
‫عدد باشد‪.‬‬
‫‪‬با ده انگشت مي شود تا ‪ 1023‬شمرد!‬
‫‪‬در اين سيستم نيز از موقعيت‪ ،‬وزن را‬
‫تعيين مي کند‪.‬‬
Dec
0
1
2
3
4
5
6
7
8
23 22 21 20
0
1
1 0
1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 0 0 0
Binary
0
1
10
11
100
101
110
111
1000
‫تبديل از مبناي‬
‫ده به مبناي دو‬
‫روش اول ‪:‬‬
‫تقسيمات متوالي‬
‫‪( 325 )10  ( 101000101 )2‬‬
‫‪2‬‬
‫‪2‬‬
‫‪2‬‬
‫‪2‬‬
‫‪2‬‬
‫‪2‬‬
‫‪1‬‬
‫‪2‬‬
‫‪5‬‬
‫‪2‬‬
‫‪1‬‬
‫‪0‬‬
‫‪20‬‬
‫‪0‬‬
‫‪10‬‬
‫‪0‬‬
‫‪0‬‬
‫‪40‬‬
‫‪2‬‬
‫‪162‬‬
‫‪81‬‬
‫‪1‬‬
‫‪325‬‬
‫‪1‬‬
‫‪0‬‬
‫تبديل از مبناي‬
‫دو به مبناي ده‬
‫‪( 1 0 1 1 1 0 )21 = 0 x 1 + 1 x 2 + 1 x 4 + 1 x 8 + 0 x 16 + 1 x 32 = (46)10‬‬
‫‪25 24 23 22 21 20‬‬
‫فصل ‪2‬‬
‫روش هاي جبري براي تحليل‬
‫و‬
‫طراحي مدارهاي منطقي‬
‫دستگاه هاي ديجيتالي‬
‫‪‬جبر بول‪:‬‬
‫‪ ‬يک عبارت منطقي مي تواند ”درست“ يا ”‬
‫نادرست“ باشد (‪ 0‬يا ‪.)1‬‬
‫‪ ‬شامل فرمول هاي جبري مربوط به ترکيب هاي‬
‫مقادير منطقي است‪.‬‬
‫درسطح سخت افزار‪:‬‬
‫‪ ‬هر عبارت منطقي با يک سيگنال الکتريکي‬
‫نشان داده مي شود‪.‬‬
‫‪ ‬ارزش منطقي هر عبارت با ولتاژ الکتريکي‬
‫سيگنال‪ ،‬مشخص‬
‫مي شود‪.‬‬
‫دستگاه هاي‬
‫مثال‪:‬‬
‫سطح ولتاژ باال‬
‫است‪.‬‬
‫سطح ولتاژ پائين‬
‫است‪.‬‬
‫ديجيتالي(‪)2‬‬
‫عبارت درست‬
‫عبارت نادرست‬
‫‪ ‬عملگرهاي منطقي با گيت هاي منطقي پياده سازي مي شوند‪.‬‬
‫اصول جبر بول‬
‫خاصيت عناصر ‪ +‬و‬
‫‪.‬‬
‫‪x.y y.x x+y y+x‬‬
‫‪x+y=y+x‬‬
‫‪:‬‬
‫‪x.y=y.x‬‬
‫‪y‬‬
‫‪x‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪1‬‬
‫‪1‬‬
‫‪0‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪1‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
)POS) ‫) و ماکسترم ها‬
SOP) ‫مينترم‬
)1(
x
y
z
x+y+z
Minterm
Maxterm
0
0
0
0
0
1
0
1
x’.y’.z’
x’.y’.z
m0
m1
x+y+z
x+y+z’
M0
M1
0
0
1
1
0
1
1
1
x’.y.z’
x’.y.z
m2
m3
x+y’+z
x+y’+z’
M2
M3
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
x.y’.z’
x.y’.z
x.y.z’
x.y.z
m4
m5
m6
m7
x’+y+z
x’+y+z’
x’+y’+z
x’+y’+z’
M4
M5
M6
M7
Digital Logic States
• The Digital Logic Gate is the basic building block from which all digital
electronic circuits and microprocessor based systems are constructed
from. Basic digital logic gates perform logical operations
of AND, OR and NOT on binary numbers.
• In digital logic design only two voltage levels or states are allowed and
these states are generally referred to as Logic “1” and Logic
“0”, High and Low, or True and False. These two states are represented
in Boolean Algebra and standard truth tables by the binary digits
of “1” and “0”respectively.
Boolean Algebra
Boolean Logic
Voltage State
Logic “1”
True (T)
High (H)
Logic “0”
False (F)
Low (L)
hakim sabzevaru university - edited by Arash khajooei
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• Most digital logic gates and digital logic systems use “Positive logic”, in
which a logic level “0” or “LOW” is represented by a zero voltage, 0v
or ground and a logic level “1” or “HIGH” is represented by a higher
voltage such as +5 volts, with the switching from one voltage level to
the other, from either a logic level “0” to a “1” or a “1” to a “0” being
made as quickly as possible to prevent any faulty operation of the
logic circuit.
• TTL Input & Output Voltage Levels
There are a large variety of logic gate types in both the
bipolar 7400 and the CMOS 4000 families of digital logic
gates such as 74Lxx, 74LSxx, 74ALSxx, 74HCxx, 74HCTxx,
74ACTxx etc, with each one having its own distinct
advantages and disadvantages compared to the other. The
exact switching voltage required to produce either a logic
“0” or a logic “1” depends upon the specific logic group or
family.
hakim sabzevaru university - edited by Arash khajooei
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Ideal Digital Logic Gate Voltage Levels
Where the opening or closing of the switch produces
either a logic level “1” or a logic level “0” with the
resistor R being known as a “pull-up” resistor.
However, when using a standard +5 volt supply any TTL
voltage input between 2.0v and 5v is considered to be a
logic “1” or “HIGH” while any voltage input below 0.8v is
recognised as a logic “0” or “LOW”. The voltage region in
between these two voltage levels either as an input or
as an output is called the Indeterminate Region and
operating within this region may cause the logic gate to
produce a false output.
The CMOS 4000 logic family uses different levels of
voltages compared to the TTL types as they are
designed using field effect transistors, or FET’s. In CMOS
technology a logic “1” level operates between 3.0 and
18 volts and a logic “0” level is below 1.5 volts.
Then from the above observations, we can define the
ideal Digital Logic Gate as one that has a “LOW” level
logic “0” of 0 volts (ground) and a “HIGH” level logic “1”
of +5 volts and this can be demonstrated as:
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14
)1(
)‫گيت ها(دريچه ها‬
And:
x
y
A
x
y
A=x.y
0
0
0
0
1
0
1
0
0
1
1
1
Logic AND Gate
• A Logic AND Gate is a type of digital logic gate that has an output
which is normally at logic level “0” and only goes “HIGH” to a logic
level “1” when ALL of its inputs are at logic level “1”. The output state
of a “Logic AND Gate” only returns “LOW” again when ANY of its
inputs are at a logic level “0”. In other words for a logic AND gate, any
LOW input will give a LOW output.
• The logic or Boolean expression given for a Digital Logic AND Gate is
that for Logical Multiplication which is denoted by a single dot or full
stop symbol, ( . ) giving us the Boolean expression of: A.B = Q.
“If both A and B are true, then Q is true”
hakim sabzevaru university - edited by Arash khajooei
16
2-input Transistor AND Gate
• A simple 2-input logic AND gate can be constructed using RTL
Resistor-transistor switches connected together as shown below with
the inputs connected directly to the transistor bases. Both transistors
must be saturated “ON” for an output at Q.
Logic AND Gates are available using digital circuits to
produce the desired logical function and is given a symbol
whose shape represents the logical operation of the AND
gate.
hakim sabzevaru university - edited by Arash khajooei
17
Digital Logic “AND” Gate Types
Because the Boolean expression for the logic AND function is
defined as (.), which is a binary operation, AND gates can be
cascaded together to form any number of individual inputs.
However, commercial available AND gate IC’s are only
available in standard 2, 3, or 4-input packages. If additional
inputs are required, then standard AND gates will need to be
cascaded together to obtain the required input value, for
example.
hakim sabzevaru university - edited by Arash khajooei
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• Multi-input AND Gate
The Boolean Expression for this 6-input AND gate will
therefore be: Q = (A.B).(C.D).(E.F)
If the number of inputs required is an odd number of
inputs any “unused” inputs can be held HIGH by
connecting them directly to the power supply using
suitable “Pull-up” resistors.
• 7408 Quad 2-input AND Gate
TTL Logic AND Gates
CMOS Logic AND Gates
74LS08 Quad 2-input
74LS11 Triple 3-input
74LS21 Dual 4-input
CD4081 Quad 2-input
CD4073 Triple 3-input
CD4082 Dual 4-input
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‫گيت ها(دريچه ها)‬
‫‪A=x+y‬‬
‫‪y‬‬
‫‪x‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪1‬‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
‫(‪)1‬‬
‫‪Or:‬‬
‫‪B‬‬
‫‪x‬‬
‫‪y‬‬
Logic OR Gate Definition
• A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that
has an output which is normally at logic level “0” and only goes
“HIGH” to a logic level “1” when one or more of its inputs are at logic
level “1”. The output, Q of a “Logic OR Gate” only returns “LOW”
again when ALL of its inputs are at a logic level “0”. In other words for
a logic OR gate, any “HIGH” input will give a “HIGH”, logic level “1”
output.
• The logic or Boolean expression given for a Digital Logic OR Gate is
that for Logical Addition which is denoted by a plus sign, ( + ) giving us
the Boolean expression of: A+B = Q.
“If either A or B is true, then Q is true”
hakim sabzevaru university - edited by Arash khajooei
21
2-input Transistor OR Gate
• A simple 2-input logic OR gate can be constructed using RTL Resistortransistor switches connected together as shown below with the
inputs connected directly to the transistor bases. Either transistor
must be saturated “ON” for an output at Q.
Logic OR Gates are available using digital circuits to
produce the desired logical function and is given a
symbol whose shape represents the logical
operation of the OR gate.
hakim sabzevaru university - edited by Arash khajooei
22
Digital Logic “OR” Gate Types
Like the AND gate, the OR function can have any number of
individual inputs. However, commercial available OR gates
are available in 2, 3, or 4 inputs types. Additional inputs will
require gates to be cascaded together for example.
hakim sabzevaru university - edited by Arash khajooei
23
• Multi-input OR Gate
The Boolean Expression for this 6-input OR gate will therefore
be: Q = (A+B)+(C+D)+(E+F)
If the number of inputs required is an odd number of inputs
any “unused” inputs can be held LOW by connecting them
directly to ground using suitable “Pull-down” resistors.
7432 Quad 2-input Logic OR Gate
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‫گيت ها‬
‫(‪)2‬‬
‫تقويت کننده‪:‬‬
‫‪x‬‬
‫‪x‬‬
‫مت ّمم‪:‬‬
‫’‪x‬‬
‫‪x‬‬
‫’‪x‬‬
‫‪1‬‬
‫‪x‬‬
‫‪0‬‬
‫‪0‬‬
‫‪1‬‬
Logic NOT Gate
• Logic NOT Gate Definition
• The digital Logic NOT Gate is the most basic of all the logical gates and
is sometimes referred to as an Inverting Buffer or simply a Digital
Inverter. It is a single input device which has an output level that is
normally at logic level “1” and goes “LOW” to a logic level “0” when
its single input is at logic level “1”, in other words it “inverts”
(complements) its input signal. The output from a NOT gate only
returns “HIGH” again when its input is at logic level “0” giving us the
Boolean expression of: A = Q.
“If A is NOT true, then Q is true”
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26
Transistor NOT Gate
• A simple 2-input logic NOT gate can be constructed using a RTL
Resistor-transistor switches as shown below with the input connected
directly to the transistor base. The transistor must be saturated “ON”
for an inverted output “OFF” at Q.
Logic NOT Gates are available using digital circuits to produce the desired
logical function. The standard NOT gate is given a symbol whose shape is of a
triangle pointing to the right with a circle at its end. This circle is known as an
“inversion bubble” and is used in NOT, NAND and NOR symbols at their
output to represent the logical operation of the NOT function. This bubble
denotes a signal inversion (complementation) of the signal and can be
present on either or both the output and/or the input terminals.
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The Logic NOT Gate Truth Table
Logic NOT gates provide the complement of their input
signal and are so called because when their input signal is
“HIGH” their output state will NOT be “HIGH”. Likewise,
when their input signal is “LOW” their output state will NOT
be “LOW”. As they are single input devices, logic NOT gates
are not normally classed as “decision” making devices or
even as a gate, such as the AND or OR gates which have two
or more logic inputs. Commercial available NOT gates IC’s
are available in either 4 or 6 individual gates within a single
IC package.
The “bubble” (o) present at the end of the NOT
gate symbol above denotes a signal inversion
(complementation) of the output signal. But this
bubble can also be present at the gates input to
indicate an active-LOW input. This inversion of the
input signal is not restricted to the NOT gate only
but can be used on any digital circuit or gate as
shown with the operation of inversion being exactly
the same whether on the input or output terminal.
The easiest way is to think of the bubble as simply
an inverter.
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)3(
Nand:
x
y
x
A
x
y
A
0
0
0
0
1
0
1
0
0
1
1
1
‫گيت ها‬
Logic NAND Gate
• The Logic NAND Gate is a combination of the digital logic AND gate with that of
an inverter or NOT gate connected together in series. The NAND (Not – AND) gate
has an output that is normally at logic level “1” and only goes “LOW” to logic level
“0” when ALL of its inputs are at logic level “1”. The Logic NAND Gate is the
reverse or “Complementary” form of the AND gate we have seen previously.
The logic or Boolean expression given for a logic NAND gate is that
for Logical Addition, which is the opposite to the AND gate, and which
it performs on the complements of the inputs. The Boolean expression
for a logic NAND gate is denoted by a single dot or full stop symbol,
( . ) with a line orOverline, ( ‾‾ ) over the expression to signify
the NOT or logical negation of the NAND gate giving us the Boolean
expression of: A.B = Q.
“If either A or B are NOT true, then Q is true”
hakim sabzevaru university - edited by Arash khajooei
30
Transistor NAND Gate
• A simple 2-input logic NAND gate can be constructed using RTL
Resistor-transistor switches connected together as shown below with
the inputs connected directly to the transistor bases. Either transistor
must be cut-off “OFF” for an output at Q.
Logic NAND Gates are available using digital circuits to
produce the desired logical function and is given a symbol
whose shape is that of a standard AND gate with a circle,
sometimes called an “inversion bubble” at its output to
represent the NOT gate symbol with the logical operation
of the NAND gate given as.
hakim sabzevaru university - edited by Arash khajooei
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The Digital Logic “NAND” Gate
As with the AND function seen previously, the NAND function
can also have any number of individual inputs and
commercial available NAND Gate IC’s are available in
standard 2, 3, or 4 input types. If additional inputs are
required, then the standard NAND gates can be cascaded
together to provide more inputs for example.
hakim sabzevaru university - edited by Arash khajooei
32
• A 4-input NAND Function
The Boolean Expression for this 4-input logic NAND gate will therefore
be: Q = A.B.C.D
If the number of inputs required is an odd number of inputs any
“unused” inputs can be held HIGH by connecting them directly to the
power supply using suitable “Pull-up” resistors.
The Logic NAND Gate function is sometimes known as the Sheffer
Stroke Function and is denoted by a vertical bar or upwards arrow
operator, for example, A NAND B = A|B or A↑B.
• The “Universal” NAND Gate
The Logic NAND Gate is generally classed as a
“Universal” gate because it is one of the most
commonly used logic gate types. NAND gates can
also be used to produce any other type of logic gate
function, and in practice the NAND gate forms the
basis of most practical logic circuits. By connecting
them together in various combinations the three
basic gate types of AND, OR and NOTfunction can
be formed using only NAND‘s, for example.
hakim sabzevaru university - edited by Arash khajooei
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7400 Quad 2-input Logic NAND Gate
TTL Logic NAND Gates
74LS00 Quad 2-input
74LS10 Triple 3-input
74LS20 Dual 4-input
74LS30 Single 8-input
CMOS Logic NAND Gates
CD4011 Quad 2-input
CD4023 Triple 3-input
CD4012 Dual 4-input
hakim sabzevaru university - edited by Arash khajooei
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)3(
Nor:
x
A
‫گيت ها‬
x
y
A
0
0
1
0
1
0
1
0
0
1
1
0
y
x
Logic NOR Gate
• The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital
logic OR gate with that of an inverter or NOT gate connected together in series.
The NOR (Not – OR) gate has an output that is normally at logic level “1” and only
goes “LOW” to logic level “0” when ANY of its inputs are at logic level “1”.
The Logic NOR Gate is the reverse or “Complementary” form of the OR gate we
have seen previously.
The logic or Boolean expression given for a
logic NOR gate is that for Logical Multiplication which it
performs on the complements of the inputs. The
Boolean expression for a logic NOR gate is denoted by
a plus sign, ( + ) with a line or Overline, ( ‾‾ ) over the
expression to signify the NOT or logical negation of
the NOR gate giving us the Boolean expression
of: A+B = Q.
“If both A and B are NOT true, then Q is true”
hakim sabzevaru university - edited by Arash khajooei
36
Transistor NOR Gate
• A simple 2-input logic NOR gate can be constructed using RTL
Resistor-transistor switches connected together as shown below with
the inputs connected directly to the transistor bases. Both transistors
must be cut-off “OFF” for an output at Q.
Logic NOR Gates are available using digital circuits to produce the
desired logical function and is given a symbol whose shape is that of a
standard OR gate with a circle, sometimes called an “inversion bubble”
at its output to represent the NOT gate symbol with the logical
operation of theNOR gate given as.
hakim sabzevaru university - edited by Arash khajooei
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The Digital Logic “NOR” Gate
As with the OR function, the NOR function
can also have any number of individual
inputs and commercial available NOR Gate
IC’s are available in standard 2, 3, or 4 input
types. If additional inputs are required, then
the standard NOR gates can be cascaded
together to provide more inputs for example.
hakim sabzevaru university - edited by Arash khajooei
38
• A 4-input NOR Function
The Boolean Expression for this 4-input NOR gate will
therefore be: Q = A+B+C+D
If the number of inputs required is an odd number of inputs
any “unused” inputs can be held LOW by connecting them
directly to ground using suitable “Pull-down” resistors.
The Logic NOR Gate function is sometimes known as
the Pierce Function and is denoted by a downwards
arrow operator as shown, A↓B.
The “Universal” NOR Gate
Like the NAND gate seen in the last section,
the NOR gate can also be classed as a
“Universal” type gate. NOR gates can be used to
produce any other type of logic gate function just
like the NANDgate and by connecting them
together in various combinations the three basic
gate types of AND,OR and NOT function can be
formed using only NOR‘s, for example.
hakim sabzevaru university - edited by Arash khajooei
39
7402 Quad 2-input NOR Gate
TTL Logic NOR Gates
74LS02 Quad 2-input
74LS27 Triple 3-input
74LS260 Dual 4-input
CMOS Logic NOR Gates
CD4001 Quad 2-input
CD4025 Triple 3-input
CD4002 Dual 4-input
hakim sabzevaru university - edited by Arash khajooei
40
)4(
Xor:
x
y
A
x
y
A
0
0
0
0
1
1
1
0
1
1
1
0
‫گيت ها‬
The Digital Logic “Exclusive-OR” Gate
The truth table above shows that the output of an Exclusive-OR
gate ONLY goes “HIGH” when both of its two input terminals are
at “DIFFERENT” logic levels with respect to each other. If these
two inputs, A and B are both at logic level “1” or both at logic level
“0” the output is a “0” making the gate an “odd but not the even
gate”.
This ability of the Exclusive-OR gate to compare two logic levels
and produce an output value dependent upon the input condition
is very useful in computational logic circuits as it gives us the
following Boolean expression of:
Q = (A O B) = A.B + A.B
The logic function implemented by a 2-input Ex-OR is given as
either: “A OR B but NOT both” will give an output at Q. In general,
an Ex-OR gate will give an output value of logic “1” ONLY when
there are an ODD number of 1’s on the inputs to the gate, if the
two numbers are equal, the output is “1”.
Then an Ex-OR function with more than two inputs is called an
“odd function” or modulo-2-sum (Mod-2-SUM), not an Ex-OR.
This description can be expanded to apply to any number of
individual inputs as shown below for a 3-input Ex-OR gate.
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The symbol used to denote an Exclusive-OR odd
function is slightly different to that for the
standard Inclusive-OR Gate. The logic or Boolean
expression given for a logic OR gate is that of
logical addition which is denoted by a standard plus
sign.
The symbol used to describe the Boolean
expression for an Exclusive-OR function is a plus
sign, ( + ) within a circle ( Ο ). This exclusive-OR
symbol also represents the mathematical “direct
sum of sub-objects” expression, with the resulting
symbol for an Exclusive-OR function being given
as: (
).
We said previously that the Ex-OR function is not a
basic logic gate but a combination of different logic
gates connected together. Using the 2-input truth
table above, we can expand the Ex-OR function
to: (A+B).(A.B) which means that we can realise
this new expression using the following individual
gates.
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7486 Quad 2-input Exclusive-OR Gate
The Exclusive-OR logic function is a very useful circuit that can be used in many different
types of computational circuits. Although not a basic logic gate in its own right, its
usefulness and versatility has turned it into a standard logical function complete with its
own Boolean expression, operator and symbol. The Exclusive-OR Gate is widely
available as a standard quad two-input 74LS86 TTL gate or the 4030B CMOS package.
One of its most commonly used applications is as a basic logic comparator which
produces a logic “1” output when its two input bits are not equal. Because of this, the
exclusive-OR gate has an inequality status being known as an odd function. In order to
compare numbers that contain two or more bits, additional exclusive-OR gates are
needed with the 74LS85 logic comparator being 4-bits wide.
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)4(
Xnor:
x
A
x
y
A
0
0
0
0
1
0
1
0
0
1
1
1
y
‫گيت ها‬
Exclusive-NOR Gate
• The Exclusive-NOR Gate function or Ex-NOR for short, is a digital logic gate that is the reverse or complementary form of
the Exclusive-OR function we look at in the previous tutorial. Basically the “Exclusive-NOR Gate” is a combination of the
Exclusive-OR gate and the NOT gate but has a truth table similar to the standard NOR gate in that it has an output that is
normally at logic level “1” and goes “LOW” to logic level “0” when ANY of its inputs are at logic level “1”.
• However, an output “1” is only obtained if BOTH of its inputs are at the same logic level, either binary “1” or “0”. For
example, “00” or “11”. This input combination would then give us the Boolean expression of: Q = A.B + A.B
• In other words, the output of a Digital Logic Exclusive-NOR Gate ONLY goes “HIGH” when its two input terminals, A and B
are at the “SAME” logic level which can be either at a logic level “1” or at a logic level “0”. An even number of logic “1’s” on
its inputs gives a logic “1” at the output. Then this type of gate gives and output “1” when its inputs are “logically equal” or
“equivalent” to each other, which is why an Exclusive-NOR gate is sometimes called an Equivalence Gate.
• The logic symbol for an Exclusive-NOR gate is simply an Exclusive-OR gate with a circle or “inversion bubble”, ( ο ) at its
output to represent the NOT function. Then the Logic Exclusive-NOR Gate is the reverse or “Complementary” form of the
Exclusive-OR gate
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The Digital Logic “Ex-NOR” Gate
The logic function implemented by a 2input Ex-NOR gate is given as “when both
A AND B are the SAME” will give an output
at Q. In general, an Exclusive-NOR gate
will give an output value of logic “1” ONLY
when there are an EVEN number of 1’s on
the inputs to the gate (the inverse of
the Ex-OR gate) except when all its inputs
are “LOW”.
Then an Ex-NOR function with more than
two inputs is called an “even function” or
modulo-2-sum (Mod-2-SUM), not an ExNOR. This description can be expanded to
apply to any number of individual inputs as
shown below for a 3-input ExclusiveNOR gate.
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Ex-NOR Gate Equivalent Circuit
Ex-NOR Function Realisation using NAND gates
One of the main disadvantages of implementing the ExNOR function above is that it contains three different
types logic gates the AND, NOT and finally an OR gate
within its basic design. One easier way of producing
the Ex-NOR function from a single gate type is to
use NAND gates as shown below. Ex-NOR gates are used
mainly in electronic circuits that perform arithmetic
operations and data checking such
as Adders, Subtractors or Parity Checkers, etc. As the ExNOR gate gives an output of logic level “1” whenever its
two inputs are equal it can be used to compare the
magnitude of two binary digits or numbers and so ExNOR gates are used in Digital Comparator circuits.
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74266 Quad 2-input Ex-NOR Gate
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‫فصل ‪3‬‬
‫خصوصيات توابع سوييچي‬
‫جدول کارنا‬
‫براي ساده سازي توابع با حداکثر ‪ 6‬ورودي‪ ،‬ميتوان‬
‫از جدول کارنا استفاده کرد‪.‬‬
‫در اين روش جدولي با توجه به تعداد ورودي ها در‬
‫نظر گرفته ميشود؛ و به هر مينترم يک خانه از اين‬
‫جدول اختصاص ميابد‪.‬‬
‫جدول کارنا براي ‪ 3‬ورودي‬
‫)‪f(x,y,z‬‬
‫‪yz‬‬
‫‪10‬‬
‫‪11‬‬
‫‪01‬‬
‫‪00‬‬
‫‪2‬‬
‫‪3‬‬
‫‪1‬‬
‫‪0‬‬
‫‪0‬‬
‫‪6‬‬
‫‪7‬‬
‫‪5‬‬
‫‪4‬‬
‫‪1‬‬
‫‪x‬‬
‫جدول کارنا براي ‪ 4‬ورودي‬
‫)‪f(x,y,z,t‬‬
‫‪zt‬‬
‫‪10‬‬
‫‪11‬‬
‫‪01‬‬
‫‪00‬‬
‫‪xy‬‬
‫‪2‬‬
‫‪3‬‬
‫‪1‬‬
‫‪0‬‬
‫‪6‬‬
‫‪7‬‬
‫‪5‬‬
‫‪4‬‬
‫‪01‬‬
‫‪14‬‬
‫‪15‬‬
‫‪13‬‬
‫‪12‬‬
‫‪11‬‬
‫‪10‬‬
‫‪11‬‬
‫‪9‬‬
‫‪8‬‬
‫‪10‬‬
‫‪00‬‬
‫جدول کارنا براي ‪5‬‬
‫ورودي (‪)1‬‬
‫)‪f(x,y,z,t,e‬‬
‫‪zte‬‬
‫‪100‬‬
‫‪101‬‬
‫‪111‬‬
‫‪110‬‬
‫‪010‬‬
‫‪011‬‬
‫‪001‬‬
‫‪000‬‬
‫‪4‬‬
‫‪5‬‬
‫‪7‬‬
‫‪6‬‬
‫‪2‬‬
‫‪3‬‬
‫‪1‬‬
‫‪0‬‬
‫‪12‬‬
‫‪13‬‬
‫‪15‬‬
‫‪14‬‬
‫‪10‬‬
‫‪11‬‬
‫‪9‬‬
‫‪8‬‬
‫‪28‬‬
‫‪29‬‬
‫‪31‬‬
‫‪30‬‬
‫‪26‬‬
‫‪27‬‬
‫‪25‬‬
‫‪24‬‬
‫‪11‬‬
‫‪20‬‬
‫‪21‬‬
‫‪23‬‬
‫‪22‬‬
‫‪18‬‬
‫‪19‬‬
‫‪17‬‬
‫‪16‬‬
‫‪10‬‬
‫‪xy‬‬
‫‪00‬‬
‫‪01‬‬
‫ساده سازي توابع با کمک‬
‫جدول کارنا‬
‫‪.1‬رسم جدول کارنا با توجه به سايزها‬
‫‪.2‬آوردن مينترم ها داخل جدول کارنا‬
‫‪.3‬تعيين ‪cube‬‬
‫‪.4‬تبديل ‪ cube‬ها به شکل جبري‬
‫اصول ساده سازي کارنا‬
‫انتخاب‪ cube‬در صورتي درست است که کليه شرايط زير برقرار باشد‪:‬‬
‫‪ cube .1‬قابل بزرگتر شدن نباشد‪.‬‬
‫‪.2‬حداقل يک ‪ 1‬در ‪cube‬موجود باشد که در هيچ ‪cube‬ديگري شرکت نکرده باشد‪.‬‬
Algorithm (1)
 1.count
the number of adjacencies for each minterm on the k-map.
 2.select an uncovered minterm with the fewest number of adjacencies.
 3. generate a prime implicant, select the one that covers the most
uncovered minterms.
4.Repeat step 2 & 3 until all minterms have been covered
‫مثالي براي جدول کارنا‬
f(x,y,z,t,e)=
m(2,4,5,6,7,8,9,10,11,12,13,15,16,18,22,24,25,27,28,29,31)
zte
xy
000
001
011
00
01
11
10
1
1
1
1
1
1
1
010
110
111
101
100
1
1
1
1
1
1
1
1
1
1
1
1
1
1
f(x,y,z,t,e)= xyz+ x’yz’ + xz’t’e’ + ye + yt’+ y’te’
Line tracking sensors and algorithms
• Line tracking is a very important notion in the world of robotics as it give to the robot a precise,
error-less and easy to implement navigation scheme.
• As you may have seen, many robotics competitions promote this concept, by adding lines on the
playground for the robot to follow, or sometimes, the sole purpose of the competition is to race
with other robots following a line along a track.
• Number of cells in a sensor
• As you can see in picture, a line sensor is composed of a number cells and each cell is composed of
a sender and a receiver. The particularity of this sender/receiver pair, is that it sends light that shall
be reflected by the line to be detected but not by the eventually opaque background surrounding
this line. Any sender/receiver pair that is able to make a difference between a line and the rest of
ground (of a different color) can be used in a line sensor.Usually, to make it easier on the designer
of the sensor, there is an important contrast between the line and the ground (for example: white
line on a dark blue ground), But in case there isn’t enough contrast, there is a method to easily
build a line sensor adapted to that specific situation, relying on old physics rules that states that a
colored surface will absorb the light of different colors, and reflect the light of the same color. For
example, If you want to build a line sensor to detect white lines drawn on a light blue floor, you can
send red light, as the blue will absorb all of it, and the white line will reflect all of it. Actually this
was the case in the playground of Robocon 2007 competition, there wasn’t enough contrast
between the white lines and the blue ground, so we had to use RED LEDs as senders instead of our
preferred IR LEDs
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• So the first aspect that affects the precision and the quality of a line sensor, is the number of cells.
Some roboticists use only two cells to know whether the line is at the left or at the right of the robot,
but as you shall see later in the software part, this very poor source of information wont allow the
controller to gradually guide the robot back on the track, instead you will notice that the robot will
keep brutally turning right and left, but will never be able to smoothly follow the line. On the other
hand, an eight cells line sensor will give a spectrum of relatively rich information to the controller,
indicating whether the robot is very close to the line, close, far, or very far away. This variety of
information will allow the controller to take actions that are proportional to the distance between the
robot and the line, resulting in a smooth line tracking system.
• Distance between the cells
• The second aspect the be considered when building a line sensor, is the cell spacing (or the distance
between a cell and the other). To understand the effect of cells spacing, consider the differential drive
robot shown in right figure, with an eight cells line sensor, whose cells are numbered from 1 to 8 (from
the left to the right). Three different situations are shown, In the first one, the cells 4 and 5 detect the
line, indicating that the robot is perfectly centered on the line. In the first situation, the spacing
between the cells is not very critical, but if the robot accidentally makes a 10° turn away from the line
(second situation), you will notice that only the cell number 6 detect the line, which is the only
indication that the controller will have about that 10° error. This means that, most probably, an error
smaller than 10° wont even be noticed.But in the third situation, the cells are closely collated together,
and you can notice that with the same 10° deviation from the line, the sensor’s cells 6 and 7 detected
the line, leaving some other possible states in between the perfectly centered position and the 10°
deviation. In other words, the closer are the cells from each others, the more will be the resolution of
the sensor.The same effect can be observed by changing the distance between the sensor and the
center of steering. In general, It is important to always try to keep the sensor as far as possible from
the center of steering, which is the back of the robot in a differential steering one, because this will
also help to amplify the deviation detected by the sensor, resulting in a better response from the
controller.
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Karnaugh map
• The Karnaugh map, also known as the K-map, is a method to simplify boolean algebra expressions. Maurice
Karnaugh introduced it in 1953 as a refinement of Edward Veitch's 1952 Veitch diagram. The Karnaugh map
reduces the need for extensive calculations by taking advantage of humans' pattern-recognition capability. It
also permits the rapid identification and elimination of potential race conditions.
• The required boolean results are transferred from a truth table onto a two-dimensional grid where the cells
are ordered in Gray code, and each cell position represents one combination of input conditions, while each
cell value represents the corresponding output value. Optimal groups of 1s or 0s are identified, which
represent the terms of a canonical form of the logic in the original truth table.These terms can be used to
write a minimal boolean expression representing the required logic.
• Karnaugh maps are used to simplify real-world logic requirements so that they can be implemented using a
minimum number of physical logic gates. A sum-of-products expression can always be implemented
using AND gates feeding into an OR gate, and a product-of-sums expression leads to OR gates feeding an
AND gate.Karnaugh maps can also be used to simplify logic expressions in software design. Boolean
conditions, as used for example in conditional statements, can get very complicated, which makes the code
difficult to read and to maintain. Once minimised, canonical sum-of-products and product-of-sums
expressions can be implemented directly using AND and OR logic operators.
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Following are two different notations describing the same function in unsimplified Boolean algebra, using the
Boolean variables A, B, C, D, and their inverses.
where mi are the minterms to map (i.e., rows that have output 1 in the truth table).
where Mi are the maxterms to map (i.e., rows that have output 0 in the truth table).
A
B
C
D
f(A, B, C, D)
0
0
0
0
0
0
1
0
0
0
1
0
2
0
0
1
0
0
3
0
0
1
1
0
4
0
1
0
0
0
5
0
1
0
1
0
6
0
1
1
0
1
7
0
1
1
1
0
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Line follower navigation with Karnaugh map
A
B
C
D
f1 f2
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
0
1
0
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• F1 is the Control function of MOTOR 1
F2 is the Control function of MOTOR 2
• Note : when the F1 Function Minterms is “1” the motor 1 is turn on and if the the
minterm of F2 is “0” then the motor 2 is off also.
If F1 and F2 is “1” with each other the motor 1 and 2 is working together.
F1 function
karnagh map
0
0
0
0
0
0
1
0
F=ABC’+CDA’B
0
1
0
0
0
0
0
0
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F1=ABC’+CDA’B
C
A
C
D
B
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